CN115312458A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN115312458A
CN115312458A CN202110494944.9A CN202110494944A CN115312458A CN 115312458 A CN115312458 A CN 115312458A CN 202110494944 A CN202110494944 A CN 202110494944A CN 115312458 A CN115312458 A CN 115312458A
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Prior art keywords
mask
material layer
side wall
fin
forming
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Chinese (zh)
Inventor
赵君红
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110494944.9A priority Critical patent/CN115312458A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a substrate and a first fin material layer on the substrate, and the first fin material layer comprises a first device area and a second device area; forming a core layer on the first fin material layer of the first device region; forming a first mask side wall on the side wall of the core layer; etching the first fin part material layer by taking the first mask side wall and the core layer as masks to form an initial fin part; forming a second fin material layer on the substrate with the exposed initial fin part, wherein the second fin material layer is different from the first fin material layer in material; removing the core layer after the second fin material layer is formed; after the core layer is removed, forming a second mask side wall on the side wall of the first mask side wall; removing the first mask side wall; and after removing the first mask side wall, etching the initial fin portion and the second fin portion material layer by taking the second mask side wall as a mask, wherein the initial fin portion is patterned into a first fin portion, and the second fin portion material layer is patterned into a second fin portion. The invention selects different fin materials to meet the performance requirements of different devices.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Transistors are currently being widely used as one of the basic semiconductor devices. Therefore, with the increase of the density and the integration of the semiconductor device, the size of the gate of the planar transistor is shorter and shorter, the control capability of the conventional planar transistor on channel current is weakened, a short channel effect occurs, leakage current is increased, and the electrical performance of the semiconductor device is affected finally.
In order to better accommodate the reduction in feature size, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). However, in the case of further reduction in feature size, it is difficult to further improve the performance of the finfet.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor structure, which improves the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a first fin material layer located on the substrate, and the base comprises a first device area used for forming a first transistor and a second device area used for forming a second transistor; forming a core layer on the first fin material layer of the first device region; forming a first mask side wall on the side wall of the core layer; etching the first fin part material layer by taking the first mask side wall and the core layer as masks, and forming a raised initial fin part on the residual substrate of the first device region; forming a second fin material layer on the residual substrate exposed out of the initial fin portion, wherein the second fin material layer covers the side wall of the initial fin portion, and the second fin material layer and the first fin material layer are made of different materials; after the second fin material layer is formed, removing the core layer; after the core layer is removed, forming a second mask side wall on the side wall of the first mask side wall; removing the first mask side wall; and after removing the first mask side walls, etching the initial fin part and the second fin part material layer by taking the second mask side walls as masks, patterning the initial fin part into a first fin part protruding on the substrate of the first device region, and patterning the second fin part material layer into a second fin part protruding on the substrate of the second device region.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the forming method provided by the embodiment of the invention, the second fin material layer and the first fin material layer are made of different materials, the initial fin portion and the second fin material layer are etched by using the second mask side wall as a mask, the initial fin portion is patterned into a first fin portion protruding on the substrate of the first device region, and the second fin material layer is patterned into a second fin portion protruding on the substrate of the second device region; in this embodiment, the first fin portion and the second fin portion are made of different materials, so that different fin portion materials can be selected in a targeted manner, and the first fin portion and the second fin portion can be used for meeting performance requirements of the first transistor and the second transistor respectively, so as to improve performances of different transistors, and further, the working performance of the semiconductor structure can be improved.
Drawings
Fig. 1 to fig. 14 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As is apparent from the background art, with the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and it is difficult for current semiconductor structures to further improve the operating performance in the situation of further reduction of feature size, and it is difficult to satisfy different requirements for different transistors in a targeted manner.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a first fin material layer located on the substrate, and the base comprises a first device region used for forming a first transistor and a second device region used for forming a second transistor; forming a core layer on the first fin material layer of the first device region; forming a first mask side wall on the side wall of the core layer; etching the first fin part material layer by taking the first mask side wall and the core layer as masks, and forming a raised initial fin part on the residual substrate of the first device region; forming a second fin material layer on the residual substrate exposed out of the initial fin portion, wherein the second fin material layer covers the side wall of the initial fin portion, and the second fin material layer and the first fin material layer are made of different materials; after the second fin material layer is formed, removing the core layer; after the core layer is removed, forming a second mask side wall on the side wall of the first mask side wall; removing the first mask side wall; and after removing the first mask side wall, etching the initial fin part and the second fin part material layer by using the second mask side wall as a mask, patterning the initial fin part into a first fin part protruding on the substrate of the first device area, and patterning the second fin part material layer into a second fin part protruding on the substrate of the second device area.
In the forming method provided by the embodiment of the invention, the second fin material layer and the first fin material layer are made of different materials, the initial fin portion and the second fin material layer are etched by using the second mask side wall as a mask, the initial fin portion is patterned into a first fin portion protruding on the substrate of the first device region, and the second fin material layer is patterned into a second fin portion protruding on the substrate of the second device region; in this embodiment, the first fin portion and the second fin portion are made of different materials, so that different fin portion materials can be selected in a targeted manner, and the first fin portion and the second fin portion can be used for meeting performance requirements of the first transistor and the second transistor respectively, so as to improve performances of different transistors, and further, the working performance of the semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 14 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Referring to fig. 1, a base (not labeled) including a substrate 100 and a first fin material layer 110 on the substrate 100 is provided, and the base includes a first device region 100A for forming a first transistor and a second device region 100B for forming a second transistor.
The substrate provides a process operation basis for the formation process of the semiconductor structure. The semiconductor structure comprises a fin field effect transistor.
In this embodiment, the base includes a substrate 100 and a first fin material layer 110 on the substrate 100, where the first fin material layer 110 is used to form a first fin and a second fin in the following step.
In this embodiment, the substrate 100 is made of silicon, in other embodiments, the substrate may also be made of one or more of germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or another type of substrate such as a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.
In the present embodiment, the material of the first fin material layer 110 includes silicon, germanium, silicon germanium, or iii-v semiconductor material.
In this embodiment, the first fin material layer 110 and the substrate 100 are an integral structure. In other embodiments, the first fin material layer may also be a semiconductor layer epitaxially grown on the substrate, so as to precisely control the height of the first fin material layer.
In this embodiment, the material of the first fin material layer 110 is the same as the material of the substrate 100, and the material of the first fin material layer 110 is silicon. In other embodiments, the material of the first fin material layer may also be different from the material of the substrate to meet the requirement of the first fin material layer for the material.
In this embodiment, the substrate includes a first device region 100A for forming a first transistor and a second device region 100B for forming a second transistor, which have different channel conductivity types.
As an example, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.
In this embodiment, a first mask material layer 200 is further formed on the top of the first fin material layer 110.
The first masking material layer 200 is used for the subsequent formation of a first masking layer.
In this embodiment, the material of the first mask material layer 200 includes one or more of silicon oxide and silicon nitride, that is, the first mask material layer 200 may have a single-layer structure or a stacked-layer structure. As an example, the material of the first mask material layer 200 is silicon oxide and silicon nitride, that is, the first mask material layer 200 is a stacked structure and includes a silicon nitride material layer 210 and a silicon oxide material layer 220 covering the silicon nitride material layer 210.
With continued reference to fig. 1, a core layer 300 is formed on the first fin material layer 110 of the first device region 100A.
Specifically, the core layer 300 is formed on the first mask material layer 200 of the first device region 100A.
The core layer 300 provides support for forming a first mask sidewall on the sidewall of the core layer 300.
The core layer 300 is subsequently removed, so that the material of the core layer 300 is easily removed, thereby reducing the difficulty of removing the core layer 300 and reducing the damage to other film layers below the core layer 300. Accordingly, the material of the core layer 300 includes one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, advanced Patterning Film (APF) material, spin On Carbon (SOC), and silicon carbide. In this embodiment, the core layer 300 is an advanced graphic film material.
Referring to fig. 2 and 3 in combination, first mask side walls 410 are formed on the side walls of the core layer 300.
The first mask sidewall 410 is used for being used as an etching mask for etching the first fin material layer 110 together with the core layer 300 in the following, and the first mask sidewall 410 is also used for providing support for forming a second mask sidewall on the sidewall of the first mask sidewall 410 in the following.
The first mask sidewall 410 is made of a material having an etching selectivity with the core layer 300, and in this embodiment, the material of the first mask sidewall 410 includes silicon nitride.
Specifically, referring to fig. 2, the step of forming the first mask sidewall spacers 410 includes: a first mask sidewall material layer 400 is formed conformally covering the top and sidewalls of the core layer 300 and the top of the first fin material layer 410.
The first mask sidewall material layer 400 is used to form a first mask sidewall 410.
In this embodiment, the first mask sidewall material layer 400 is formed by an atomic layer deposition process.
The first mask side wall material layer 400 formed by the atomic layer deposition process has good thickness uniformity and good step coverage (step coverage) capability, so that the first mask side wall material layer 400 can well conformally cover the top and the side walls of the core layer 300 and the top of the first fin material layer 410.
In this embodiment, the material of the first mask sidewall spacer material layer 400 includes silicon nitride, which is used to directly form the first mask sidewall spacer 410.
Referring to fig. 3, the first mask sidewall material layer 400 on the top of the core layer 300 and on the top of the first fin material layer 110 is removed, and the first mask sidewall material layer 400 on the sidewall of the core layer 300 is remained as a first mask sidewall 410.
The first mask side wall material layer 400 on the top of the core layer 300 and the top of the first fin material layer 110 is removed to prepare for subsequent pattern transfer by using the side wall 350 and the core layer 300 as etching masks, and the top surface of the core layer 300 can be better exposed, so that the process difficulty of subsequently removing the core layer 300 is reduced.
In this embodiment, the first mask sidewall material layer 400 on the top of the core layer 300 and on the top of the first fin material layer 110 is removed by a dry etching process.
The dry etching process has anisotropic etching characteristics, so that the dry etching process is selected to be beneficial to reducing damage to the first fin material layer 110, and meanwhile, the dry etching process has etching directionality and is beneficial to improving the sidewall morphology quality and the dimensional accuracy of the first mask sidewall 410.
Referring to fig. 4, the first fin material layer 110 is etched using the first mask sidewall 410 and the core layer 300 as masks, and a raised initial fin 130 is formed on the remaining substrate of the first device region 100A.
The raised initial fin portion 130 is used for forming a first fin portion subsequently, and the remaining substrate exposed by the raised initial fin portion 130 is used for forming a second fin portion material layer subsequently.
In this embodiment, before the step of etching the first fin material layer 110, the method further includes: and etching the first mask material layer 200 by using the first mask sidewall 410 and the core layer 300 as masks to form a first mask layer 250.
Correspondingly, the first fin material layer 110 is etched by using the first mask layer 250 as a mask, so as to form the initial fin 130.
In this embodiment, the first mask layer 250 includes a silicon nitride layer 230 and a silicon oxide layer 240 covering the silicon nitride layer 230.
In this embodiment, in the step of etching the first fin material layer 110, a portion of the thickness of the first fin material layer 110 is removed.
After a second Fin material layer is subsequently formed on the remaining substrate exposed from the initial Fin portion 130, the second Fin material layer is also etched, and the patterned second Fin material layer is used for forming a second Fin portion, and usually, only a Fin portion with a partial height in the Fin portion is used as an effective Fin portion (effective Fin), that is, the second Fin portion with the partial height in the second Fin portion does not play a role of an effective Fin portion, so that it is ensured that the second Fin portion with the partial height used as the effective Fin portion is formed by using the second Fin material layer in the second Fin portion, in this embodiment, the first Fin material layer 110 with a partial thickness is removed, the second Fin portion with the partial height used as the effective Fin portion is provided, and the first Fin material layer 110 with the remaining partial thickness is reserved for subsequent formation without being used as an effective Fin portion, so that the etching amount of the first Fin material layer 110 is reduced, and the material of the second Fin material layer is saved, thereby saving the process cost and improving the process efficiency.
It should be noted that, in the step of removing the first fin material layer with a partial thickness, the thickness d of the removed first fin material layer with a partial thickness cannot be too large or too small. If the thickness d of the removed part of the first fin material layer is too large, the thickness of the second fin material layer formed subsequently is too large, so that unnecessary process waste is easily caused; if the thickness d of the removed first fin material layer with a partial thickness is too small, the thickness of the subsequently formed second fin material layer is too small, which easily causes the portion of the subsequently formed second fin to contain the material of the first fin material layer 110, which is used as an effective fin, and thus the working performance of the second device region 100B is difficult to satisfy. Therefore, in this embodiment, in the step of removing the partial thickness of the first fin material layer 110, the thickness d of the removed partial thickness of the first fin material layer 110 is equal to
Figure BDA0003053867240000071
To
Figure BDA0003053867240000072
In this embodiment, in the step of etching the first fin material layer 110, the first fin material layer 110 is etched by using a dry etching process.
The dry etching process has the characteristic of anisotropic etching, so that the dry etching process is selected, the etching amount is favorably controlled, the damage to the residual substrate is reduced, and meanwhile, the dry etching process has higher etching directionality and is favorable for improving the sidewall appearance quality and the size precision of the formed raised initial fin portion 130.
Referring to fig. 5, a second fin material layer 120 is formed on the remaining substrate exposed by the initial fin 130, the second fin material layer 120 covers the sidewalls of the initial fin 130, and the second fin material layer 120 and the first fin material layer 110 are made of different materials.
In the following, the first fin material layer 110 is used to form a first fin portion, and the second fin material layer 120 is used to form a second fin portion, and a portion of the second fin portion, which is used as an effective fin portion, is provided.
In this embodiment, in the step of forming the second fin material layer 120 on the remaining substrate where the initial fin 130 is exposed, the second fin material layer 120 covers the remaining thickness of the first fin material layer 110.
In this embodiment, in the step of forming the second fin material layer 120, an epitaxial growth process is used to form the second fin material layer 120.
The epitaxial growth process can well control process parameters, has high process controllability, is easy to obtain a precise film thickness dimension, and is easy to form a film with less impurities, so that the quality of the second fin material layer 120 is high.
In the present embodiment, in the step of forming the second fin material layer 120, the material of the second fin material layer 120 includes silicon, germanium, silicon germanium, or a iii-v semiconductor material. As an example, in the present embodiment, the material of the second fin material layer 120 is silicon germanium.
Specifically, in this embodiment, the first transistor is an NMOS transistor, the second transistor is a PMOS transistor, the first fin material layer 110 is used to form an effective fin portion of the NMOS transistor, the second fin material layer 120 is used to form an effective fin portion of the PMOS transistor, the first fin material layer 110 is made of silicon, the second fin material layer 120 is made of silicon germanium, and the silicon germanium formed is likely to generate a large compressive stress due to a large lattice constant of germanium element, so that the silicon germanium can provide a large compressive stress as the material of the second fin material layer 120, and the second fin material layer 120 is used to form an effective fin portion of the PMOS transistor, and the large compressive stress is beneficial to improve the hole mobility of the PMOS region, thereby being beneficial to improve the working performance of the semiconductor structure.
With combined reference to fig. 6 and 7, after forming the second fin material layer 120 on the remaining substrate where the initial fin 130 is exposed, the method further includes: a second mask layer 270 is formed on the top of the second fin material layer 120, the second mask layer 270 covers the sidewall of the first mask layer 250, and the second mask layer 270 is flush with the top of the first mask layer 250.
The second mask layer 270 is used for being used as an etching mask for forming a first fin portion and a second fin portion together with the first mask layer 250 in a follow-up mode, and the tops of the second mask layer 270 and the first mask layer 250 are flush with each other, so that a relatively flat process platform is provided for a follow-up forming process.
In this embodiment, the material of the second mask layer 270 includes silicon oxide.
Specifically, referring to fig. 6, the step of forming a second mask layer 270 on top of the second fin material layer 120 includes: a second mask material layer 260 covering the sidewalls of the first mask layer 250, the sidewalls of the first mask sidewalls 410 and the top of the core layer 300 is formed on the second fin material layer 120.
The second masking material layer 260 is used to form a second masking layer 270.
In this embodiment, the second mask material layer 260 is formed by a chemical vapor deposition process.
The filling property and the coverage property of the chemical vapor deposition process are good, the first mask side walls 410 and the core layer 300 can be filled and covered well, and the second mask material layer 260 formed by the chemical vapor deposition process is good in uniformity, so that a good basis is provided for the subsequent formation of the second mask layer 270.
In this embodiment, the material of the second mask material layer 260 includes silicon oxide, which is used to directly form the second mask layer 270.
Referring to fig. 7, a portion of the thickness of the second mask material layer 260 is etched back, and the second mask material layer 260 covering the sidewalls of the first mask layer 250 remains as a second mask layer 270.
The method for forming the second mask material layer 260, etching back the second mask material layer 260 with partial thickness and forming the second mask layer 270 intersects with a scheme for directly forming the second mask layer 270 can well control process parameters, process controllability is high, and accurate thickness size of the second mask layer 270 is easy to obtain.
In this embodiment, a dry etching process is used to etch back the second mask material layer 260 with a certain thickness.
The dry etching process has anisotropic etching characteristics, so that the dry etching process is selected to be beneficial to reducing damage to the first mask side wall 410, and meanwhile, the dry etching process has etching directionality and is beneficial to improving the appearance quality and the size precision of the formed second mask layer 270.
The core layer 300 also needs to be removed subsequently.
With reference to fig. 8 and 9, after forming the second fin material layer 120, before removing the core layer 300, the method further includes: and forming third mask side walls 510 on the side walls of the first mask side walls 410 facing away from the core layer 300.
The third mask side wall 510 is used for being used as a support for forming a second mask side wall together with the first mask side wall 410 in the following process, and the first fin material layer 110 is etched by using the first mask side wall 410 and the core layer 300 as masks, so that the side wall of the first mask side wall 410 facing away from the core layer 300 is flush with the side wall of the initial fin 130, that is, the side wall of the first mask side wall 410 facing away from the core layer 300 is flush with the interface between the first fin material layer 110 and the second fin material layer 120, in this embodiment, the third mask side wall 510 is formed on the side wall of the first mask side wall 410 facing away from the core layer 300, and then the first mask side wall 410 and the third mask side wall 510 are used together as supports for forming a second mask, so that the second mask side wall is prevented from being formed on the interface between the first fin material layer 110 and the second fin material layer 120 to a great extent, and thus when the second mask is used as a mask to form a first fin portion and a second fin portion, the second fin portion is beneficial to improve the quality of the second fin portion formed at the interface between the first fin portion 110 and the second fin material layer.
In addition, the space between the first fin portion and the second fin portion adjacent to each other subsequently meets the process requirement through the third mask sidewall 510.
In this embodiment, the third mask sidewall 510 is made of a material having an etching selectivity with the core layer 300, and the material of the third mask sidewall 510 includes silicon oxide.
Specifically, referring to fig. 8, the step of forming the third mask sidewall spacers 510 includes: forming a third mask sidewall material layer 500 conformally covering the sidewalls of the first mask sidewall 410 facing away from the core layer 300, the top of the first mask sidewall 410, the top of the core layer 300 and the top of the second fin material layer 120.
The third mask sidewall material layer 500 is used to form a third mask sidewall layer 510.
In this embodiment, the third mask sidewall material layer 500 is formed by using an atomic layer deposition process.
The third mask side wall material layer 500 formed by the atomic layer deposition process has good thickness uniformity and good step coverage (step coverage) capability, so that the third mask side wall material layer 500 can well conformally cover the side wall of the first mask side wall 410 opposite to the core layer 300, the top of the first mask side wall 410, the top of the core layer 300 and the top of the second fin material layer 120.
In this embodiment, the material of the third mask sidewall material layer 500 includes silicon oxide, which is used to directly form the third mask sidewall 510.
Referring to fig. 9, the third mask side wall material layers 500 on the top of the first mask side walls 410, the top of the core layer 300, and the top of the second fin material layer 120 are removed, and the third mask side wall material layers 500 on the side walls of the first mask side walls 410 opposite to the core layer 300 are remained as third mask side walls 510.
The third mask side wall material layer 500 on the top of the first mask side wall 410, the top of the core layer 300, and the top of the second fin material layer 120 is removed to prepare for forming a second mask layer on the side wall of the third mask layer 510 in the following step, and the top surface of the core layer 300 can be better exposed, so that the difficulty in the process of removing the core layer 300 in the following step is reduced.
In this embodiment, the third mask sidewall material layer 500 on the top of the first mask sidewall 410, the top of the core layer 300, and the top of the second fin material layer 120 is removed by a dry etching process.
The dry etching process has anisotropic etching characteristics, so that the damage to the second mask layer 270 is reduced by selecting the dry etching process, and meanwhile, the dry etching process has higher etching directionality, and the improvement of the sidewall morphology quality and the dimensional accuracy of the third mask sidewall 510 is facilitated.
Referring to fig. 10, after the second fin material layer 120 is formed, the core layer 300 is removed.
The core layer 300 is removed to expose the sidewalls of the first mask sidewall 410, in preparation for forming a second mask sidewall.
In this embodiment, the core layer 300 is removed by a wet etching process.
The wet etching process has isotropic etching characteristics, which is beneficial to completely removing the core layer 300, and meanwhile, the wet etching process can provide better etching selectivity, which is beneficial to removing the core layer 300 and simultaneously reducing damage to the first mask side wall 410, the third mask side wall 510, the first mask layer 250 and the second mask layer 270.
Referring to fig. 11 and 12 together, after removing the core layer 300, second mask side walls 610 are formed on the side walls of the first mask side walls 410.
The second mask sidewall 610 is used as an etching mask for subsequently forming the first fin portion and the second fin portion.
In this embodiment, the first mask side wall 410 and the third mask side wall 510 are also removed subsequently, then the second mask side wall 610 is made of a material having etching selectivity with the first mask side wall 410 and the third mask side wall 510, and the material of the second mask layer 610 includes amorphous silicon.
Specifically, referring to fig. 11, the step of forming the second mask sidewall spacers 610 includes: forming a second mask sidewall material layer 600 conformally covering the sidewalls of the first mask sidewall 410, the top of the first mask sidewall 410, and the top of the second fin material layer 120.
The second mask sidewall material layer 600 is used to form a second mask sidewall 610.
In this embodiment, the second mask sidewall material layer 600 is formed by using an atomic layer deposition process.
The second mask side wall material layer 600 formed by the atomic layer deposition process has good thickness uniformity and good step coverage (step coverage) capability, so that the second mask side wall material layer 600 can have a good conformal coverage effect.
In this embodiment, the material of the second mask sidewall spacer material layer 600 includes amorphous silicon, which is used to directly form the second mask sidewall spacers 610.
In this embodiment, since the third mask sidewall 510 is formed on the sidewall of the first mask sidewall 410 facing away from the core layer 300, in the step of forming the second mask sidewall 610 on the sidewall of the first mask sidewall 410, the second mask sidewall 610 covers the sidewall of the first mask sidewall 410 facing away from the third mask sidewall 510 and the sidewall of the third mask sidewall 510 facing away from the first mask sidewall 410.
Correspondingly, in the step of forming the second mask side wall material layer 600, the second mask side wall material layer 600 conformally covers the side wall of the first mask side wall 410 facing away from the third mask side wall 510, the side wall of the third mask side wall 510 facing away from the first mask side wall 410, the tops of the first mask side wall 410 and the third mask side wall 510, and the top of the second fin material layer 120.
Referring to fig. 12, the second mask sidewall material layer 600 on the tops of the first mask sidewall 410 and the third mask sidewall 510 and on the top of the second fin material layer 120 is removed, and the second mask sidewall material layer 600 on the sidewall of the first mask sidewall 410 facing away from the third mask sidewall 510 and the sidewall of the third mask sidewall 510 facing away from the first mask sidewall 410 is reserved as a second mask sidewall 610.
In this embodiment, the second mask sidewall material layer 600 on the tops of the first mask sidewall 410 and the third mask sidewall 510 and on the top of the second fin material layer 120 is removed by using a dry etching process.
The dry etching process has anisotropic etching characteristics, so that the damage to the second mask layer 270 is reduced by selecting the dry etching process, and meanwhile, the dry etching process has etching directionality, and the improvement of the sidewall morphology quality and the size precision of the second mask sidewall 610 is facilitated.
Referring to fig. 13, the first mask sidewall spacers 410 are removed.
The first mask sidewalls 410 are removed in preparation for forming the first fin portion and the second fin portion subsequently using the second mask sidewalls 610 as masks.
In this embodiment, the first mask sidewall 410 is removed by a wet etching process.
The wet etching process has the characteristic of isotropic etching, and is favorable for completely removing the first mask side wall 410, and meanwhile, the wet etching process can provide better etching selectivity, and is favorable for removing the first mask side wall 410 and reducing damage to the second mask side wall 610, the first mask layer 250 and the second mask layer 270.
With reference to fig. 12, after forming the second mask sidewall spacers 610, before etching the initial fin 130, the second fin material layer 120, and the remaining first fin material layer 110 by using the second mask sidewall spacers 610 as masks, the method further includes: the third mask sidewall 510 is removed.
The third mask spacers 510 are removed to prepare for forming the first fin portion and the second fin portion subsequently using the second mask spacers 610 as masks.
In this embodiment, the third mask sidewall 510 is removed by a wet etching process.
The wet etching process has the characteristic of isotropic etching, and is favorable for completely removing the third mask side wall 510, and meanwhile, the wet etching process can provide better etching selectivity, and is favorable for removing the third mask side wall 510 and simultaneously reducing the damage to the second mask side wall 610, the first mask layer 250 and the second mask layer 270.
Referring to fig. 14, after removing the first mask sidewalls 410, etching the initial fin portion 130 and the second fin portion material layer 120 by using the second mask sidewalls 610 as masks, patterning the initial fin portion 130 into a first fin portion 700 protruding from the substrate 100 in the first device region 100A, and patterning the second fin portion material layer 120 into a second fin portion 800 protruding from the substrate 100 in the second device region 100B.
The first fin portion 700 is used for forming a channel of a first transistor, the second fin portion 800 is used for forming a channel of a second transistor, and different materials are adopted to form channels of different transistors, so that the performance requirements of the first transistor and the performance requirements of the second transistor can be met, the performances of different transistors can be improved, and the working performance of the semiconductor structure can be improved.
In this embodiment, the first fin 700 is made of silicon and is used to form a channel of an NMOS transistor, and the second fin 800 is made of silicon germanium and is used to form a channel of a PMOS transistor.
In this embodiment, in the process of etching the initial fin 130 and the second fin material layer 120 by using the second mask sidewall 610 as a mask, the second fin material layer 120 with a remaining thickness is further etched, in the first device region 100A, the initial fin 130 and the remaining first fin material layer 110 are patterned to protrude from the first fin 700 on the substrate 100, and in the second device region 100B, the second fin material layer 120 and the remaining first fin material layer 110 are patterned to protrude from the second fin 800 on the substrate 100.
Generally, only fins with a partial height in the fins are used as effective fins, in this embodiment, in the first fin portion 700 formed by patterning the initial fin portion 130, a part of the first fin portion 700 is used as an effective fin portion, and in the second fin portion 800 formed by patterning the second fin portion material layer 120, the second fin portion 800 with the same material as the second fin portion material layer 120 is used to provide an effective fin portion, so that the process cost is saved, and the process efficiency is improved.
With reference to fig. 14, before etching the initial fin 130 and the second fin material layer 120 by using the second mask sidewall spacers 610 as masks, the method further includes: and etching the first mask layer 250 and the second mask layer 270 by using the second mask sidewall spacers 610 as masks, wherein the remaining first mask layer 250 and the remaining second mask layer 270 are used as fin mask layers 280.
The fin mask layer 280 is used as an etching mask for etching the initial fin 130 and the second fin material layer 120.
Therefore, in this embodiment, in the process of etching the initial fin 130 and the second fin material layer 120 by using the second mask sidewall 610 as a mask, the fin mask layer 280 is also used as a mask.
In the process of etching the initial fin portion 130 and the second fin portion material layer 120 by using the second mask sidewall 610 as a mask, the fin portion mask layer 280 is also used as a mask, which is beneficial to improving the precision of pattern transfer and forming the first fin portion 700 and the second fin portion 800 with higher dimensional precision.
In this embodiment, in the step of etching the initial fin portion 130 and the second fin portion material layer 120 by using the second mask sidewall 610 as a mask, the initial fin portion 130 and the second fin portion material layer 120 are etched by using a dry etching process.
The dry etching process has anisotropic etching characteristics, so that damage to the substrate 100 is reduced by selecting the dry etching process, and meanwhile, the dry etching process has etching directionality, and the sidewall morphology quality and the size precision of the first fin portion 700 and the second fin portion 800 are improved.
It is noted that the fin mask layer 280 is subsequently removed to form a gate structure spanning the first fin 700 and the second fin 800. The description of the subsequent steps is not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a first fin material layer located on the substrate, and the base comprises a first device area used for forming a first transistor and a second device area used for forming a second transistor;
forming a core layer on the first fin material layer of the first device region;
forming a first mask side wall on the side wall of the core layer;
etching the first fin part material layer by taking the first mask side wall and the core layer as masks, and forming a raised initial fin part on the residual substrate of the first device region;
forming a second fin material layer on the residual substrate exposed out of the initial fin portion, wherein the second fin material layer covers the side wall of the initial fin portion, and the second fin material layer and the first fin material layer are made of different materials;
after the second fin material layer is formed, removing the core layer;
after the core layer is removed, forming a second mask side wall on the side wall of the first mask side wall;
removing the first mask side wall;
and after removing the first mask side wall, etching the initial fin part and the second fin part material layer by using the second mask side wall as a mask, patterning the initial fin part into a first fin part protruding on the substrate of the first device area, and patterning the second fin part material layer into a second fin part protruding on the substrate of the second device area.
2. The method of claim 1, wherein in the providing the substrate step, a first masking material layer is further formed on top of the first fin material layer;
before the step of etching the first fin material layer, the method further includes: etching the first mask material layer by taking the first mask side wall and the core layer as masks to form a first mask layer;
after forming a second fin material layer on the remaining substrate with the exposed initial fin, the method further includes: and forming a second mask layer on the top of the second fin material layer, wherein the second mask layer covers the side wall of the first mask layer, and the second mask layer is flush with the top of the first mask layer.
3. The method for forming the semiconductor structure according to claim 2, wherein before etching the initial fin portion and the second fin portion material layer by using the second mask sidewall as a mask, the method further comprises: etching the first mask layer and the second mask layer by taking the second mask side wall as a mask, wherein the remaining first mask layer and the remaining second mask layer are taken as fin mask layers;
and in the process of etching the initial fin part and the second fin part material layer by taking the second mask side wall as a mask, the fin part mask layer is also taken as a mask.
4. The method of forming a semiconductor structure of claim 2, wherein forming a second mask layer on top of the second layer of fin material comprises: forming a second mask material layer covering the side wall of the first mask layer, the side wall of the first mask side wall and the top of the core layer on the second fin material layer;
and etching back the second mask material layer with partial thickness, and reserving the second mask material layer covering the side wall of the first mask layer as a second mask layer.
5. The method of claim 1, wherein after forming the second layer of fin material and before removing the core layer, further comprising: forming a third mask side wall on the side wall of the first mask side wall back to the core layer;
in the step of forming a second mask side wall on the side wall of the first mask side wall, the second mask side wall covers the side wall of the first mask side wall facing away from the third mask side wall and the side wall of the third mask side wall facing away from the first mask side wall;
after the second mask side wall is formed, before the initial fin portion, the second fin portion material layer and the remaining first fin portion material layer are etched by using the second mask side wall as a mask, the method further includes: and removing the third mask side wall.
6. The method for forming the semiconductor structure according to claim 5, wherein the step of forming the third mask sidewall spacers comprises: forming a third mask side wall material layer covering the side wall of the first mask side wall opposite to the core layer, the top of the first mask side wall, the top of the core layer and the top of the second fin material layer in a conformal manner;
and removing the third mask side wall material layers positioned at the top of the first mask side wall, the top of the core layer and the top of the second fin material layer, and reserving the third mask side wall material layer positioned at the side wall of the first mask side wall, which is opposite to the core layer, as a third mask side wall.
7. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the second mask sidewall spacers comprises: forming a second mask side wall material layer conformally covering each side wall of the first mask side wall, the top of the first mask side wall and the top of the second fin material layer;
and removing the second mask side wall material layer positioned at the top of the first mask side wall and the top of the second fin material layer, and reserving the second mask side wall material layer positioned at the side wall of the first mask side wall as a second mask side wall.
8. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the first mask sidewall spacers comprises: forming a first mask side wall material layer which conformally covers the top and the side wall of the core layer and the top of the first fin material layer;
and removing the first mask side wall material layer positioned at the top of the core layer and the top of the first fin material layer, and reserving the first mask side wall material layer positioned at the side wall of the core layer as a first mask side wall.
9. The method of claim 1, wherein in the step of etching the first fin material layer, a portion of the thickness of the first fin material layer is removed;
in the step of forming a second fin material layer on the residual substrate exposed out of the initial fin portion, the second fin material layer covers the first fin material layer with the residual thickness;
and in the process of etching the initial fin part and the second fin part material layer by using the second mask side wall as a mask, etching the second fin part material layer with the rest thickness, in the first device area, patterning the initial fin part and the rest first fin part material layer into a first fin part protruding from the substrate, and in the second device area, patterning the second fin part material layer and the rest first fin part material layer into a second fin part protruding from the substrate.
10. The method of forming a semiconductor structure of claim 9, wherein the removing the partial thickness of the first fin material layer is performed to a thickness of the removed partial thickness of the first fin material layer
Figure FDA0003053867230000031
11. The method for forming a semiconductor structure according to claim 1, wherein in the step of etching the first fin material layer, the first fin material layer is etched by a dry etching process.
12. The method of forming a semiconductor structure of claim 1, wherein the step of forming the second fin material layer comprises forming the second fin material layer using an epitaxial growth process.
13. The method for forming the semiconductor structure according to claim 1, wherein in the step of etching the initial fin portion and the second fin portion material layer by using the second mask sidewall as a mask, the initial fin portion and the second fin portion material layer are etched by using a dry etching process.
14. The method of forming a semiconductor structure of claim 4, wherein the second masking material layer is formed using a chemical vapor deposition process.
15. The method of claim 1, wherein in the step of forming the first fin material layer, a material of the first fin material layer comprises silicon, germanium, silicon germanium, or a group III-V semiconductor material; in the step of forming the second fin material layer, a material of the second fin material layer includes silicon, germanium, silicon germanium, or a group iii-v semiconductor material.
16. The method of forming a semiconductor structure according to claim 1, wherein the step of forming the core layer comprises the materials of amorphous silicon, polycrystalline silicon, single crystal silicon, advanced patterning film materials, spin-on carbon, and silicon carbide.
17. The method for forming a semiconductor structure according to claim 1, wherein in the step of forming the first mask sidewall spacers, the first mask sidewall spacers are made of a material including silicon nitride; in the step of forming the second mask side wall, the material of the second mask side wall comprises amorphous silicon.
18. The method for forming the semiconductor structure according to claim 5, wherein in the step of forming the third mask sidewall spacers, a material of the third mask sidewall spacers comprises silicon oxide.
19. The method of claim 2, wherein in the step of forming the second mask layer, a material of the second mask layer comprises silicon oxide.
20. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, channel conductivity types of the first transistor and the second transistor are different.
CN202110494944.9A 2021-05-07 2021-05-07 Method for forming semiconductor structure Pending CN115312458A (en)

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