CN115911036A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a bottom fin material layer on the substrate, and the substrate comprises a first device area and a second device area; forming a first fin material layer on the bottom fin material layer, wherein the material of the first fin material layer is different from that of the bottom fin material layer; removing the first fin material layer in the second device region to form an opening exposing the top of the bottom fin material layer; forming a second fin material layer in the opening; and performing fin portion patterning treatment, patterning the bottom fin portion material layer into a bottom fin portion, patterning the first fin portion material layer into a first device fin portion protruding from the bottom fin portion of the first device region, and patterning the second fin portion material layer into a second device fin portion protruding from the bottom fin portion of the second device region. The contact surfaces of the formed second device fin portion and the first device fin portion and the bottom fin portion are smooth, and the height consistency of the second device fin portion and the first device fin portion is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Transistors are currently being widely used as one of the basic semiconductor devices. Therefore, as the density and integration of semiconductor devices are increased, the gate size of the planar transistor is shorter and shorter, the control capability of the conventional planar transistor on channel current is weakened, a short channel effect occurs, leakage current is increased, and the electrical performance of the semiconductor device is finally affected.

In order to better accommodate the reduction in feature size, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). However, in the case of further reduction in feature size, it is difficult to further improve the performance of the finfet.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, so as to improve the working performance of the semiconductor structure.

To solve the above problem, an embodiment of the present invention provides a semiconductor structure, including: the transistor comprises a base and a plurality of transistors, wherein the base comprises a substrate, and the substrate comprises a first device area used for forming a first transistor and a second device area used for forming a second transistor; the fin-shaped part is raised on the substrate and comprises a bottom fin part raised on the substrate and a device fin part located on the bottom fin part, the device fin part comprises a first device fin part located in the first device area and a second device fin part located in the second device area, contact surfaces of the device fin part and the bottom fin part are both flat surfaces, and materials of the first device fin part and the bottom fin part are different.

Accordingly, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a bottom fin material layer positioned on the substrate, and the substrate comprises a first device area used for forming a first transistor and a second device area adjacent to the first device area and used for forming a second transistor; forming a first fin material layer on the bottom fin material layer, wherein the material of the first fin material layer is different from that of the bottom fin material layer; removing the first fin material layer positioned in the second device region, reserving the first fin material layer positioned in the first device region, and forming an opening exposing the top of the bottom fin material layer; forming a second fin material layer in the opening; and performing fin imaging treatment, imaging the first fin material layer, the second fin material layer and the bottom fin material layer, imaging the bottom fin material layer into bottom fin portions protruding from the substrate of the first device area and the substrate of the second device area respectively, imaging the first fin material layer into a first device fin portion protruding from the bottom fin portion of the first device area, and imaging the second fin material layer into a second device fin portion protruding from the bottom fin portion of the second device area.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the semiconductor structure provided by the embodiment of the invention, the contact surfaces of the device Fin part and the bottom Fin part are both flat, so that the contact surfaces of the device Fin part and the bottom Fin part are relatively flat, the height consistency of the formed first device Fin part and the second device Fin part can be improved, and the uniformity of the heights of effective Fin parts (effective Fin) of the first transistor and the second transistor is correspondingly improved, thereby being beneficial to ensuring the working performance of the semiconductor structure.

In the forming method provided by the embodiment of the invention, the material of the first fin material layer is different from the material of the bottom fin material layer, so that in the process of removing the first fin material layer located in the second device region, the top surface of the bottom fin material layer can be used as an etching stop surface, so that the sidewall verticality of the opening is higher, and thus the bottom surface flatness of the remaining first fin material layer in the first device region is improved, and correspondingly, the sidewall verticality of the second fin material layer formed in the opening is higher, and the bottom surface flatness of the second fin material layer is also higher, so that after fin patterning processing is performed, the contact surfaces of the formed second device portion and the first device fin portion and the bottom fin portion are smoother, so that the height consistency of the fin portions of the second device portion and the first device fin portion is improved, the uniformity of the effective fin portions of the first transistor and the second transistor is correspondingly improved, and the fin portions of the second device portion are easier to be formed, and the fin portions of different regions are better in depth and better in consistency in the fin portion depth of the second device material layer, and the fin portion material layer can be used for further improving the consistency of the fin portion working performance of the semiconductor device, so that the semiconductor device and the fin portion of the semiconductor device can be further used for improving the consistency of the semiconductor device.

Drawings

Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

FIG. 5 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;

fig. 6 to 21 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.

Detailed Description

The performance of semiconductor structures currently needs to be improved. The reason why the working performance of the semiconductor structure needs to be improved is analyzed in combination with a method for forming the semiconductor structure.

Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a base (not labeled) is provided, and includes a substrate 10 and a first fin material layer 11 located on the substrate 10, where the substrate 10 and the first fin material layer 11 are an integrated structure, and the base includes a first device region 10N for forming a first transistor and a second device region 10P adjacent to the first device region 10N and for forming a second transistor.

The substrate 10 and the first fin material layer 11 are typically formed in the same process, and the substrate 10 and the first fin material layer 11 are made of the same material and have an integral structure.

Referring to fig. 2, the first fin material layer 11 in the second device region 10P is removed to form an opening 23.

Since the substrate 10 and the first fin material layer 11 are made of the same material and have an integral structure, the etching rates of the top and the side of the etching opening 23 are relatively consistent, so that a rounded shape (as shown by a dotted circle in fig. 2) is easily formed at the intersection of the bottom and the sidewall of the opening 23, which results in poor verticality of the sidewall of the opening 23 and poor flatness of the bottom of the opening 23, and in the process of forming the opening 23, the thickness of the first fin material layer 11 removed in each second device region 10P is difficult to be uniform, which results in non-uniform depth of the opening 23 (as shown by a dotted frame in fig. 2, the bottoms of the openings 23 of different second device regions 10P have a height difference).

Referring to fig. 3, a second fin material layer 12 is formed in the opening 23.

The second fin material layer 12 is formed with a poor sidewall verticality and a poor bottom flatness due to the poor sidewall verticality and the poor bottom flatness of the opening 23, and the second fin material layer 12 is formed with a non-uniform thickness due to the non-uniform depth of the opening 23.

Referring to fig. 4, the first fin material layer 11, the second fin material layer 12 and the substrate 10 with a partial thickness are patterned, the substrate 10 with a partial thickness is patterned to protrude from the bottom fin 20 of the remaining substrate 10, the first fin material layer 11 is patterned to protrude from a first device fin 21 of the bottom fin 20 in the first device region 10P, and the second fin material layer 12 is patterned to protrude from a second device fin 22 of the bottom fin 20 in the second device region 10N.

As the sidewall verticality and the bottom surface flatness of the second fin material layer 12 are also poor, the bottom of the second device fin 22 formed is in a radian shape (as shown by a dotted circle in fig. 4), that is, the flatness of the contact surface between the second device fin 22 and the bottom fin 20 is poor, so that the effective fin height uniformity of the second transistor is poor, and the performance of the semiconductor structure is affected.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, where a material of a first fin material layer is different from a material of a bottom fin material layer, and in a process of removing the first fin material layer located in a second device region, a top surface of the bottom fin material layer may be used as an etching stop surface, so that a sidewall of an opening has a higher verticality, thereby improving bottom surface flatness of remaining first fin material layers of the first device region, and accordingly, a sidewall of a second fin material layer formed in the opening has a higher flatness, and a bottom surface of the second fin material layer has a higher flatness, so that after fin patterning, a contact surface between a formed second device fin and the bottom fin is smoother, thereby improving height uniformity of the second device fin and the first device fin, accordingly, improving uniformity of effective fin heights of a first transistor and a second transistor, and further improving working performance uniformity of the second fin in a semiconductor device, and further facilitating formation of the second fin material layer in a semiconductor device, and further improving the performance of the second fin structure.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

FIG. 5 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

The semiconductor structure includes: a base (not labeled) including a substrate 101, the substrate 101 including a first device region 101P for forming a first transistor and a second device region 101N for forming a second transistor; the semiconductor device comprises a fin (not shown) protruding from a substrate 101, the fin comprises a bottom fin 601 protruding from the substrate 101 and a device fin 631 located on the bottom fin 601, the device fin 631 comprises a first device fin 611 located in a P region of a first device 101 and a second device fin 621 located in a second device region 101N, contact surfaces of the device fin 631 and the bottom fin 601 are both planar, and materials of the first device fin 611 and the bottom fin 601 are different.

The substrate provides a process operation basis for a forming process of the semiconductor structure. Wherein the semiconductor structure comprises a fin field effect transistor (FinFET).

In this embodiment, the substrate 101 is made of silicon, in other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate 101 may be a material suitable for process requirements or easy integration.

In this embodiment, the substrate 101 includes a first device region 101P for forming a first transistor and a second device region 101N for forming a second transistor, the first transistor and the second transistor have different channel conductivity types, and the channel conductivity type includes an N type or a P type. As an example, the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

In this embodiment, the substrate further includes: an etch stop layer 111 on the substrate 101; the bottom fin 601 protrudes above the etch stop layer 111.

Generally, the steps of forming the bottom fin 601 and the device fin 631 include: forming a bottom fin material layer (not shown), a first fin material layer (not shown) and a second fin material layer (not shown) on the substrate 101; performing fin imaging processing, imaging the first fin material layer, the second fin material layer and the bottom fin material layer, imaging the bottom fin material layer into bottom fins 601 protruding from the substrate 101 in the first device region 101P and the second device region 101N respectively, imaging the first fin material layer into first device fins 611 protruding from the bottom fins 601 in the first device region 101P, and imaging the second fin material layer into second device fins 621 protruding from the bottom fins 601 in the second device region 101N.

The etching stop layer 111 is used as a stop position for etching the bottom fin material layer during fin patterning, so that after fin patterning, the top surface flatness of the etching stop layer 110 is high, and the overall heights of the first device fin 611 and the bottom fin 601 and the overall heights of the second device fin 621 and the bottom fin 601 are made to be uniform, thereby facilitating the effective fin heights of the first transistor and the second transistor to be uniform, and further facilitating the performance improvement of the semiconductor structure.

In this embodiment, the material of the etch stop layer 111 includes phosphorus-doped silicon, arsenic-doped silicon, carbon-doped silicon, or boron-doped silicon. In this embodiment, the etching stop layer 111 is formed by performing ion implantation on the substrate 101, and the implanted ions include phosphorus, arsenic, carbon, or boron, so that the material of the etching stop layer 111 includes phosphorus-doped silicon, arsenic-doped silicon, carbon-doped silicon, or boron-doped silicon, and the phosphorus-doped silicon, arsenic-doped silicon, carbon-doped silicon, or boron-doped silicon has a higher hardness and can form a higher etching selectivity with the material of the bottom fin 601, thereby achieving a better etching stop effect. In other embodiments, the semiconductor structure may not include the etch stop layer, depending on the actual situation.

In this embodiment, the material of the bottom fin 601 includes silicon, germanium, silicon germanium, or a iii-v semiconductor material. As an example, the material of the bottom fin 601 is the same as the material of the substrate 101, the material of the substrate 101 is silicon, and the material of the bottom fin 601 is also silicon accordingly.

The device fin 631 is to provide a channel of a finfet, wherein the first and second device fins 611 and 621 are to provide channels of first and second transistors, respectively.

Specifically, the first device fin portion 611 includes a first middle fin portion (not labeled) and a first top fin portion (not labeled), and the second device fin portion 621 includes a second middle fin portion (not labeled) and a second top fin portion (not labeled), where the first middle fin portion and the first top fin portion together serve as a channel of the first transistor, where the first middle fin portion includes a sidewall and the first top fin portion includes a sidewall and a top surface that is circular arc shaped, and thus the first middle fin portion and the first top fin portion provide different channel stresses for the first transistor, and correspondingly, the second middle fin portion and the second top fin portion together serve as a channel of the second transistor, where the second middle fin portion includes a sidewall and the second top fin portion includes a top surface that is circular arc shaped, and thus the second middle fin portion and the second top fin portion provide different channel stresses for the second transistor.

In this embodiment, the contact surfaces of the device fin portion 631 and the bottom fin portion 601 are flat surfaces, and then the contact surfaces of the device fin portion 631 and the bottom fin portion 601 are flat, so that the height consistency of the first device fin portion 611 and the second device fin portion 621 can be improved, and the uniformity of the effective fin portions of the first transistor and the second transistor is correspondingly improved, thereby being beneficial to ensuring the working performance of the semiconductor structure.

Specifically, in this embodiment, the step of forming the first fin material layer and the second fin material layer includes: forming a first fin material layer on the bottom fin material layer; removing the first fin material layer in the second device region 101N, and leaving the first fin material layer in the first device region 101P to form an opening (not shown) exposing the top of the bottom fin material layer; and forming a second fin material layer in the opening. In this embodiment, the first device fin portion 611 is made of a different material from the bottom fin portion 601, and thus the first fin portion material layer and the bottom fin portion material layer can have a larger etching selection ratio, so that the bottom fin portion material layer can be used as an etching stop layer to etch the first fin portion material layer in the process of forming the opening, so that the verticality of the side wall and the flatness of the bottom surface of the opening are better, and the flatness of the bottom surface of the remaining first fin portion material layer of the first device region 101P is improved.

In this embodiment, the material of the first device fin 611 includes silicon, germanium, silicon germanium, or a iii-v semiconductor material; the material of the second device fin 621 includes silicon, germanium, silicon germanium, or a iii-v semiconductor material.

In this embodiment, the material of the first device fin 611 is different from that of the second device fin 621, that is, the channel materials of the first transistor and the second transistor are different, specifically, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor, so in this embodiment, the material of the first device fin 611 is silicon germanium, and the material of the second device fin 621 is silicon. The PMOS transistor adopts the device fin part made of the silicon germanium material, so that the channel mobility of the PMOS transistor is improved, and meanwhile, the problem of Negative Bias Temperature Instability (NBTI) of the PMOS transistor is favorably solved, so that the performance of the PMOS transistor is improved.

Therefore, in this embodiment, the material of the bottom fin portion 601 is the same as that of the second device fin portion 621, and meanwhile, the second fin portion material layer is usually formed in the opening by an epitaxial growth process, and the bottom of the opening is the bottom fin portion material layer, so that the material of the bottom fin portion 601 is the same as that of the second device fin portion 621, which is beneficial to the growth of the second fin portion material layer, and the second device fin portion 621 with higher quality is formed. In other embodiments, the material of the bottom fin portion may also be different from the material of the second device fin portion according to process requirements.

In this embodiment, the semiconductor structure further includes: and the isolation layer 121 is located on the etching stop layer 111 and covers the side wall of the bottom fin 601. The isolation layer 121 serves as a Shallow Trench Isolation (STI) structure for isolating adjacent transistors. In this embodiment, the isolation layer 121 covers the sidewalls of the bottom fin 601, so that the first transistor only uses the first device fin 611 as a trench and the second transistor only uses the second device fin 621 as a channel.

In this embodiment, a portion of the device Fin 631 exposed to the isolation layer 121 serves as an effective Fin (effective Fin), that is, a portion of the device Fin 631 exposed to the isolation layer 121 is covered by a device gate structure, and according to actual requirements, the top of the isolation layer 121 is higher than or flush with the bottoms of the first device Fin 611 and the second device Fin 621, that is, the isolation layer 121 exposes the entire sidewalls or partial sidewalls of the first device Fin 611 and the second device Fin 621. As an example, fig. 5 illustrates a case where the top of the isolation layer 121 is flush with the bottoms of the first and second device fins 611 and 621.

In this embodiment, the isolation layer 121 is made of silicon oxide. In other embodiments, the material of the isolation layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

Fig. 6 to 21 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to fig. 6 to 9 in combination, a base (not labeled) is provided, the base including a substrate 100 and a bottom fin material layer 200 on the substrate 100, the substrate 100 including a first device region 100P for forming a first transistor and a second device region 100N adjacent to the first device region 100P for forming a second transistor.

The substrate provides a process operation basis for the formation process of the semiconductor structure. The semiconductor structure comprises a fin field effect transistor.

In this embodiment, the substrate 100 is made of silicon, in other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate 100 may be a material suitable for process requirements or easy integration.

In this embodiment, the substrate 100 includes a first device region 100P for forming a first transistor and a second device region 100N for forming a second transistor, the first and second transistors have different channel conductivity types, and the channel conductivity type includes an N-type or a P-type. As an example, the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

The bottom fin material layer 200 is used for forming a bottom fin portion in a subsequent step, and when the first fin material layer located in the second device region 100N is removed in a subsequent step, the bottom fin material layer 200 is also used as an etching stop layer. In the present embodiment, the material of the bottom fin material layer 200 includes silicon, germanium, silicon germanium or a iii-v semiconductor material. As an example, the material of the bottom fin material layer 200 is the same as the material of the substrate 100, the material of the substrate 100 is silicon, and the material of the bottom fin material layer 200 is also silicon accordingly.

In this embodiment, in the step of providing the base, the base further includes an etching stop layer 110 located between the substrate 100 and the bottom fin material layer 200.

Typically, the subsequent processes further include: forming a first fin material layer on the bottom fin material layer 200 of the first device region 100P, and forming a second fin material layer on the bottom fin material layer 200 of the second device region 100N; performing fin imaging processing, imaging the first fin material layer, the second fin material layer and the bottom fin material layer 200, imaging the bottom fin material layer 200 into bottom fin portions of the substrate 100 protruding from the first device region 100P and the second device region 100N respectively, imaging the first fin material layer into first device fin portions protruding from the bottom fin portion of the first device region 100P, and imaging the second fin material layer into second device fin portions protruding from the bottom fin portion of the second device region 100N.

The etching stop layer 110 is used as a stop position for etching the bottom fin material layer 200 during the fin patterning process, so that after the fin patterning process, the top surface flatness of the etching stop layer 110 is high, and the overall heights of the first device fin and the bottom fin and the overall heights of the second device fin and the bottom fin are good, thereby being beneficial to making the heights of effective fins of the first transistor and the second transistor good in uniformity, and further being beneficial to improving the performance of the semiconductor structure.

Specifically, referring to fig. 6, the step of providing a substrate includes: providing a substrate 100; referring to fig. 7 and 8 in combination, a modification process is performed on the surface of the substrate 100 to convert the substrate 100 with a thickness of a top portion of the substrate 100 into an etch stop layer 110.

In this embodiment, in the step of performing modification treatment on the surface of the substrate 100, an ion implantation process is adopted to convert the substrate with a partial thickness at the top of the substrate 100 into an etching stop layer.

The ion implantation process has the characteristics of uniform large-area ion implantation, more accurate control of ion doping depth and high repeatability. In this embodiment, the thickness of the etching stop layer 110 and the uniformity of the surface of the etching stop layer 110 can be better controlled by using an ion implantation process.

In this embodiment, the implanted ions in the ion implantation process include boron ions, carbon ions, arsenic ions, or phosphorus ions. The implantation of boron ions, carbon ions, arsenic ions or phosphorus ions can form the etching stop layer 110 with high hardness, and the etching stop layer 110 and the material of the bottom fin material layer 200 form a high etching selection ratio, so that a good etching stop effect can be achieved. Therefore, in the present embodiment, the material of the etch stop layer 110 includes phosphorus-doped silicon, arsenic-doped silicon, carbon-doped silicon, or boron-doped silicon.

It should be noted that the implantation energy of the ion implantation process should not be too large or too small. If the implantation energy is too large, the ion implantation range is easily too large, the process is not easy to control, and accordingly, the thickness of the etching stop layer 110 is too large; if the implantation energy is too small, the reaction time of ion implantation is too long, the efficiency of the process is reduced, the thickness of the etching stop layer 110 is affected, and the process effect cannot be achieved. For this reason, in the present embodiment, the implantation energy ranges from 1KeV to 600KeV.

It should be noted that the implantation dose of the ion implantation process should not be too large, nor too small. If the implantation dose is too large, the ion implantation range is easily too large, the process is not easy to control, and accordingly, the thickness of the etching stop layer 110 is too large; if the implantation dose is too small, the reaction time of ion implantation is too long, the efficiency of the process is reduced, the thickness of the etching stop layer 110 is affected, the process effect cannot be achieved, and the etching stop layer 110 is easily close to the etched rate of the substrate 100, so that the etching stop surface for etching the bottom fin material layer 200 is difficult to form during the fin patterning process. For this reason, in the present embodiment, the implantation dose range is 1 × 10 ¹² ions/cm ² To 2X 10 ¹⁸ ions/cm ² . Wherein ions/cm ² Refers to the number of ions per square centimeter.

Referring to fig. 9, a bottom fin material layer 200 is formed on the etch stop layer 110.

In this embodiment, the bottom fin material layer 200 is formed on the substrate 100 by an epitaxial growth process. The epitaxial growth process can better control process parameters, has high process controllability, is easy to obtain a more accurate film thickness dimension, and is easy to form a film with less impurities, so that the bottom fin material layer 200 has high quality.

In this embodiment, after the etch stop layer 110 is formed, the bottom fin material layer 200 is formed on the etch stop layer 110.

It should be noted that, in the present embodiment, the etching stop layer 200 is formed by performing ion implantation on the substrate 100, and compared with depositing a new film layer on the substrate as the etching stop layer, after the etching stop layer 110 is formed in the present embodiment, the material of the etching stop layer 110 is a semiconductor material doped with ions, so that the bottom fin material layer 200 is favorable for performing epitaxial growth on the surface of the etching stop layer 110, and the bottom fin material layer 200 with a high film quality is formed.

It should be further noted that, in this embodiment, ion implantation is performed on the substrate 100 to form the etching stop layer 110, and then the bottom fin material layer 200 is epitaxially grown, compared with a scheme of forming an integrated structure of the substrate and the bottom fin material layer, and then ion implantation is performed to a certain depth to form the etching stop layer in the substrate, in this embodiment, ion implantation is performed before the bottom fin material layer 200 is formed, which is beneficial to reducing or avoiding the influence of an ion implantation process on the bottom fin material layer 200, and ensuring the formation quality of the bottom fin material layer 200, and is beneficial to accurately controlling the doping concentration of ions in the etching stop layer 110, the thickness of the etching stop layer 110, and the formation position of the etching stop layer 110.

In this embodiment, after the bottom fin material layer 200 is formed on the substrate 100 by using an epitaxial growth process, the method further includes: the top surface of the bottom fin material layer 200 is planarized.

Compared with the method of directly forming the bottom fin material layer 200 with the target thickness, in this embodiment, after the bottom fin material layer 200 is epitaxially grown, the bottom fin material layer 200 is planarized, which is beneficial to accurately controlling the thickness of the bottom fin material layer 200, and the planarization process improves the top surface flatness of the bottom fin material layer 200, which is beneficial to improving the height uniformity of the subsequently formed bottom fin.

In other embodiments, the bottom fin material layer and the substrate may be of an integrated structure, that is, the substrate and the bottom fin material layer may be formed in the same process, and then ions may be implanted to a certain depth, so as to implant ions into the substrate, and form an etching stop layer on the top of the substrate.

Referring to fig. 10, a first fin material layer 210 is formed on the bottom fin material layer 200, where a material of the first fin material layer 210 is different from a material of the bottom fin material layer 200.

The first fin material layer 210 is used for subsequent formation of first device fins.

In the embodiment of the present invention, it is further necessary to remove the first fin material layer 210 located in the second device region 100N, form an opening exposing the top of the bottom fin material layer 200, form a second fin material layer in the opening, pattern the first fin material layer 210, the second fin material layer, and the bottom fin material layer 200, where the material of the first fin material layer 210 is different from the material of the bottom fin material layer 200, so that in the process of removing the first fin material layer 210 located in the second device region 100N, the top surface of the bottom fin material layer 200 can be used as an etching stop surface, so that the verticality of the side walls of the opening is higher, and the probability of generating arc morphology at the corner of the opening is reduced, thereby improving the bottom surface flatness of the remaining first fin material layer 210 in the first device region 100P, correspondingly, so that the verticality of the side walls of the second fin material layer formed in the opening is higher, the flatness of the bottom surface of the second fin material layer is also higher, and therefore, after performing fin patterning, the fin portion, the second device region is more uniform in contact with the bottom surface of the fin material layer, thereby improving the uniformity of the fin portion, and the uniformity of the fin structure, and the uniformity of the fin portion, thereby further improving the uniformity of the fin portion of the fin structure, and improving the uniformity of the semiconductor device, and the uniformity of the fin portion, and the uniformity of the fin structure, and the uniformity of the fin portion, thereby, and improving the uniformity of the semiconductor device, and the uniformity of the fin portion, and improving the uniformity of the semiconductor device, the first device fin portion and the second device fin portion can be used for meeting performance requirements of the first transistor and the second transistor respectively, so that the performance of different transistors is improved, and the working performance of the semiconductor structure is further improved.

In this embodiment, the first fin material layer 210 is formed by an epitaxial growth process.

The epitaxial growth process can better control process parameters, has high process controllability, is easy to obtain a more accurate film thickness dimension, and is easy to form a film with less impurities, so that the quality of the first fin material layer 210 is high.

In this embodiment, after the first fin material layer 210 is formed by an epitaxial growth process, the method further includes: a planarization process is performed on the top surface of the first fin material layer 210.

Compared with the method of directly forming the first fin material layer 210 with the target thickness, in this embodiment, after the first fin material layer 210 is epitaxially grown, planarization processing is performed on the first fin material layer 210, so that the thickness of the first fin material layer 210 can be accurately controlled, and the planarization processing improves the flatness of the top surface of the first fin material layer 210, which is beneficial to improving the height uniformity of a subsequently formed first device fin.

In the present embodiment, the material of the first fin material layer 210 includes silicon, germanium, silicon germanium or iii-v semiconductor material.

In this embodiment, the first transistor is a PMOS transistor, and thus the material of the first fin material layer 210 is silicon germanium, so that the material of the subsequently formed first device fin is silicon germanium. The PMOS transistor adopts the device fin part made of the silicon germanium material, so that the channel mobility of the PMOS transistor is improved, and meanwhile, the problem of negative bias temperature instability of the PMOS transistor is favorably solved, so that the performance of the PMOS transistor is improved.

Referring to fig. 11 to 13, the first fin material layer 210 in the second device region 100N is removed, and an opening 230 exposing the top of the bottom fin material layer 200 is formed.

The opening 230 is used to provide a spatial location for the subsequent formation of the second fin material layer.

In this embodiment, the first fin material layer 210 located in the second device region 100N is removed by using a dry etching process. The dry etching process is a dry etching process with anisotropic etching characteristics, which is beneficial to reducing damage to the bottom fin material layer 200, and meanwhile, the dry etching process is more directional, and can improve the sidewall morphology quality and the size precision of the opening 230.

Specifically, the first fin material layer 210 is etched with the top of the bottom fin material layer 200 as an etching stop position.

Specifically, referring to fig. 11 and 12 in combination, the step of removing the first fin material layer 210 in the second device region 100N includes: a first mask layer 310 is formed on the first fin material layer 210.

The first mask layer 310 is used as an etching mask for removing the first fin material layer 210 located in the second device region 100N.

Specifically, referring to fig. 11, a pattern transfer layer 300 is further formed on the first mask layer 310.

The pattern transfer layer 300 is used as a mask for patterning the first mask layer 310.

In this embodiment, the pattern transfer layer 300 is a stacked structure, and the pattern transfer layer 300 includes a planarization layer 320, an anti-reflective coating 330 on the planarization layer 320, and a photoresist layer 340 on the anti-reflective coating 330.

A pattern transfer opening 350 is formed in the photoresist layer 340, and the anti-reflective coating 330 and the planarization layer 320 are sequentially etched through the pattern transfer opening 350 to transfer a pattern to the first mask layer 310.

In the present embodiment, the material of the planarization layer 320 is a Spin On Carbon (SOC) material. The spin-coated carbon is formed by a spin-coating process, so that the process cost is low; moreover, by using spin-on carbon, the flatness of the top surface of the planarization layer 320 is advantageously improved, thereby providing a good interface for the process of transferring a pattern. In this embodiment, the material of the anti-reflective layer 330 is a Si-ARC (silicon-containing anti-reflective coating) material.

Referring to fig. 12, the first mask layer 310 is patterned, a mask opening 370 is formed in the first mask layer 310, and the mask opening 370 exposes the first fin material layer 210 in the second device region 100N, so as to prepare for removing the first fin material layer 210 in the second device region 100N.

Specifically, after the anti-reflection coating 330 and the planarization layer 320 at the bottom of the pattern transfer opening 350 are sequentially etched using the photoresist layer 340 as a mask, the first mask layer 310 is etched using the remaining pattern transfer layer 300 as a mask, and a mask opening 370 is formed in the first mask layer 310.

In this embodiment, after forming the mask opening 370 in the first mask layer 310, the method further includes: the remaining pattern transfer layer 300 is removed.

Referring to fig. 13, the first fin material layer 210 in the second device region 100N is removed along the mask opening 370 to form an opening 230 exposing the top of the bottom fin material layer 200, which is beneficial to improving the dimensional accuracy and the topography quality of the formed opening 230.

In this embodiment, after the opening 230 is formed, the first mask layer 310 is removed.

Referring to fig. 14, a second fin material layer 220 is formed in the opening 230.

The second fin material layer 220 is used for subsequent formation of second device fins.

In this embodiment, the second fin material layer 220 is formed in the opening 230 by an epitaxial growth process. The epitaxial growth process can better control process parameters, has high process controllability, is easy to obtain a more accurate film thickness dimension, and is easy to form a film with less impurities, so that the quality of the second fin material layer 220 is high.

In the present embodiment, the material of the second fin material layer 220 includes silicon, germanium, silicon germanium or iii-v semiconductor material.

In the present embodiment, the material of the second fin material layer 220 is different from the material of the first fin material layer 210, that is, the channel material of the first transistor and the channel material of the second transistor are different, so as to meet the process requirements of different transistors. Specifically, the first transistor is a PMOS transistor and the second transistor is an NMOS transistor, and thus, in the present embodiment, the material of the first fin material layer 210 is silicon germanium and the material of the second fin material layer 220 is silicon.

Therefore, in this embodiment, the material of the bottom fin material layer 200 is the same as the material of the second fin material layer 220, and meanwhile, the second fin material layer 220 is formed in the opening 230 by using an epitaxial growth process, and the bottom fin material layer 200 is at the bottom of the opening 230, so that the material of the bottom fin material layer 200 is the same as the material of the second fin material layer 220, which is beneficial to the growth of the second fin material layer 220, and the second fin material layer 220 with higher quality is formed. In other embodiments, the material of the bottom fin material layer may be different from the material of the second fin material layer according to process requirements.

Specifically, the step of forming the second fin material layer 220 in the opening 230 includes: filling the second fin material layer 220 in the opening 230 by using an epitaxial growth process, wherein the second fin material layer 220 also covers the top of the first fin material layer 210 in the first device region 100N; the second fin material layer 220 is planarized, and the second fin material layer 220 on top of the first fin material layer 210 in the first device region 100P is removed.

Compared with the direct formation of the second fin material layer located in the opening, in this embodiment, the second fin material layer 220 is firstly made to cover the top of the first fin material layer 210 located in the first device region 100N, and then the second fin material layer 220 located at the top of the first fin material layer 210 in the first device region 100P is removed, so that the thickness of the second fin material layer 220 in the opening 230 is favorably and accurately controlled.

In this embodiment, the second fin material layer 220 is planarized using a chemical mechanical polishing process.

With reference to fig. 15 to 20, after forming the second fin material layer 220 and before performing the fin patterning process, the method further includes: a second mask layer 400 is formed on first fin material layer 210 and second fin material layer 220.

The second mask layer 400 is used as a mask layer for subsequent fin formation. In this embodiment, the material of the second mask layer 400 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the second mask layer 400 is a stack including a silicon nitride layer 410 and a silicon oxide layer 420 on the silicon nitride layer 410.

In this embodiment, the second mask layer 400 is patterned to form a fin mask layer 500. The fin portion mask layer 500 is used as an etching mask for subsequent fin portion patterning, the bottom fin portion material layer 200, the first fin portion material layer 210 and the second fin portion material layer 220 are patterned through the second mask layer 500, and therefore the pattern transfer accuracy is improved, and a bottom fin portion, a first device fin portion and a second device fin portion are formed.

In the present embodiment, the fin mask layer 500 is formed by a self-aligned quadruple patterning (SAQP) process.

Specifically, referring to fig. 15, a bottom core material layer 430 is formed on the second mask layer 400, and a top core material layer 440 is formed on the bottom core material layer 430; referring to fig. 16, the top core material layer 440 is patterned to form a discrete top core layer 450; referring to fig. 17, a first sidewall layer 460 is formed on the sidewall of the top core layer 450; after the first sidewall layer 460 is formed, the top core layer 450 is removed; referring to fig. 18, after removing the top core layer 450, the bottom core material layer 430 is patterned using the first sidewall layer 460 as a mask to form a bottom core layer 470 protruding above the second mask layer 400; referring to fig. 19, a second side wall layer 480 is formed on the side wall of the bottom core layer 470; after the second side wall layer 480 is formed, the bottom core layer 470 is removed; referring to fig. 20, after removing the bottom core layer 470, the second mask layer 400 is patterned using the second sidewall layer 480 as a mask to form a discrete fin mask layer 500.

In this embodiment, the fin mask layer 500 is formed by a self-aligned quadruple patterning process, so that the fin mask layer 500 has higher pattern density and more accurate pattern conversion, and the constraint of a lithography machine can be overcome while the process requirements are met. In other embodiments, the fin mask layer may be formed in other patterning manners according to process requirements. For example, a self-aligned double patterning (SADP) process or a single photo-etch process may be employed.

Referring to fig. 21, performing fin patterning processing, patterning the first fin material layer 210, the second fin material layer 220, and the bottom fin material layer 200, patterning the bottom fin material layer 200 into bottom fins 600 protruding from the substrate 100 in the first device region 100P and the second device region 100N, respectively, patterning the first fin material layer 210 into first device fins 610 protruding from the bottom fins 600 in the first device region 100P, and patterning the second fin material layer 220 into second device fins 620 protruding from the bottom fins 600 in the second device region 100N.

The first and second device fins 610 and 620 are used to provide channels for first and second transistors, respectively.

In this embodiment, in the step of performing the fin patterning process, the first fin material layer 210, the second fin material layer 220, and the bottom fin material layer 200 are etched using the fin mask layer 500 as a mask.

In this embodiment, a dry etching process is used to perform fin patterning. The dry etching process is a dry etching process with anisotropic etching characteristics, has directionality, and is beneficial to forming the bottom fin portion 600, the first device fin portion 610 and the second device fin portion 620 with good sidewall quality, and meanwhile, the dry etching process can better control process parameters and can more accurately control parameters of fin portion graphical processing.

Specifically, the first fin material layer 210, the second fin material layer 220, and the bottom fin material layer 200 are etched with the top of the etch stop layer 110 as an etch stop position.

Accordingly, the first device fin 610 is formed of silicon germanium and the second device fin 620 is formed of silicon.

It should be noted that an isolation layer covering the sidewalls of the bottom fin 600 is also formed subsequently, and the fin mask layer 500 is removed in the process of forming the isolation layer. For the specific description of the isolation layer, reference may be made to the foregoing embodiments, which are not repeated herein.

It should be further noted that, after the isolation layer is formed subsequently, a gate structure crossing the first device fin 610 and the second device fin 620 is also formed, which is not described herein too much.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (23)

1. A semiconductor structure, comprising:

the transistor comprises a base and a plurality of transistors, wherein the base comprises a substrate, and the substrate comprises a first device area used for forming a first transistor and a second device area used for forming a second transistor;

the fin-shaped part is raised on the substrate and comprises a bottom fin part raised on the substrate and a device fin part located on the bottom fin part, the device fin part comprises a first device fin part located in the first device area and a second device fin part located in the second device area, contact surfaces of the device fin part and the bottom fin part are both flat surfaces, and materials of the first device fin part and the bottom fin part are different.

2. The semiconductor structure of claim 1, wherein the substrate further comprises: the etching stop layer is positioned on the substrate;

the bottom fin portion is raised above the etch stop layer.

3. The semiconductor structure of claim 2, wherein the material of the etch stop layer comprises phosphorus doped silicon, arsenic doped silicon, carbon doped silicon or boron doped silicon.

4. The semiconductor structure of claim 1, wherein channel conductivity types of the first transistor and the second transistor are different.

5. The semiconductor structure of claim 4, wherein the first transistor is a PMOS transistor; the second transistor is an NMOS transistor.

6. The semiconductor structure of claim 1, wherein a material of the first device fin is different from a material of the second device fin.

7. The semiconductor structure of claim 1, wherein a material of the bottom fin portion comprises silicon, germanium, silicon germanium, or a group iii-v semiconductor material; the material of the first device fin portion comprises silicon, germanium, silicon germanium or a III-V semiconductor material; the material of the second device fin includes silicon, germanium, silicon germanium, or a group III-V semiconductor material.

8. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a substrate and a bottom fin material layer positioned on the substrate, and the substrate comprises a first device area used for forming a first transistor and a second device area adjacent to the first device area and used for forming a second transistor;

forming a first fin material layer on the bottom fin material layer, wherein the material of the first fin material layer is different from that of the bottom fin material layer;

removing the first fin material layer positioned in the second device region, reserving the first fin material layer positioned in the first device region, and forming an opening exposing the top of the bottom fin material layer;

forming a second fin material layer in the opening;

performing fin portion imaging processing, imaging the first fin portion material layer, the second fin portion material layer and the bottom fin portion material layer, imaging the bottom fin portion material layer to be protruded on bottom fin portions of the substrate of the first device area and the substrate of the second device area respectively, imaging the first fin portion material layer to be protruded on first device fin portions on bottom fin portions of the first device area, and imaging the second fin portion material layer to be protruded on second device fin portions on bottom fin portions of the second device area.

9. The method of forming a semiconductor structure of claim 8, wherein in the step of providing a base, the base further comprises an etch stop layer between the substrate and the bottom fin material layer.

10. The method of forming a semiconductor structure of claim 9, wherein the step of providing a substrate comprises: providing a substrate;

modifying the surface of the substrate, and converting the substrate with partial thickness at the top of the substrate into an etching stop layer;

and forming a bottom fin material layer on the etching stop layer.

11. The method of claim 8, wherein removing the layer of first fin material in the second device region comprises: forming a first mask layer on the first fin material layer;

patterning the first mask layer to form a mask opening, wherein the mask opening exposes the first fin material layer of the second device region;

removing the first fin material layer located in the second device region along the mask opening to form an opening exposing the top of the bottom fin material layer;

and removing the first mask layer after the opening is formed.

12. The method of forming a semiconductor structure of claim 8, wherein after forming the second layer of fin material and before performing the fin patterning process, further comprising: forming a second mask layer on the first fin material layer and the second fin material layer;

patterning the second mask layer to form a fin part mask layer;

and etching the first fin material layer and the second fin material layer by using the fin mask layer as a mask in the step of performing the fin patterning treatment.

13. The method of claim 10, wherein the step of modifying the surface of the substrate comprises converting a portion of the thickness of the top of the substrate into an etch stop layer by an ion implantation process.

14. The method of forming a semiconductor structure of claim 13, wherein the parameters of the ion implantation process comprise: the implanted ions include boron ions, carbon ions, arsenic ions or phosphorus ions, the implantation energy is 1KeV to 600KeV, and the implantation dose is 1 × 10 ¹² ions/cm ² To 2X 10 ¹⁸ ions/cm ² 。

15. The method of forming a semiconductor structure of claim 8, wherein forming the bottom fin material layer comprises: and forming the bottom fin material layer on the substrate by adopting an epitaxial growth process.

16. The method of forming a semiconductor structure of claim 15, wherein after forming the bottom fin material layer on the substrate using an epitaxial growth process, further comprising: and carrying out planarization treatment on the top surface of the bottom fin material layer.

17. The method of forming a semiconductor structure of claim 8, wherein in the step of forming a first fin material layer on the bottom fin material layer, the first fin material layer is formed using an epitaxial growth process.

18. The method of forming a semiconductor structure of claim 17, wherein after forming the first fin material layer using an epitaxial growth process, further comprising: and carrying out planarization treatment on the top surface of the first fin material layer.

19. The method of forming a semiconductor structure of claim 8, wherein in the step of removing the first fin material layer in the second device region, a dry etching process is used to remove the first fin material layer in the second device region.

20. The method of forming a semiconductor structure of claim 8, wherein forming a second layer of fin material in the opening comprises: filling the second fin material layer in the opening by adopting an epitaxial growth process, wherein the second fin material layer also covers the top of the first fin material layer positioned in the first device region;

and flattening the second fin material layer, and removing the second fin material layer positioned at the top of the first fin material layer of the first device area.

21. The method of forming a semiconductor structure of claim 8, wherein in the step of providing a substrate, channel conductivity types of the first transistor and the second transistor are different.

22. The method of claim 8, wherein a material of the first fin material layer is different from a material of the second fin material layer.

23. The method of claim 8, wherein a material of the bottom fin material layer comprises silicon, germanium, silicon germanium, or a group III-V semiconductor material; the material of the first fin material layer comprises silicon, germanium, silicon germanium or a III-V semiconductor material; the material of the second fin material layer includes silicon, germanium, silicon germanium, or a group III-V semiconductor material.

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