CN115312103B - Erasing voltage configuration method, device and equipment of flash memory chip and storage medium - Google Patents
Erasing voltage configuration method, device and equipment of flash memory chip and storage medium Download PDFInfo
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- CN115312103B CN115312103B CN202211229121.4A CN202211229121A CN115312103B CN 115312103 B CN115312103 B CN 115312103B CN 202211229121 A CN202211229121 A CN 202211229121A CN 115312103 B CN115312103 B CN 115312103B
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
Abstract
The invention relates to the technical field of memories, and particularly discloses a method, a device, equipment and a storage medium for configuring an erasing voltage of a flash memory chip, wherein the method comprises the following steps: acquiring the Cycle times of a target storage area to be erased; calling an erasing voltage group from a preset erasing voltage group library according to Cycle times, wherein the erasing voltage group comprises an erasing voltage value and a weak programming voltage value, and the erasing voltage group library comprises a plurality of erasing voltage groups matched with different Cycle time intervals; the Cycle times of the target storage area acquired by the method can represent the use degree of the target storage area, the erasing voltage group is called from the preset erasing voltage group library based on the Cycle time interval corresponding to the Cycle times, the erasing voltage value and the weak programming voltage value matched with the characteristics of the current target storage area can be quickly determined, and the flash memory chip can be ensured to efficiently, high-quality and smoothly complete the erasing operation in the whole life Cycle.
Description
Technical Field
The present disclosure relates to the field of memory technologies, and in particular, to a method, an apparatus, a device, and a storage medium for configuring an erase voltage of a flash memory chip.
Background
For the operation of a flash memory chip such as a nor flash, the erasing operation generally takes a relatively long time, and the erasing characteristic of the nor flash generally shows that the more the cycles are, the more difficult the erasing is, especially until the end of the life Cycle of the flash memory chip, the data in the storage area in the flash memory chip is difficult to erase based on the relevant voltage of the erasing operation configured by the factory, so that the longer the user feels the flash memory chip is, the slower the data is.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
The application aims to provide a flash memory chip erasing voltage configuration method, a flash memory chip erasing voltage configuration device, flash memory chip erasing voltage configuration equipment and a storage medium, so that the flash memory chip can be ensured to efficiently complete the erasing operation in the whole life cycle.
In a first aspect, the present application provides a method for configuring an erase voltage of a flash memory chip, for configuring a voltage associated with an erase operation performed by the flash memory chip, the method including the following steps:
acquiring Cycle times of a target storage area to be erased;
and calling an erasing voltage group from a preset erasing voltage group library according to the Cycle times, wherein the erasing voltage group comprises an erasing voltage value and a weak programming voltage value, and the erasing voltage group library comprises a plurality of erasing voltage groups matched with different Cycle time intervals.
According to the erasing voltage configuration method of the flash memory chip, the erasing voltage group is called from the preset erasing voltage group library based on the Cycle number interval corresponding to the Cycle number, the erasing voltage value and the weak programming voltage value matched with the characteristics of the current target storage area can be quickly determined, the target storage area is erased by using the erasing voltage value and the weak programming voltage value matched with the target storage area, and the flash memory chip can be guaranteed to efficiently, high-quality and smoothly complete the erasing operation in the whole life Cycle.
The erasing voltage configuration method of the flash memory chip is characterized in that the erasing voltage value of the erasing voltage group in the erasing voltage group library is positively correlated with the increasing sequence of the Cycle times interval.
In this example, the erase voltage values of different erase voltage groups in the erase voltage group library are set to be positively correlated with the increasing sequence of the Cycle number interval, so that a target storage area in which the Cycle number is in a larger Cycle number interval can be configured with a larger erase voltage value.
The erasing voltage configuration method of the flash memory chip comprises the following steps of: 0-10000 times, 10001-20000 times, 20001-50000 times, 50001-80000 times and 80000 times or more.
The method for configuring the erasing voltage of the flash memory chip comprises the following steps that the target storage area is a plurality of blocks or sectors in the flash memory chip.
The erasing voltage configuration method of the flash memory chip is characterized in that the Cycle times are counted and stored based on a nonvolatile counter.
The erasing voltage configuration method of the flash memory chip comprises the following steps of calling an erasing voltage group from a preset erasing voltage group library according to the Cycle times:
acquiring a Cycle frequency interval in which the Cycle frequency is located according to the Cycle frequency;
updating configuration information based on the Cycle frequency interval;
calling the erase voltage group from the erase voltage group library based on the configuration information.
In the method of this example, the configuration information may be repeatedly used to call the erase voltage group to perform the erase operation until the Cycle number of the target storage region increases to the next Cycle number interval.
The method for configuring the erase voltage of the flash memory chip, wherein the step of calling the erase voltage group from the erase voltage group library based on the configuration information includes:
writing the configuration information into a configuration area or a configuration register of a corresponding target storage area;
and when the target storage area needs to be erased, reading the configuration information in the configuration area or the configuration register, and calling the erasing voltage group from the erasing voltage group library based on the read configuration information.
In a second aspect, the present application further provides an erase voltage configuration apparatus for a flash memory chip, configured to configure voltages associated with an erase operation performed by the flash memory chip, the apparatus including:
the acquisition module is used for acquiring the Cycle times of a target storage area to be erased;
and the configuration module is used for calling an erasing voltage group from a preset erasing voltage group library according to the Cycle times, wherein the erasing voltage group comprises an erasing voltage value and a weak programming voltage value, and the erasing voltage group library comprises a plurality of erasing voltage groups matched with different Cycle time intervals.
The erasing voltage configuration device of the flash memory chip can quickly determine the erasing voltage value and the weak programming voltage value matched with the characteristics of the current target storage area by calling the erasing voltage group from the preset erasing voltage group library based on the Cycle number interval corresponding to the Cycle number, and can erase the target storage area by using the erasing voltage value and the weak programming voltage value matched with the target storage area, so that the flash memory chip can efficiently, high-quality and smoothly complete the erasing operation in the whole life Cycle.
In a third aspect, the present application further provides an electronic device, comprising a processor and a memory, where the memory stores computer readable instructions, and the computer readable instructions, when executed by the processor, perform the steps of the method as provided in the first aspect.
In a fourth aspect, the present application also provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method as provided in the first aspect.
From the above, the present application provides an erase voltage configuration method, an erase voltage configuration device, an erase voltage configuration apparatus, and a storage medium for a flash memory chip, wherein a Cycle number of a target storage region obtained by the erase voltage configuration method for the flash memory chip can represent a usage degree of the target storage region, that is, an erase difficulty of the target storage region is reflected, an erase voltage value and a weak program voltage value matched with characteristics of the current target storage region can be quickly determined by calling the erase voltage group from a preset erase voltage group library based on a Cycle number interval corresponding to the Cycle number, and the target storage region is erased by using the erase voltage value and the weak program voltage value matched with the target storage region, so that the flash memory chip can be ensured to efficiently, highly and smoothly complete an erase operation in a whole life Cycle.
Drawings
Fig. 1 is a flowchart of an erase voltage configuration method of a flash memory chip according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of an erase voltage configuration apparatus of a flash memory chip according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Reference numerals: 201. an acquisition module; 202. a configuration module; 301. a processor; 302. a memory; 303. a communication bus.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
In a first aspect, referring to fig. 1, some embodiments of the present application provide a method for configuring an erase voltage of a flash memory chip, for configuring a voltage associated with an erase operation of the flash memory chip, the method including the following steps:
s1, acquiring Cycle times of a target storage area to be erased;
and S2, calling an erasing voltage group from a preset erasing voltage group library according to Cycle times, wherein the erasing voltage group comprises an erasing voltage value and a weak programming voltage value, and the erasing voltage group library comprises a plurality of erasing voltage groups matched with different Cycle time intervals.
Specifically, in the technical field of memory, cycle is a program erase operation, which refers to a recyclable operation in which a target storage area in a flash memory chip is subjected to one-time programming and erasing, and the programming and erasing operations in Cycle can be performed continuously or separately; the Cycle number represents the usage degree of the target storage area and also reflects the current performance of the target storage area, and generally, the larger the Cycle number of the target storage area is, the worse the performance is, that is, the harder the memory cell of the target storage area is to be erased and programmed.
More specifically, the target storage area is an area to be erased in a storage array of the flash memory chip, different storage areas in the storage array have certain process differences due to different use conditions, a storage area with a large Cycle number is generally harder to erase than a storage area with a small Cycle number, and more erasing time needs to be consumed when the erasing operation is performed; the erase operation includes multiple phases, typically including erase (erase), over erase repair (over erase program), weak program (soft program); in the whole erasing process, the voltage configuration of erase and soft program is particularly important, if the voltage of erase is too small, more time is consumed to erase all data in the target storage area to 1 when the erase is executed, and if the voltage of erase is too large, a large amount of over-erased (over erase) storage units are easily generated in the target storage area after the erase is executed, and more time is required to execute over erase program to repair; if the voltage of the soft program is too small, it will take more time to adjust the threshold voltage of the target storage area to execute the soft program; if the voltage of the soft program is too large, the target storage area is easy to generate a storage unit which is expressed as weak 0 data after the soft program is executed, so that erase needs to be executed again; the erase and soft program voltages can prolong the whole erasing operation time; it should be understood that the above description of the voltage being too small or too large refers to an operating voltage that does not match the target storage region, and in particular, the operating voltage that originally matches becomes unmatched by causing performance degradation after the target storage region is cycled for a plurality of cycles.
More specifically, as can be seen from the foregoing, the target memory region changes toward a characteristic that the erase is more difficult and the program is more easy as the Cycle number increases, and the erase voltage and the soft program voltage, which are fixed by the preset parameters in the prior art, become too small and too large, respectively, and the time of the erase operation is seriously affected.
More specifically, the erase voltage is an erase voltage, and the weak program voltage is a soft program voltage.
More specifically, in the embodiment of the present application, each erase voltage group includes one erase voltage value and a weak program voltage value; the erasing voltage group bank comprises a plurality of erasing voltage groups, and each Cycle time interval has an erasing voltage group uniquely corresponding to the Cycle time interval.
More specifically, the Cycle number interval is a numerical interval divided based on the Cycle number, because the life Cycle (the number of cycles that can be performed) of the flash memory chip is generally more than one hundred thousand, the characteristic change process of the target storage region is relatively unobvious, and if the erase voltage group is directly called according to the Cycle number, a large amount of memory resources are wasted, in the embodiment of the application, a plurality of Cycle number intervals are divided according to the Cycle number, and a proper erase voltage group is designed for each Cycle number interval, so that when the Cycle number of the target storage region in the flash memory chip is increased from one Cycle number interval to another, the proper erase voltage group can be directly called to perform erase operation, and the erase efficiency and the erase effect of the flash memory chip are ensured while the memory resources are reasonably utilized.
The Cycle times of the target storage area, which are obtained by the method for configuring the erasing voltage of the flash memory chip, can represent the use degree of the target storage area, namely the erasing difficulty of the target storage area is reflected, the erasing voltage group is called from a preset erasing voltage group library based on the Cycle time interval corresponding to the Cycle times, the erasing voltage value and the weak programming voltage value matched with the characteristics of the current target storage area can be quickly determined, and the target storage area is erased by utilizing the erasing voltage value and the weak programming voltage value matched with the target storage area, so that the flash memory chip can be ensured to efficiently, high-quality and smoothly complete the erasing operation in the whole life Cycle.
The erasing voltage configuration method of the flash memory chip provided by the embodiment of the application is used for carrying out voltage configuration on a target storage area, so that each storage area has proper voltage configuration to ensure that erasing operation can be efficiently and smoothly completed.
It should be understood that the method of the embodiment of the present application is applied to a flash memory chip, and the erase voltage bank and Cycle time interval information are stored in a nonvolatile manner through a non-volatile register circuit.
More specifically, the erase voltage group in the erase voltage group library is adapted to the Cycle number interval of the flash memory chip, and the erase voltage value and the weak programming voltage value set in the erase voltage group library can be obtained and set by performing multiple experimental tests on the same type of flash memory chips according to the actual situation, or can be obtained and set by performing multiple simulation tests based on a design model of the flash memory chips, so as to obtain the erase voltage group library suitable for the corresponding type of flash memory chips; more specifically, the erase voltage sets in the erase voltage set bank are adapted to the type of the corresponding flash memory chip, the charge pump circuit, and the storage area partition size.
In some preferred embodiments, the method for configuring erase voltage of a flash memory chip according to the embodiments of the present application may be selectively activated based on a usage requirement or automatically run when the Cycle number of the target memory region exceeds a Cycle number interval.
Specifically, when the erase voltage configuration method of the flash memory chip according to the embodiment of the present application is selectively started based on the use requirement, the user may determine whether the erase voltage value and the weak program voltage value need to be reconfigured according to the operation speed of the flash memory chip; when the method for configuring the erase voltage of the flash memory chip in the embodiment of the application automatically runs when the Cycle times of the target storage area exceed the Cycle time interval, the flash memory chip judges whether the erase voltage value and the weak program voltage value of the corresponding storage area are required to be updated and configured by monitoring the Cycle times of each storage area, so that the erase voltage value and the weak program voltage value corresponding to each storage area can be configured spontaneously in the whole life Cycle of the flash memory chip, and the flash memory chip is ensured to have the optimized erase efficiency under any use degree.
In some preferred embodiments, the Cycle count is stored based on a non-volatile counter (counter) count.
Specifically, the nonvolatile counter is a circuit device commonly used in the memory technology field, and is used for counting digital related data; in the embodiment of the application, each storage area of the flash memory chip is provided with a corresponding nonvolatile counter which is respectively used for recording the Cycle times of the corresponding storage area; according to the erasing voltage configuration method of the flash memory chip, the Cycle times can be conveniently and accurately acquired by reading the data in the nonvolatile counter corresponding to the target storage area.
More specifically, each storage area is corresponding to a configuration counter for counting, so that the counting data of each storage area can be ensured to be accurate and not interfered with each other.
In some preferred embodiments, the erase voltage values of the erase voltage groups in the erase voltage group library are positively correlated with the ascending order of the Cycle number intervals.
Specifically, as can be seen from the foregoing, a storage area with a larger Cycle number is generally harder to erase than a storage area with a smaller Cycle number, and therefore, the storage area with the larger Cycle number generally needs to apply an erase voltage value larger than that in the initial configuration to successfully erase the storage area, and therefore, in the embodiment of the present application, the erase voltage values of different erase voltage groups in the erase voltage group library are set to be positively correlated with the increasing sequence of the Cycle number interval, so that a target storage area with the Cycle number within the larger Cycle number interval can be configured with a larger erase voltage value.
In some embodiments, the weak program voltage values of the erase voltage groups in the erase voltage group library are inversely related to the ascending order of the Cycle number interval.
Specifically, a storage area with a large Cycle number is generally easier to program than a storage area with a small Cycle number, and therefore, a weak programming voltage value needs to be applied to a storage area with a large Cycle number to prevent a storage unit in the storage area from being programmed with weak "0" data; however, the actual weak program voltage value is smaller, and the change amplitude is not large during configuration, so in the embodiment of the present application, the weak program voltage value of the erase voltage group in the erase voltage group library is preferably negatively correlated with the increasing sequence of the Cycle number intervals of the complex combination (for example, the same weak program voltage value is configured for every two Cycle number intervals).
In some preferred embodiments, the Cycle number interval is preferably set based on a percentage value of a life Cycle of the memory, the life Cycle of the memory is the available erasing number of each storage array suggested or recorded in the memory use specification, and in the embodiment of the present application, the Cycle number interval is divided based on 10%, 20%, 50% and 80% of the life Cycle.
In some preferred embodiments, since the lifecycle of the nor flash memory chip is generally one hundred thousand times, the Cycle number interval is divided based on the following Cycle numbers: 0-10000 times, 10001-20000 times, 20001-50000 times, 50001-80000 times and 80000 times or more.
In some preferred embodiments, the target storage area is a number of blocks or a number of sectors in a flash memory chip.
Specifically, the erasing manner of the flash memory chip includes full erase (chip erase), block erase (block erase) and sector erase (sector erase), the difference of the use degrees of different storage areas of the flash memory chip is large (representing different Cycle times of different storage areas), and if the method of the embodiment of the present application is adopted to perform the full erase, the improvement effect of the erase efficiency is very small, so the method of the embodiment of the present application is mainly used for performing optimized use on the block erase and the sector erase, that is, the erase voltage value and the weak programming voltage value are updated on a target storage area formed by a plurality of blocks or a plurality of sectors, so as to improve the erase operation efficiency of the target storage area.
In some preferred embodiments, the step of retrieving the erase voltage set from a preset erase voltage set library according to the Cycle number includes:
s21, acquiring a Cycle frequency interval in which the Cycle frequency is located according to the Cycle frequency;
s22, updating configuration information based on the Cycle frequency interval;
and S23, calling the erasing voltage group from the erasing voltage group library based on the configuration information.
Specifically, the erase voltage and the soft program voltage are generated by a charge pump circuit of the flash memory chip, and are generally generated by electrically reading corresponding configuration information and according to the configuration information, so in the embodiment of the present application, a process of configuring a voltage related to an erase operation of the flash memory chip is a process of updating the configuration information about the erase voltage value and the weak program voltage value, so that the present application updates the configuration information based on step S22, so that step S23 can call the corresponding erase voltage value and the weak program voltage value according to the updated configuration information, thereby implementing repeated call of the erase voltage value and the weak program voltage value.
More specifically, in this embodiment, after the configuration information is updated in step S22, the configuration information may be reused to call the erase voltage group to perform the erase operation until the Cycle number of the target storage area increases to the next Cycle number interval.
In some preferred embodiments, the step of calling the erase voltage set from the erase voltage set library based on the configuration information includes:
s231, writing the configuration information into a configuration area or a configuration register of the corresponding target storage area;
s232, when the target storage area needs to be erased, reading configuration information in the configuration area or the configuration register, and calling the erase voltage group from the erase voltage group library based on the read configuration information.
Specifically, in the embodiment of the present application, the configuration information may be written in a configuration area or a configuration register of the target storage area, where the configuration area is a storage area where data is started in the target storage area, and is generally set in the first 8 bytes in the corresponding storage array; the configuration register is arranged in a register used for nonvolatile register of specific configuration information in a chip; the two modes can be used for registering or updating the configuration information, so that the flash memory chip can quickly read the configuration information and call a proper erasing voltage value and a proper weak programming voltage value when the target storage area needs to be erased, and the target storage area can be erased.
More specifically, in the embodiment of the present application, the Cycle number section has a corresponding configuration number, and step S231 is to write the configuration number into a configuration area or a configuration register of a corresponding target storage area to update the configuration information; the erase voltage groups of the erase voltage group library in step S232 are matched with the configuration information one by one, and the configuration and updating processes of the erase voltage groups are effectively simplified by this setting manner.
In some preferred embodiments, the configuration relationship between the Cycle number interval and the erase voltage value and the weak program voltage value is as follows:
TABLE 1 Erase Voltage set configuration Table
| Cycle number interval | Value of erase voltage | Weak programming voltage value |
| 0 to 10000 times | 14.5V | 3V |
| 10001-20000 times | 14.8V | 3V |
| 20001-50000 times | 15V | 2.8V |
| 50001-80000 times | 15.2V | 2.8V |
| 80000 times or more | 15.5V | 2.5V |
In a second aspect, referring to fig. 2, some embodiments of the present application further provide an erase voltage configuration apparatus for a flash memory chip, configured to configure voltages associated with an erase operation performed by the flash memory chip, the apparatus including:
an obtaining module 201, configured to obtain the Cycle number of a target storage area to be erased;
the configuration module 202 is configured to invoke an erase voltage group from a preset erase voltage group library according to Cycle times, where the erase voltage group includes an erase voltage value and a weak program voltage value, and the erase voltage group library includes a plurality of erase voltage groups paired with different Cycle time intervals.
The Cycle times of the target storage area, which are acquired by the erasing voltage configuration device of the flash memory chip, can represent the use degree of the target storage area, namely the erasing difficulty of the target storage area is reflected, the erasing voltage group is called from a preset erasing voltage group library based on the Cycle time interval corresponding to the Cycle times, the erasing voltage value and the weak programming voltage value matched with the characteristics of the current target storage area can be quickly determined, and the target storage area is erased by utilizing the erasing voltage value and the weak programming voltage value matched with the target storage area, so that the flash memory chip can be ensured to efficiently, high-quality and smoothly complete the erasing operation in the whole life Cycle.
In some preferred embodiments, the erase voltage configuration apparatus of the flash memory chip of the embodiment of the present application is configured to perform the erase voltage configuration method of the flash memory chip provided in the first aspect.
In a third aspect, referring to fig. 3, an embodiment of the present application provides a structural schematic diagram of an electronic device, where the electronic device includes: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method in any alternative implementation of the above-described embodiments.
In a fourth aspect, the present application provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In summary, embodiments of the present application provide a method, an apparatus, a device, and a storage medium for configuring an erase voltage of a flash memory chip, where a Cycle number of a target storage area obtained by the method for configuring an erase voltage of a flash memory chip can represent a usage degree of the target storage area, that is, an erase difficulty of the target storage area is reflected, an erase voltage group is called from a preset erase voltage group library based on a Cycle number interval corresponding to the Cycle number to quickly determine an erase voltage value and a weak program voltage value that are matched with characteristics of the current target storage area, and the target storage area is erased by using the erase voltage value and the weak program voltage value that are matched with the target storage area, so that the flash memory chip can efficiently, high-quality, and smoothly complete an erase operation in a whole life Cycle.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (9)
1. An erase voltage configuration method for a flash memory chip, configured to configure voltages associated with the flash memory chip to perform an erase operation, the method comprising:
acquiring Cycle times of a target storage area to be erased;
calling an erasing voltage group from a preset erasing voltage group library according to the Cycle times, wherein the erasing voltage group comprises an erasing voltage value and a weak programming voltage value, the erasing voltage group library comprises a plurality of erasing voltage groups matched with different Cycle time intervals, and the weak programming voltage value is a voltage configured in a soft program stage in the erasing operation;
the erasing voltage value of the erasing voltage group in the erasing voltage group library is positively correlated with the increasing sequence of the Cycle times interval;
and the weak programming voltage value of the erasing voltage group in the erasing voltage group library is inversely related to the increasing sequence of the Cycle times interval.
2. The method according to claim 1, wherein the Cycle number interval is divided based on the following Cycle numbers: 0-10000 times, 10001-20000 times, 20001-50000 times, 50001-80000 times and 80000 times or more.
3. The method of claim 1, wherein the target storage area is a plurality of blocks or a plurality of sectors in the flash memory chip.
4. The method of claim 1, wherein the Cycle count is stored based on a non-volatile counter.
5. The method according to claim 1, wherein the step of calling the erase voltage group from a preset erase voltage group library according to the Cycle number comprises:
acquiring a Cycle frequency interval in which the Cycle frequency is located according to the Cycle frequency;
updating configuration information based on the Cycle frequency interval;
calling the erase voltage group from the erase voltage group library based on the configuration information.
6. The method of claim 5, wherein the step of calling the erase voltage set from the erase voltage set library based on the configuration information comprises:
writing the configuration information into a configuration area or a configuration register of a corresponding target storage area;
and when the target storage area needs to be erased, reading the configuration information in the configuration area or the configuration register, and calling the erasing voltage group from the erasing voltage group library based on the read configuration information.
7. An erase voltage configuration apparatus for a flash memory chip, configured to configure voltages associated with the flash memory chip to perform an erase operation, the apparatus comprising:
the acquisition module is used for acquiring the Cycle times of a target storage area to be erased;
the configuration module is used for calling an erasing voltage group from a preset erasing voltage group library according to the Cycle times, wherein the erasing voltage group comprises an erasing voltage value and a weak programming voltage value, and the erasing voltage group library comprises a plurality of erasing voltage groups matched with different Cycle time intervals; the weak programming voltage value is the voltage configured at the soft program stage in the erasing operation;
the erasing voltage value of the erasing voltage group in the erasing voltage group library is positively correlated with the increasing sequence of the Cycle times interval;
and the weak programming voltage value of the erasing voltage group in the erasing voltage group library is inversely related to the ascending sequence of the Cycle times interval.
8. An electronic device comprising a processor and a memory, the memory storing computer readable instructions which, when executed by the processor, perform the steps of the method of any one of claims 1-6.
9. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any of claims 1-6.
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