CN115309345B - Erasing method, device, equipment and medium of nor flash - Google Patents
Erasing method, device, equipment and medium of nor flash Download PDFInfo
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- CN115309345B CN115309345B CN202211229128.6A CN202211229128A CN115309345B CN 115309345 B CN115309345 B CN 115309345B CN 202211229128 A CN202211229128 A CN 202211229128A CN 115309345 B CN115309345 B CN 115309345B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
The invention relates to the technical field of memories, and particularly discloses a method, a device, equipment and a medium for erasing nor flash, wherein the method comprises the following steps: acquiring the Cycle times of each partition in the to-be-erased area, and calculating and acquiring the Cycle time difference between different partitions; when a Cycle time difference value larger than a preset threshold value exists, grouping all the partitions according to the Cycle time to obtain an erasing group; respectively carrying out erasing operation on each erasing group; the method comprises the steps of judging the difference degree of the erasing characteristics of storage units in an area to be erased based on the Cycle times of all partitions in the area to be erased, and grouping the partitions according to the Cycle times and respectively performing erasing operation when the difference value of the Cycle times is larger than a preset threshold value, so that the partitions with similar erasing characteristics in each erasing group can be smoothly erased.
Description
Technical Field
The present application relates to the field of memory technologies, and in particular, to an erasing method, apparatus, device, and medium for a nor flash.
Background
The ideal erasure case for a nor flash is: the erase characteristics of all memory cells in the erased area are identical, and the erase time is very short under appropriate conditions, but this ideal case is not present in the currently developed flash manufacturing technology. Once the erasing characteristics of the erased memory cells in the same erasing area are very different, some memory cells are easily over-erased during the erasing operation, so that the erasing time is long, and even the erasing characteristics of the memory cells in different areas (blocks or sectors) in the memory area are too different, so that the memory cells in the whole erasing area cannot be erased to an erased state when the whole memory area is erased, thereby causing the erasing failure.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
The application aims to provide an erasing method, device, equipment and medium of a nor flash, and the erasing operation is guaranteed to be completed smoothly.
In a first aspect, the present application provides a method for erasing a non-flash, which is used to erase an area to be erased of the non-flash, and includes the following steps:
acquiring the Cycle times of each partition in the to-be-erased area, and calculating and acquiring the Cycle time difference between different partitions;
when a Cycle time difference value larger than a preset threshold value exists, grouping all the partitions according to the Cycle time to obtain an erasing group;
and respectively carrying out erasing operation on each erasing group.
According to the method for erasing the nor flash, the difference degree of the erasing characteristics of the storage unit in the area to be erased is judged based on the Cycle times of all the partitions in the area to be erased, and when the Cycle time difference is larger than a preset threshold value, the partitions are grouped according to the Cycle times and are respectively erased, so that the partitions with similar erasing characteristics in each erasing group can be smoothly erased, the whole area to be erased can be successfully erased, and the problem that the erasing failure of the area to be erased is caused by the fact that the erasing characteristic difference of different partitions is too large is effectively avoided.
The erasing method of the nor flash, wherein the step of grouping all the partitions according to the Cycle times to obtain the erasing group comprises the following steps:
and traversing the rest of the non-grouped partitions based on any one of the non-grouped partitions, acquiring the partitions of which the Cycle number difference is smaller than the preset threshold value to form an erasing group, and repeatedly executing the processes until all the partitions are grouped.
In the example, the traversal thinking is adopted to extract the partitions from the partition pool formed by all the partitions to form the erasure group, so that the partitions in each erasure group have similar erasure performance, and the partitions can be effectively prevented from being overlooked and missed in selection.
The erasing method of the nor flash, wherein the step of grouping all the partitions according to the Cycle times to obtain the erasing group comprises the following steps:
and grouping according to a plurality of preset divided Cycle frequency intervals and the Cycle frequency of each partition to obtain an erasing group.
In this example, the Cycle number section is a numerical value section divided based on the Cycle number, and a difference between an upper limit value and a lower limit value of each Cycle number section should be smaller than or equal to a preset threshold value, so that the erasing characteristics of the partitions in the erasing group divided based on the Cycle number section are similar.
The erasing method of the nor flash is characterized in that the Cycle times of each partition are counted and stored on the basis of a corresponding nonvolatile counter.
In the method for erasing the nor flash, when the area to be erased is the whole storage array, the partition unit is a block, a half block or a sector.
The erasure method of the nor flash, wherein the partition unit of the partition is determined based on the partition configuration information bit.
The erasing method of nor flash is characterized in that the preset threshold is 20000 times.
In a second aspect, the present application also provides an erasing apparatus for a nor flash, configured to erase an area to be erased of the nor flash, the apparatus including:
the acquisition module is used for acquiring the Cycle times of each partition in the to-be-erased area and calculating and acquiring the Cycle time difference between different partitions;
the grouping module is used for grouping all the partitions according to the Cycle times to acquire an erasing group when a Cycle time difference value larger than a preset threshold value exists;
and the erasing module is used for respectively performing erasing operation on each erasing group.
The erasing device of the nor flash judges the difference degree of the erasing characteristics of the storage units in the area to be erased based on the Cycle times of all the partitions in the area to be erased, and when the Cycle time difference is larger than a preset threshold value, the partitions are grouped and respectively erased according to the Cycle times, so that the partitions with similar erasing characteristics in each erasing group can be smoothly erased, the whole area to be erased can be successfully erased, and the problem that the erasing failure is caused due to the overlarge difference of the erasing characteristics of different partitions in the area to be erased is effectively avoided.
In a third aspect, the present application further provides an electronic device, comprising a processor and a memory, where the memory stores computer readable instructions, and the computer readable instructions, when executed by the processor, perform the steps of the method as provided in the first aspect.
In a fourth aspect, the present application also provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method as provided in the first aspect.
It can be seen from the above that, the present application provides an erasing method, an erasing device, an erasing apparatus, and an erasing medium for a nor flash, wherein the erasing method for a nor flash determines a difference degree of erasing characteristics of memory cells in an area to be erased based on Cycle times of respective partitions in the area to be erased, and when a difference value of the Cycle times is greater than a preset threshold value, the partitions are grouped and respectively erased according to the Cycle times, so that partitions with similar erasing characteristics in each erasing group can be smoothly erased, thereby ensuring that the entire area to be erased can be successfully erased, and effectively avoiding the problem that the erasing failure of the area to be erased is caused by too large difference of the erasing characteristics of different partitions.
Drawings
Fig. 1 is a flowchart of an erasing method of a nor flash according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of an erasing apparatus of a nor flash according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Reference numerals: 201. an acquisition module; 202. a grouping module; 203. an erasing module; 301. a processor; 302. a memory; 303. a communication bus.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
When the erasing characteristics of the memory cells of different partitions (blocks or sectors) in a memory area are too different, the memory area is subjected to an overall erasing operation, so that an over-erasing phenomenon occurs to a part of the memory cells in the partitions, and after the over-erased memory cells are repaired, the memory cells which are partially successfully erased are also converted into a programming state, and all the memory cells in the memory area cannot be changed into an erasing state by repeating multiple times of erasing and over-erasing repairing, so that an erasing failure is caused.
In a first aspect, referring to fig. 1, some embodiments of the present application provide a method for erasing a nor flash, which is used to erase an area to be erased of the nor flash, and the method includes the following steps:
s1, acquiring the Cycle times of each partition in a to-be-erased area, and calculating and acquiring the Cycle time difference between different partitions;
s2, when a Cycle time difference value larger than a preset threshold value exists, grouping all the partitions according to the size of the Cycle times to obtain an erasing group;
and S3, respectively carrying out erasing operation on each erasing group.
Specifically, in the field of memory technology, cycle is a program/erase operation, which refers to a recyclable operation in which a certain memory region (memory array, block, sector, or memory cell) in nor flash is programmed and erased once, and the program/erase operation in Cycle may be performed continuously or separately; the Cycle number represents the usage degree of the corresponding storage area and also reflects the current performance of the corresponding storage area, and generally, the larger the Cycle number of the storage area is, the worse the performance is, that is, the harder the memory cell of the storage area is to be erased and programmed.
More specifically, the erasing operation of the nor flash generally refers to erasing operation of the whole storage region, such as full erase (chip erase), block erase (block erase), sector erase (sector erase), and the like, but the programming operation can program a part of the storage units in the storage region, for example, the storage region is programmed with 10-times alternating data, so the erasing method of the nor flash in the embodiment of the present application preferably represents the Cycle times by using the erasing times, and in other embodiments, the Cycle times can be obtained by integrating the programming times and the erasing times.
More specifically, in the embodiment of the present application, the partition may be the minimum operation unit of the erase operation, or may not be, and in the embodiment of the present application, it is preferable to perform the partition in the minimum operation unit of the erase operation.
It should be understood that after step S1 is executed, if all Cycle times differences are less than or equal to the preset threshold, performing a normal erase operation on the area to be erased, and if the area to be erased is the entire storage array, performing a full erase (chip erase).
More specifically, the step S1 of calculating the difference in the acquired Cycle times reflects the difference in the degree of use between the different partitions; the smaller difference of the Cycle times indicates that the erasing characteristics of the two corresponding partitions are relatively similar, namely the time consumed by erasing with the same erasing voltage is similar, and the probability of over-erasing phenomenon is smaller when erasing is carried out at the same time; the larger difference of the Cycle times indicates that the erasing characteristics of the two corresponding partitions are far apart, that is, the difference of the time consumed by erasing with the same erasing voltage is larger, and the over-erasing phenomenon is more easily caused when erasing is carried out at the same time.
More specifically, step S2 is equivalent to calculating and obtaining the difference between all cycles times to determine whether there is a partition in the to-be-erased area whose erase characteristic difference is larger than the expected one, and if the area with large erase characteristic difference is erased integrally, the problem of too long erase time is caused, and the time for repairing the over-erased memory cell is also prolonged due to the over-erase phenomenon which is more likely to occur; therefore, the method for erasing a nor flash according to the embodiment of the present application determines that there is a partition having an erase characteristic difference larger than an expected difference in the erase characteristic difference in step S2, groups the partitions, and then erases the group of the divided partitions in step S3.
More specifically, step S3 is a process of performing an erasing operation independently on each erase group, that is, an erasing process is implemented by simultaneously selecting all erasable units in the corresponding erase group and applying an erasing voltage, it should be understood that the current crosstalk or voltage drop problem is avoided, each erase group needs to perform an erasing operation in sequence, and the erasing voltages applied by each erase group do not interfere with each other, so that the nor flash erasing method according to the embodiment of the present application can perform batch erasing on partitions with similar erasing characteristics, thereby effectively avoiding an over-erasing phenomenon, and ensuring that the erasing operation is completed smoothly.
More specifically, the preset threshold is a parameter value set according to the use characteristics of the corresponding nor flash, and needs to be set in combination with the condition that the threshold voltage of a specific nor flash storage unit changes with respect to the Cycle times; it should be understood that, in the embodiment of the present application, when the difference between the Cycle times of the two partitions is smaller than or equal to the preset threshold, the erasing characteristics of the two partitions may be considered to be similar, and the two partitions can perform the erasing operation at the same time to save the erasing time.
According to the method for erasing the nor flash, the difference degree of the erasing characteristics of the storage units in the area to be erased is judged based on the Cycle times of all the partitions in the area to be erased, and when the difference value of the Cycle times is larger than a preset threshold value, the partitions are grouped according to the Cycle times and are respectively subjected to erasing operation, so that the partitions with similar erasing characteristics in each erasing group can be smoothly erased, the whole area to be erased can be successfully erased, and the problem that the erasing failure of the area to be erased is caused due to the fact that the erasing characteristics of different partitions are too different is effectively avoided.
In some preferred embodiments, when the erasure method of the nor flash in the embodiment of the present application is actually applied, whether to start or not can be selected according to the use requirement, or the erasure method can be automatically started according to the use times; in the initial use stage of the nor flash, the Cycle times of each storage area are small values, and the erasing difficulty of the whole storage array is relatively similar, so that the erasing efficiency of the erasing method of the nor flash in the initial use stage of the nor flash is not obviously improved.
Specifically, when the method of the embodiment of the present application is configured to be automatically started according to the number of times of use, the erasing method of the nor flash further includes the steps performed before step S1:
and S0, executing the step S1 after the using times or the starting times or the total erasing times of the nor flash are greater than a preset starting threshold.
It should be understood that if the number of times of use or the number of times of activation or the total number of times of erasing is less than or equal to the activation threshold, the area to be erased is subjected to a normal erasing operation, and if the area to be erased is the entire memory array, a full-chip erase (chip erase) is performed.
Specifically, the start threshold is a parameter value set according to the use characteristic of the corresponding nor flash, and needs to be set in combination with the change of the threshold voltage of the specific nor flash memory cell with respect to the number of times of erasing.
More specifically, in this embodiment, the degree of use of the nor flash can be quickly judged based on the start threshold, and it is possible to avoid the deterioration of the overall operation efficiency of the nor flash due to the execution of step S1 at the initial stage of use.
In some preferred embodiments, grouping all the partitions according to the size of Cycle times to obtain the erase group includes:
and S21, traversing the rest of the non-grouped partitions based on any non-grouped partition, acquiring the partitions with the Cycle number difference smaller than a preset threshold value to form an erasing group, and repeatedly executing the processes until all the partitions are grouped.
Specifically, after it is determined that there are partitions in the to-be-erased area where the Cycle number difference is greater than the preset threshold, the partitions need to be reasonably grouped, so that the Cycle number difference between the partitions in each erase group is smaller than the preset threshold, and it is ensured that the partitions in each erase group can be smoothly erased.
More specifically, in the embodiment, the traversal thinking is adopted to extract the partitions from the partition pool formed by all the partitions to form the erase group, so that the partitions in each erase group can be ensured to have similar erase performance, and the partitions can be effectively prevented from being missed in sorting.
In other embodiments, the step of grouping all the partitions according to the size of Cycle times to obtain the erase group may further include:
s21', grouping according to a plurality of preset divided Cycle frequency intervals and the Cycle frequency of each partition to obtain an erasing group.
In particular, in the embodiment mode, all the partitions are divided into different intervals by adopting the thinking of interval division, and partition grouping can be conveniently completed.
More specifically, the Cycle number interval is a numerical interval divided based on the Cycle number, and a difference between an upper limit value and a lower limit value of each Cycle number interval is smaller than or equal to a preset threshold value, so that the erasing characteristics of each partition in the erasing group divided based on the Cycle number interval are similar.
More specifically, the grouping can be completed conveniently by the above-mentioned dividing manner, and therefore, the erasure method of the nor flash in the embodiment of the present application preferably performs the grouping of the partitions by using the step S21'.
In some preferred embodiments, the number of cycles for each partition is stored based on a corresponding non-volatile counter (counter) count.
Specifically, the nonvolatile counter is a circuit device commonly used in the memory technology field, and is used for counting digital related data; in the embodiment of the application, each partition of the area to be erased is provided with a corresponding nonvolatile counter which is respectively used for recording the Cycle times of the corresponding partition; according to the erasing method of the nor flash, the Cycle times can be conveniently and accurately acquired by reading the data in the nonvolatile counter of each partition.
More specifically, each partition is counted by a corresponding configuration counter, so that the counting data of each partition can be ensured to be accurate and not interfered with each other.
In some preferred embodiments, when the area to be erased is the entire memory array, the partition is divided into blocks, half blocks or sectors.
Specifically, the erase operation of the nor flash is generally divided into: for a nor flash, the larger the area to be erased is, the more difficult it is to maintain the consistency of the erasing characteristics of the memory cells therein, and therefore, the erasing method of the nor flash in the embodiment of the present application sets the partition unit of a partition to be a block, a half block, or a sector.
In some preferred embodiments, the partition unit of the partition is determined based on the partition configuration information bits.
Specifically, the nor flash erasing method of the embodiment of the present application is intended to improve a large-scale erasing manner, such as a full-slice erasing (chip erase), an array erase (array erase), and a block erase (block erase), and when the improved erasing manner objects are the full-slice erasing (chip erase) and the array erase (array erase), a partition unit of a partition may be set to be a block, a half block, or a sector, and is preferably a block; when the improved erasing mode object is block erasing (block erase), the partition unit of the partition can be set as a sector to reasonably partition an area to be erased, so that the erasing operation is ensured to be successfully completed while the erasing efficiency is ensured to be relatively high.
More specifically, in the method for erasing a nor flash according to the embodiment of the present application, preferably, one partition configuration information bit is used to record partition configuration information, and step S1 includes:
reading partition configuration information of a corresponding partition configuration information bit according to the erasing operation command, and partitioning an area to be erased according to the partition configuration information;
and acquiring the Cycle times of each partition in the to-be-erased area, and calculating and acquiring the Cycle time difference between different partitions.
The erase operation command is one of a chip erase (chip erase), an array erase (array erase) and a block erase (block erase).
Specifically, the erasing method of the nor flash in the embodiment of the application can perform partitioning based on different partition units according to the type of the erasing operation, and reasonably call the erasing resources of the nor flash.
In some preferred embodiments, the preset threshold is 20000 times.
Specifically, since the life Cycle (Cycle number) of the nor flash memory chip is generally one hundred thousand times, and the preset threshold is set to 20000 times, partitions with different erasing characteristics can be effectively distinguished.
In a second aspect, referring to fig. 2, some embodiments of the present application further provide an erasing apparatus for a nor flash, configured to erase an area to be erased of the nor flash, where the apparatus includes:
the acquiring module 201 is configured to acquire the Cycle times of each partition in the to-be-erased area, and calculate and acquire a Cycle time difference between different partitions;
the grouping module 202 is configured to, when a Cycle time difference greater than a preset threshold exists, group all the partitions according to the Cycle time to obtain an erase group;
and the erasing module 203 is used for respectively performing erasing operation on each erasing group.
The nor flash erasing device provided by the embodiment of the application judges the difference degree of the erasing characteristics of the storage units in the area to be erased based on the Cycle times of each partition in the area to be erased, and when the Cycle time difference is larger than a preset threshold value, the partitions are grouped and respectively erased according to the Cycle times, so that the partitions with similar erasing characteristics in each erasing group can be smoothly erased, the whole area to be erased can be successfully erased, and the problem that the erasing failure is caused due to the overlarge difference of the erasing characteristics of different partitions in the area to be erased is effectively avoided.
In some preferred embodiments, the erasing apparatus of the nor flash according to the embodiment of the present application is configured to perform the erasing method of the nor flash provided in the first aspect.
In a third aspect, referring to fig. 3, some embodiments of the present application further provide a schematic structural diagram of an electronic device, where the present application provides an electronic device, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the electronic device is running to perform the method in any of the alternative implementations of the embodiments described above.
In a fourth aspect, the present application provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In summary, embodiments of the present application provide an erasing method, an erasing device, an erasing apparatus, and an erasing medium for a nor flash, where the erasing method for a nor flash determines a difference degree of erasing characteristics of storage units in a to-be-erased area based on Cycle times of respective partitions in the to-be-erased area, and when a difference value of the Cycle times is greater than a preset threshold, the partitions are grouped and respectively erased according to the Cycle times, so that partitions with similar erasing characteristics in each erasing group can be smoothly erased, thereby ensuring that the entire to-be-erased area can be successfully erased, and effectively avoiding an erasing failure problem caused by too large difference of erasing characteristics of different partitions in the to-be-erased area.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. An erasing method of a nor flash, which is used for erasing an area to be erased of the nor flash, and is characterized by comprising the following steps:
acquiring the Cycle times of each partition in the to-be-erased area, and calculating and acquiring the Cycle time difference between different partitions;
when a Cycle time difference value larger than a preset threshold value exists, grouping all the partitions according to the Cycle time to obtain an erasing group;
and respectively carrying out erasing operation on each erasing group.
2. The method of claim 1, wherein the step of grouping all the partitions according to the Cycle times to obtain the erase group comprises:
and traversing the rest of the non-grouped partitions based on any one of the non-grouped partitions, acquiring the partitions of which the Cycle number difference is smaller than the preset threshold value to form an erasing group, and repeatedly executing the processes until all the partitions are grouped.
3. The method of claim 1, wherein the step of grouping all the partitions according to the Cycle times to obtain the erase group comprises:
and grouping according to a plurality of preset divided Cycle frequency intervals and the Cycle frequency of each partition to obtain an erasing group.
4. An erasing method of a nor flash as claimed in claim 1, wherein the Cycle number of each of the partitions is stored based on a corresponding non-volatile counter count.
5. The method of claim 1, wherein the partition is divided into blocks, half blocks or sectors when the area to be erased is the entire memory array.
6. The nor flash erase method of claim 5, wherein the partition unit of the partition is determined based on a partition configuration information bit.
7. An erasing method of a nor flash as claimed in claim 1, wherein the predetermined threshold is 20000 times.
8. An erasing apparatus of a nor flash, for erasing an area to be erased of the nor flash, the apparatus comprising:
the acquisition module is used for acquiring the Cycle times of each partition in the to-be-erased area and calculating and acquiring the Cycle time difference between different partitions;
the grouping module is used for grouping all the partitions according to the Cycle times to acquire an erasing group when a Cycle time difference value larger than a preset threshold value exists;
and the erasing module is used for respectively performing erasing operation on each erasing group.
9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method according to any one of claims 1 to 7.
10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-7.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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