CN115279060A

CN115279060A - Circuit board processing method and circuit board

Info

Publication number: CN115279060A
Application number: CN202111401656.0A
Authority: CN
Inventors: 周亚军; 霍佳仁; 宋关强; 刘德波
Original assignee: Sky Chip Interconnection Technology Co Ltd
Current assignee: Sky Chip Interconnection Technology Co Ltd
Priority date: 2021-11-19
Filing date: 2021-11-19
Publication date: 2022-11-01

Abstract

The application discloses a circuit board processing method and a circuit board, wherein the processing method comprises the following steps: obtaining a plate to be processed; the plate to be processed comprises a plurality of separated welding pads; mounting a chip on one of the bonding pads; welding a lead on the surface of one side of the chip far away from the bonding pad; after laminating the insulating material with the copper base material, the chip and the conducting wire, grinding the insulating material to form a first insulating medium layer; forming a first blind hole on a peripheral bonding pad of the bonding pad attached with the chip; carrying out whole-board electroplating on the plate to be processed so as to form a first connecting column in the first blind hole and form a first conductive circuit on the surface of one side, away from the copper substrate, of the first insulating medium layer; the first conductive circuit covers the top of one side of the wire far away from the chip and the first connecting column, and is used for realizing interconnection between the chip and the copper substrate. The method and the device solve the problem that the chip aluminum pin cannot be directly processed in the PLFO process.

Description

Circuit board processing method and circuit board

Technical Field

The application relates to the technical field of circuit board processing, in particular to a circuit board processing method and a circuit board.

Background

With the development of the 5G technology, electronic products have more and more comprehensive functions and smaller volumes, so that the requirements on circuit boards are higher and higher, and the PCB industry is driven to develop towards high density, high integration and multilayering. Mosfet (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) are applied to almost all power industry products, and power devices are developed to high performance, fast speed, small volume and multi-chip connection packaging.

In the prior art, a PLFO (planar level Fan-out) is generally adopted to package a chip. In the PLFO process, a chip is usually soldered on a bottom pad, and in order to interconnect the chip and a substrate, a small blind hole needs to be formed above one side of the chip far away from the bottom pad, a large blind hole needs to be formed on the other bottom pad close to the chip, copper is plated in the blind hole, and electrical interconnection is realized through the blind hole interconnection.

However, if the chip pin is made of aluminum, the PLFO process involves the problem of modifying the chip pin because the melting point of aluminum is low and chemical formation is active, i.e., the aluminum pin needs to be modified in advance, so that the aluminum pin is prevented from being damaged by high temperature and corrosive liquid in the process of forming the blind hole.

Disclosure of Invention

The technical problem mainly solved by the application is to provide a circuit board processing method and a circuit board, and the problem that a chip aluminum pin cannot be directly processed in the prior art can be solved.

In order to solve the above technical problem, a first technical solution adopted by the present application is to provide a circuit board processing method, including: obtaining a plate to be processed; the plate to be processed is a patterned copper base material, and the copper base material comprises a plurality of separated welding pads; obtaining a chip, and mounting the chip on one bonding pad; welding a lead on the surface of one side of the chip away from the bonding pad; obtaining an insulating material, pressing the insulating material with a copper base material, a chip and a lead, and grinding the insulating material to form a first insulating medium layer; the first insulating medium layer is positioned around the lead and covers the surface of one side of the copper substrate, which is in contact with the chip, and the surface of one side of the chip, which is far away from the copper substrate; processing a first preset position of the first insulating medium layer until one side surface of the copper base material is exposed so as to form a first blind hole on a peripheral bonding pad attached with a chip; carrying out whole-plate electroplating on the plate to be processed with the first blind hole so as to form a first connecting column in the first blind hole and form a first conductive circuit on the surface of one side, away from the copper substrate, of the first insulating medium layer; the first conductive circuit covers the top of one side of the wire far away from the chip and the first connecting column, and is used for realizing interconnection between the chip and the copper substrate.

The step of obtaining a chip and mounting the chip on one of the pads specifically includes: and coating a conductive adhesive on one side surface of the bonding pad, and mounting a chip on the conductive adhesive.

The step of welding the wire on the surface of one side of the chip far away from the bonding pad specifically comprises: and welding the wires on the surface of the chip far away from the bonding pad by using a wire bonding mode.

The method comprises the steps of obtaining an insulating material, pressing the insulating material with a copper base material, a chip and a wire, grinding the insulating material to form a first insulating medium layer, and specifically comprises the following steps: obtaining an insulating material, and pressing the insulating material, the copper base material, the chip and the lead so that the insulating material covers the surface of one side, which is in contact with the chip, of the copper base material, the surface of one side, which is far away from the copper base material, of the chip and the top end of one side, which is far away from the chip, of the lead; grinding the insulating material until the top end of one side of the lead, which is far away from the chip, is exposed to form a first insulating medium layer; the first insulating medium layer is positioned around the lead and covers one side surface of the copper substrate, which is contacted with the chip, and one side surface of the chip, which is far away from the copper substrate.

Wherein, carry out whole board electroplating to the panel of treating that is formed with first blind hole to form first connecting post in first blind hole, and before the step of the first conducting wire of the side surface formation of keeping away from the copper substrate at first insulating medium layer, still include: and forming a conductive seed layer on the surface of one side of the first insulating medium layer, which is far away from the copper substrate, and the hole wall of the first blind hole by adopting a chemical copper plating mode.

Wherein, carry out whole board electroplating to the panel of treating that is formed with first blind hole to form first connecting post in first blind hole, and keep away from the step of copper substrate's a side surface formation first conducting wire at first insulating medium layer, specifically include: carrying out whole-plate electroplating on the plate to be processed with the first blind hole so as to form a first connecting column in the first blind hole and form a first conducting layer on the surface of one side, away from the copper substrate, of the first insulating medium layer; attaching a first dry film on the first conductive layer, and exposing a second preset position on the first conductive layer; etching the first conductive layer to form a first conductive circuit on the first conductive layer; the first conductive circuit covers the top of one side of the wire far away from the chip and the first connecting column, and is used for realizing interconnection between the chip and the copper substrate.

Wherein, after the step of etching the first conductive layer to form the first conductive circuit on the first conductive layer, the method further comprises: and obtaining an insulating material, and laminating the insulating material and the surface of one side of the first conductive circuit, which is far away from the first insulating medium layer, and the surface of one side of the first insulating medium layer, which is far away from the copper substrate to form a second insulating medium layer.

Wherein the insulating material comprises one or more of epoxy resin, phenolic resin, polyimide, BT, ABF and ceramic base.

In order to solve the above technical problem, a second technical solution adopted by the present application is to provide a circuit board, including: a patterned copper substrate comprising a plurality of spaced apart pads; the chip is arranged on one bonding pad; the conducting wire is arranged on the surface of one side of the chip, which is far away from the copper substrate; the first insulating medium layer is positioned around the lead and covers the surface of one side, which is in contact with the chip, of the copper substrate and the surface of one side, which is far away from the copper substrate, of the chip; the first blind hole is arranged on a peripheral bonding pad of the bonding pad attached with the chip; the first connecting column is arranged in the first blind hole; and the first conductive circuit covers the top of one side of the wire far away from the chip and the first connecting column and is used for realizing interconnection between the chip and the copper substrate.

The circuit board further comprises a second insulating medium layer, and the second insulating medium layer is arranged on the surface of one side, away from the first insulating medium layer, of the first conducting circuit and the surface of one side, away from the copper substrate, of the first insulating medium layer.

The beneficial effect of this application is: different from the prior art, the application provides a circuit board processing method and a circuit board, a lead is welded on the surface of one side, far away from a bonding pad, of a chip, a blind hole can be prevented from being formed in a chip pin, and the lead bonding mode does not need to be carried out at a high temperature or electroplating, so that the chip pin does not need to be modified, and the problem that a chip aluminum pin cannot be directly processed in a PLFO process is solved. Furthermore, the wires are interconnected with the first blind holes through the first conductive circuit instead of the wire arcs, so that the wire arcs are prevented from increasing the height of the whole device, and the miniaturization and the lightness of the packaging device are realized.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic flow chart of one embodiment of a method for processing a circuit board according to the present application;

fig. 2 is a schematic structural view of an embodiment of the plate to be processed obtained in S11;

fig. 3 is a schematic structural view of an embodiment of the plate to be processed obtained in S12;

fig. 4 is a schematic structural view of an embodiment of the plate to be processed obtained in S13;

fig. 5 is a schematic structural view of an embodiment of the plate to be processed acquired in S14;

fig. 6 is a schematic structural view of an embodiment of the plate to be processed acquired in S15;

FIG. 7 is a schematic flow chart of one embodiment of S16 of FIG. 1;

fig. 8 is a schematic structural view of an embodiment of the plate to be processed acquired in S161;

fig. 9 is a schematic structural view of an embodiment of the plate to be processed acquired in S163;

fig. 10 is a schematic structural diagram of an embodiment of the wiring board of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plural" includes at least two in general, but does not exclude the presence of at least one.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

In the prior art, a PLFO (planar level Fan-out) is generally adopted to package a chip. In the PLFO process, a chip is usually soldered to a bottom pad, and in order to interconnect the chip and a substrate, a small blind hole needs to be formed above one side of the chip away from the bottom pad, and a large blind hole needs to be formed in the other bottom pad close to the chip, and copper is plated in the blind hole, so that electrical interconnection is realized through the blind hole interconnection. However, if the chip pin is made of aluminum, the PLFO process involves the problem of modifying the chip pin because the melting point of aluminum is low and chemical formation is active, i.e., the aluminum pin needs to be modified in advance, so that the aluminum pin is prevented from being damaged by high temperature and corrosive liquid in the process of forming the blind hole.

Based on the situation, the application provides a circuit board processing method and a circuit board, and the problem that a chip aluminum pin cannot be directly processed in the prior art can be solved.

The present application will be described in detail below with reference to the drawings and embodiments.

Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of the method for processing a circuit board of the present application. As shown in fig. 1, in the present embodiment, the method includes:

s11: obtaining a plate to be processed; the plate to be processed is a patterned copper base material, and the copper base material comprises a plurality of separated welding pads.

In this embodiment, a complete copper substrate is obtained first, and then the copper substrate is etched by chemical etching or physical etching to form a circuit pattern on the copper substrate, where the patterned copper substrate includes a plurality of divided pads. For ease of description, reference to copper substrates hereinafter will be made to patterned copper substrates.

Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of the plate to be processed obtained in S11. As shown in fig. 2, the sheet material to be processed 100 includes a first pad 10 and a second pad 20 which are separated.

In the present embodiment, the edges of the first pad 10 and the second pad 20 are flat, but in the actual etching, the edges of the first pad 10 and the second pad 20 often have some bumps due to the undercut.

S12: and obtaining a chip, and mounting the chip on one of the bonding pads.

In this embodiment, a conductive adhesive is applied to one surface of the pad, and a chip is attached to the conductive adhesive.

The conductive adhesive can be solder paste, silver paste and the like.

Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of the plate to be processed obtained in S12. As shown in fig. 3, the plate material to be processed 200 includes a first pad 10 and a second pad 20 which are separated. And a chip 30, wherein the chip 30 is arranged on the first bonding pad 10. Wherein the chip 30 is bonded to the first pad 10 by the conductive adhesive 11.

S13: and welding the wires on the surface of one side of the chip far away from the bonding pad.

In this embodiment, a wire is bonded to the surface of the chip on the side away from the bonding pad by wire bonding.

Specifically, wire bonding is a process of using thin metal wires to tightly bond metal leads and substrate pads by using heat, pressure or ultrasonic energy, thereby achieving electrical interconnection between chips and substrates and information intercommunication between chips. Under ideal control conditions, electron sharing or atomic interdiffusion can occur between the lead and the substrate, so that atomic-scale bonding between the two metals is realized.

Bonding can be classified into hot pressure welding, cold ultrasonic bonding, and hot ultrasonic bonding according to bonding conditions. Depending on the lead, the bonding process can be gold wire, copper wire or aluminum wire. Wherein, cold ultrasonic bonding is usually aluminum wire wedge bonding, and thermosonic bonding is usually gold wire ball bonding, and because of using hot pressing and ultrasonic energy simultaneously, can realize better bonding quality under lower temperature.

It can be understood that, unlike the higher heat required for drilling blind holes in the prior art, the wire bonding method of the present embodiment can wedge the wire into the surface of one side of the chip at a lower temperature, thereby avoiding melting of the aluminum pins on the surface of the chip due to high temperature. And because the wire is a metal wire, copper plating operation is not needed, and the aluminum pin can be prevented from being corroded, so that the aluminum pin of the chip is not needed to be modified, and the problem that the aluminum pin of the chip cannot be directly processed in a PLFO process is solved.

Furthermore, the wire diameter of the lead is small, so that the wire bonding process is not limited by the problems of small window and the like of a blind hole processing process above a chip.

In other embodiments, when the material of the chip surface is copper, silver, nickel-gold or nickel-palladium-gold, the wire may also be bonded to the side surface of the chip away from the bonding pad by wire bonding (wire bonding), which is not limited in this application.

Specifically, referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of the plate to be processed obtained in S13. As shown in fig. 4, the plate material 300 to be processed includes a first pad 10 and a second pad 20 which are separated. And a chip 30, wherein the chip 30 is arranged on the first bonding pad 10. Wherein the chip 30 is bonded to the first pad 10 by the conductive adhesive 11. And the lead 31, wherein the lead 31 is arranged on the surface of the chip 30 far away from the first bonding pad 10.

S14: obtaining an insulating material, pressing the insulating material with a copper base material, a chip and a lead, and grinding the insulating material to form a first insulating medium layer; the first insulating medium layer is positioned around the conducting wire and covers one side surface of the copper base material, which is contacted with the chip, and one side surface of the chip, which is far away from the copper base material.

In this embodiment, the insulating material is obtained, and the insulating material is pressed with the copper base material, the chip, and the wire, so that the insulating material covers a surface of the copper base material, which is in contact with the chip, a surface of the chip, which is far away from the copper base material, and a top end of the wire, which is far away from the chip.

Further, the insulating material is ground until the top end of one side of the lead wire, which is far away from the chip, is exposed, so that a first insulating medium layer is formed. It can be understood that the first insulating medium layer may perform plastic encapsulation and protection on the chip.

In the present embodiment, the insulating material includes one or more of epoxy resins, phenol resins, polyimides, BT resins, ABF resins, and ceramic substrates, but the present invention is not limited thereto.

Specifically, referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of the plate to be processed obtained in S14. As shown in fig. 5, the plate material 400 to be processed includes a first pad 10 and a second pad 20 which are separated. And a chip 30, wherein the chip 30 is arranged on the first bonding pad 10. Wherein the chip 30 is bonded to the first pad 10 by the conductive adhesive 11. And the lead 31, wherein the lead 31 is arranged on the surface of the chip 30 far away from the first bonding pad 10. And the first insulating medium layer 40 is positioned around the wire 31 and covers one side surface of the first bonding pad 10, which is in contact with the chip 30, one side surface of the chip 30, which is far away from the first bonding pad 10, of the second bonding pad 20 and a separation area between the first bonding pad 10 and the second bonding pad 20.

S15: and processing the first preset position of the first insulating medium layer until one side surface of the copper base material is exposed so as to form a first blind hole on the peripheral bonding pad attached with the chip.

In this embodiment, a first predetermined position of the first insulating medium layer is subjected to surface treatment by chemical etching or physical etching, so as to form a first blind via on a peripheral pad to which a chip is attached.

The first preset position comprises a first blind hole and the peripheral position of the hole. In other embodiments, the first preset position may only include the position of the first blind hole, which is not limited in this application.

Specifically, referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment of the plate to be processed obtained in S15. As shown in fig. 6, the plate material 500 to be processed includes a first pad 10 and a second pad 20 which are separated. And a chip 30, wherein the chip 30 is arranged on the first bonding pad 10. Wherein the chip 30 is bonded to the first pad 10 by the conductive adhesive 11. And the lead 31, wherein the lead 31 is arranged on the surface of the chip 30 far away from the first bonding pad 10. And the first insulating medium layer 40 is positioned around the wire 31 and covers one side surface of the first bonding pad 10, which is in contact with the chip 30, one side surface of the chip 30, which is far away from the first bonding pad 10, of the second bonding pad 20 and a separation area between the first bonding pad 10 and the second bonding pad 20. And a first blind hole 41, the first blind hole 41 being disposed on the second pad 20.

S16: carrying out whole-plate electroplating on the plate to be processed with the first blind hole so as to form a first connecting column in the first blind hole and form a first conductive circuit on the surface of one side, away from the copper substrate, of the first insulating medium layer; the first conductive circuit covers the top of one side of the wire far away from the chip and the first connecting column, and is used for realizing interconnection between the chip and the copper substrate.

In this embodiment, before the board to be processed is subjected to the whole board electroplating, a conductive seed layer is formed on the surface of the first insulating medium layer, which is far away from the copper substrate, and the hole wall of the first blind hole by using a chemical copper plating method.

In another embodiment, a conductive seed layer may be formed on both the surface of the first insulating medium layer away from the copper substrate and the wall of the first blind via by carbon adsorption such as black holes, shadow, or graphene oxide.

In yet another embodiment, a conductive seed layer may be further formed on both a surface of the first insulating dielectric layer away from the copper substrate and a wall of the first blind via by coating with a conductive high molecular polymer.

Specifically, referring to fig. 7, fig. 7 is a schematic flow chart of an embodiment of S16 in fig. 1. As shown in fig. 7, in the present embodiment, the board to be processed, on which the first blind hole is formed, is subjected to whole board electroplating to form the first connection pillar in the first blind hole, and form the first conductive trace on the surface of the first insulating medium layer on the side away from the copper substrate; the first conductive circuit covers the top of one side of the wire far away from the chip and the first connecting column, and the step for realizing interconnection between the chip and the copper substrate specifically comprises the following steps:

s161: and carrying out whole-plate electroplating on the plate to be processed with the first blind hole so as to form a first connecting column in the first blind hole and form a first conducting layer on the surface of one side, away from the copper substrate, of the first insulating medium layer.

Specifically, referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment of the plate to be processed obtained in S161. As shown in fig. 8, the plate material 600 to be processed includes a first pad 10 and a second pad 20 which are separated. And a chip 30, wherein the chip 30 is arranged on the first bonding pad 10. Wherein the chip 30 is bonded to the first pad 10 by the conductive adhesive 11. And the lead 31, wherein the lead 31 is arranged on the surface of the chip 30 far away from the first bonding pad 10. And the first insulating medium layer 40 is positioned around the wire 31 and covers one side surface of the first bonding pad 10, which is in contact with the chip 30, one side surface of the chip 30, which is far away from the first bonding pad 10, of the second bonding pad 20 and a separation area between the first bonding pad 10 and the second bonding pad 20. And a first blind hole 41, the first blind hole 41 being disposed on the second pad 20. The first connecting post 42 is disposed in the first blind hole 41, and the first connecting post 42 is disposed in the first blind hole 41. And the first conductive layer 50 is disposed on a surface of the first insulating medium layer 40 away from the first bonding pad 10, and covers a top end of a side of the wire 31 away from the chip 30 and a surface of a side of the first connection pillar 42 away from the second bonding pad 20.

S162: and attaching the first dry film on the first conductive layer, and exposing the second preset position on the first conductive layer.

In this embodiment, the second preset position is a position on the plate to be processed where no conductive circuit needs to be manufactured.

Wherein the first dry film is a resist photosensitive film. The resist photosensitive film is a high molecular compound which can generate a polymerization reaction (a reaction process of synthesizing a polymer from a monomer) after being irradiated by a specific light source to form a stable substance to be attached to a plate surface, thereby achieving the function of etching resistance.

S163: etching the first conductive layer to form a first conductive circuit on the first conductive layer; the first conductive circuit covers the top of one side of the wire far away from the chip and the first connecting column, and is used for realizing interconnection between the chip and the copper substrate.

As can be understood, since the wires are interconnected with the first blind holes through the first conductive traces, rather than being interconnected through the wire loops, the wire loops are prevented from increasing the height of the whole device, thereby realizing miniaturization and lightness of the packaged device.

As can be appreciated, the electrical interconnection of the chip through the first conductive traces can also enhance the heat dissipation of the chip, thereby improving the heat dissipation effect of the whole device.

Specifically, referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of the plate to be processed obtained in S163. As shown in fig. 9, the plate material 700 to be processed includes a first pad 10 and a second pad 20 which are separated. And a chip 30, wherein the chip 30 is arranged on the first bonding pad 10. Wherein the chip 30 is bonded to the first pad 10 by the conductive adhesive 11. And a wire 31, wherein the wire 31 is arranged on the surface of one side of the chip 30 far away from the first bonding pad 10. And the first insulating medium layer 40 is positioned around the wire 31 and covers one side surface of the first bonding pad 10, which is in contact with the chip 30, one side surface of the chip 30, which is far away from the first bonding pad 10, of the second bonding pad 20 and a separation area between the first bonding pad 10 and the second bonding pad 20. And a first blind hole 41, the first blind hole 41 being disposed on the second pad 20. The first connecting post 42 is disposed in the first blind hole 41, and the first connecting post 42 is disposed in the first blind hole 41. And the first conductive line 51, the first conductive line 51 is arranged on the surface of one side of the first insulating medium layer 40 far away from the first bonding pad 10, and covers the top of one side of the wire 31 far away from the chip 30 and the first connecting column 42, so as to realize interconnection between the chip 30 and the second bonding pad 20.

In this embodiment, in order to protect the first conductive line, a second insulating medium layer is further provided on the first conductive line. Specifically, the insulating material is obtained, and the insulating material and the surface of one side, away from the first insulating medium layer, of the first conductive circuit and the surface of one side, away from the copper base material, of the first insulating medium layer are pressed to form a second insulating medium layer.

The insulating material includes one or more of epoxy resins, phenolic resins, polyimides, BT, ABF and ceramic base, which is not limited in the present application.

Different from the prior art, the lead bonding method has the advantages that the lead is welded on the surface of one side, far away from the bonding pad, of the chip, the blind hole can be prevented from being formed in the chip pin, and the lead bonding mode does not need to be carried out at high temperature or electroplating, so that the chip pin does not need to be modified, and the problem that the chip aluminum pin cannot be directly processed in a PLFO process is solved. Furthermore, the wires are interconnected with the first blind holes through the first conductive circuit instead of the wire arcs, so that the wire arcs are prevented from increasing the height of the whole device, and the miniaturization and the lightness of the packaging device are realized.

Correspondingly, the application provides a circuit board.

Specifically, please refer to fig. 10, fig. 10 is a schematic structural diagram of an embodiment of the circuit board of the present application.

As shown in fig. 10, the wiring board 800 includes a first pad 10 and a second pad 20 separated. And a chip 30, wherein the chip 30 is arranged on the first bonding pad 10. Wherein the chip 30 is bonded to the first pad 10 by the conductive adhesive 11. And a wire 31, wherein the wire 31 is arranged on the surface of one side of the chip 30 far away from the first bonding pad 10. And the first insulating medium layer 40 is positioned around the wire 31 and covers one side surface of the first bonding pad 10, which is in contact with the chip 30, one side surface of the chip 30, which is far away from the first bonding pad 10, of the second bonding pad 20 and a separation area between the first bonding pad 10 and the second bonding pad 20. And a first blind hole 41, the first blind hole 41 being disposed on the second pad 20. The first connecting post 42 is disposed in the first blind hole 41, and the first connecting post 42 is disposed in the first blind hole 41. And the first conductive line 51, the first conductive line 51 is arranged on the surface of one side of the first insulating medium layer 40 far away from the first bonding pad 10, and covers the top of one side of the wire 31 far away from the chip 30 and the first connecting column 42, so as to realize interconnection between the chip 30 and the second bonding pad 20. And the second insulating medium layer 60, wherein the second insulating medium layer 60 is arranged on the surface of one side of the first conductive line 51 far away from the first insulating medium layer 40 and the surface of one side of the first insulating medium layer 40 far away from the first bonding pad 10.

Different from the prior art, the circuit board provided by the embodiment can avoid forming blind holes on chip pins by wedging the wires above the chip to realize electrical interconnection, and the lead bonding mode does not need to carry out electroplating or higher temperature, so that the chip pins do not need to be modified, and the problem that the chip aluminum pins cannot be directly processed in a PLFO process is solved. Furthermore, the wires are interconnected with the first blind holes through the first conductive circuit instead of the wire arcs, so that the wire arcs are prevented from increasing the height of the whole device, and the miniaturization and the lightness of the packaging device are realized.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A circuit board processing method is characterized by comprising the following steps:

obtaining a plate to be processed; the plate to be processed is a patterned copper base material, and the copper base material comprises a plurality of separated welding pads;

obtaining a chip, and mounting the chip on one of the bonding pads;

welding a lead on the surface of one side of the chip far away from the bonding pad;

obtaining an insulating material, pressing the insulating material with the copper base material, the chip and the lead, and then grinding the insulating material to form a first insulating medium layer; the first insulating medium layer is positioned around the lead and covers one side surface of the copper base material, which is contacted with the chip, and one side surface of the chip, which is far away from the copper base material;

processing a first preset position of the first insulating medium layer until one side surface of the copper base material is exposed so as to form a first blind hole on a peripheral bonding pad attached with the chip;

carrying out whole-plate electroplating on the plate to be processed with the first blind hole so as to form a first connecting column in the first blind hole and form a first conductive circuit on the surface of one side, far away from the copper substrate, of the first insulating medium layer; the first conductive circuit covers the top of one side of the wire far away from the chip and the first connecting column, and is used for realizing interconnection of the chip and the copper base material.

2. The method for processing a circuit board according to claim 1, wherein the step of obtaining a chip and mounting the chip on one of the pads specifically comprises:

and coating a conductive adhesive on the surface of one side of the bonding pad, and mounting the chip on the conductive adhesive.

3. The circuit board processing method according to claim 1, wherein the step of soldering the wire on the surface of the chip on the side away from the bonding pad specifically comprises:

and welding the wire on the surface of one side of the chip far away from the bonding pad by using a wire bonding mode.

4. The circuit board processing method according to claim 1, wherein the step of obtaining an insulating material, pressing the insulating material with the copper base material, the chip, and the wire, and then grinding the insulating material to form a first insulating dielectric layer specifically comprises:

obtaining the insulating material, and pressing the insulating material, the copper base material, the chip and the wire to enable the insulating material to cover the surface of one side, which is in contact with the chip, of the copper base material, the surface of one side, which is far away from the copper base material, of the chip and the top end of one side, which is far away from the chip, of the wire;

grinding the insulating material until the top end of one side of the lead, which is far away from the chip, is exposed to form a first insulating medium layer; the first insulating medium layer is positioned around the lead and covers one side surface of the copper base material, which is contacted with the chip, and one side surface of the chip, which is far away from the copper base material.

5. The method for processing a circuit board according to claim 1, wherein the step of performing full-board electroplating on the board to be processed on which the first blind hole is formed to form the first connection post in the first blind hole, and the step of forming the first conductive trace on the surface of the first insulating medium layer on the side away from the copper substrate further comprises:

and forming a conductive seed layer on the surface of one side of the first insulating medium layer, which is far away from the copper substrate, and the hole wall of the first blind hole by adopting a chemical copper plating mode.

6. The method for processing the circuit board according to claim 5, wherein the step of performing full-board electroplating on the board to be processed, on which the first blind hole is formed, to form the first connection post in the first blind hole, and to form the first conductive circuit on a surface of the first insulating dielectric layer on a side away from the copper substrate specifically comprises:

carrying out whole-plate electroplating on the plate to be processed with the first blind hole so as to form the first connecting column in the first blind hole and form a first conducting layer on the surface of one side, far away from the copper base material, of the first insulating medium layer;

attaching a first dry film on the first conductive layer, and exposing a second preset position on the first conductive layer;

etching the first conductive layer to form the first conductive line on the first conductive layer; the first conductive circuit covers the top of one side of the wire, which is far away from the chip, and the first connecting column, and is used for realizing interconnection of the chip and the copper base material.

7. The method for processing a circuit board according to claim 6, wherein after the step of etching the first conductive layer to form the first conductive trace on the first conductive layer, the method further comprises:

and obtaining the insulating material, and laminating the insulating material and the surface of one side of the first conductive circuit, which is far away from the first insulating medium layer, and the surface of one side of the first insulating medium layer, which is far away from the copper substrate to form a second insulating medium layer.

8. The method of processing a wiring board according to claim 7, wherein the insulating material includes one or more of epoxy resins, phenol resins, polyimides, BT, ABF and ceramic base.

9. A circuit board, comprising:

a patterned copper substrate comprising a plurality of spaced apart pads;

a chip disposed on one of the pads;

the conducting wire is arranged on the surface of one side, far away from the copper substrate, of the chip;

the first insulating medium layer is positioned around the lead and covers the surface of one side, which is in contact with the chip, of the copper substrate and the surface of one side, which is far away from the copper substrate, of the chip;

the first blind hole is arranged on a peripheral bonding pad attached with the bonding pad of the chip;

the first connecting column is arranged in the first blind hole;

the first conductive circuit covers the top of one side, far away from the chip, of the wire and the first connecting column, and is used for achieving interconnection of the chip and the copper base material.

10. The wiring board of claim 9, further comprising a second insulating dielectric layer disposed on a surface of the first conductive trace on a side away from the first insulating dielectric layer and a surface of the first insulating dielectric layer on a side away from the copper substrate.