CN115279020A - Connecting structure of small pad pitch chip and PCB and processing method thereof - Google Patents
Connecting structure of small pad pitch chip and PCB and processing method thereof Download PDFInfo
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- CN115279020A CN115279020A CN202210913549.4A CN202210913549A CN115279020A CN 115279020 A CN115279020 A CN 115279020A CN 202210913549 A CN202210913549 A CN 202210913549A CN 115279020 A CN115279020 A CN 115279020A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/858—Bonding techniques
- H01L2224/85801—Soldering or alloying
Abstract
The invention discloses a connecting structure of a chip with small pad spacing and a PCB (printed circuit board), which comprises a PCB (printed circuit board) substrate, a plurality of adapter plates and chips, wherein the adapter plates and the chips are stacked, the chips are provided with chip pads, the PCB is provided with leading-out pads, the adapter plates are fixed on the PCB substrate and positioned between the chips and the leading-out pads, each layer of connecting plate is provided with a plurality of first pads and a plurality of second pads which are respectively arranged in rows, the first pads and the second pads are correspondingly conducted one by one through printed circuits, the chip pads and the first pads as well as the second pads and the leading-out pads are connected through gold wires, and the spacing of the chip pads is less than the spacing of the first pads and less than the spacing of the second pads and less than the spacing of the leading-out pads. The invention discloses a processing method of a connecting structure, which solves the problem of leading-out of a chip with a small bonding pad interval and reduces the process difficulty.
Description
Technical Field
The invention relates to a chip and PCB (printed circuit board) connecting structure, in particular to a connecting structure of a chip and a PCB with a small pad pitch and a processing method thereof.
Background
In the application of optoelectronic chips, the size of the module is often limited, and the size of the chip is related to the cost, so that the size design of the chip pursues minimization, and the size and the space design of pads (bonding pads) on the chip are relatively small, so that the space of about 20um can be realized. Because the PCB has many layers and the surface has factors such as circuit, via hole, through-hole and component arrangement, even if the line width line distance of the carrier plate technology is conventionally 45um to 50um, the minimum distance of Pad size on the PCB needs 100um to 110um. It is a technical challenge how to bring out the dense pads on the chip onto the PCB, and the size of the PCB needs to be as small as possible.
If the chip is directly led out, the position offset size of the welding Pad exceeds the safe length of the gold wire bonding equipment due to the difference between the Pad pitch of the chip and the Pad pitch of the PCB. The mainstream wire bonder brand is ASM/KS/KAIJO and the like, the length of a gold wire which can be generally welded is within 6mm, the gold wire cannot be welded when the length exceeds the size, the length of the gold wire is too long, and the welded shape, radian and height cannot be controlled through parameters. Therefore, the Pad of the chip with the dense Pad spacing has more quantity and more layers and has small spacing, so that the length of a gold thread is overlong and the angle is too small due to the size problem when the Pad is welded with a PCB, and the chip cannot be directly welded with the Pad of the PCB by the gold thread.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a connecting structure of a small pad pitch chip and a PCB, and solves the problem of connection between the small pad pitch chip and a pad of the PCB. Another task of the present invention is to provide a method for connecting a small inter-pad-distance chip to a PCB.
The technical scheme of the invention is as follows: the utility model provides a connection structure of little pad interval chip and PCB, includes PCB base plate, a plurality of keysets and the chip of range upon range of setting, the chip is equipped with the chip pad, the PCB board is equipped with draws forth the pad, the keysets is fixed in on the PCB base plate and be located the chip with draw forth between the pad, every layer the connecting plate is equipped with a plurality of first pads and a plurality of second pads that become to arrange in line respectively, first pad with the second pad switches on through printed circuit one-to-one, the chip pad with between the first pad and the second pad with draw forth and connect through the gold thread between the pad, the interval of chip pad < the interval of first pad is not more than the interval of second pad < the interval of drawing forth the pad.
Furthermore, the first bonding pad and the second bonding pad are respectively arranged on two opposite edges of the surface of the connecting plate, the connecting plate on the upper layer is positioned between the first bonding pad and the second bonding pad of the connecting plate on the lower layer, the first bonding pad is close to the chip, and the second bonding pad is close to the leading-out bonding pad.
Furthermore, the chip bonding pads and the lead-out bonding pads are arranged into a plurality of rows, each row of the chip bonding pads is connected with the first bonding pad of one connecting plate, and each row of the lead-out bonding pads is connected with the second bonding pad of one connecting plate.
Further, the distance between the chip bonding pads is not more than 25 microns, and the distance between the lead-out bonding pads is not less than 100 microns.
A method for processing a connecting structure of a small pad pitch chip and a PCB comprises the following steps:
s1, fixing a chip on a PCB substrate, wherein the chip is provided with a plurality of chip bonding pads, and the PCB substrate is provided with a plurality of leading-out bonding pads;
s2, a layer of adapter plate is fixed between the chip and the lead-out bonding pad on the PCB substrate, and a plurality of first bonding pads and second bonding pads which are conducted through printed circuits in a one-to-one correspondence mode are arranged on the adapter plate;
s3, welding and conducting the chip bonding pad and the first bonding pad by using a gold wire, and welding and conducting the second bonding pad and the lead-out bonding pad by using a gold wire;
s4, fixing another layer of adapter plate on the lower layer of adapter plate;
s5, welding and conducting the chip bonding pad and a first bonding pad of the adapter plate on the top layer through a gold wire, and welding and conducting a second bonding pad of the adapter plate on the top layer and the lead-out bonding pad through the gold wire;
s6, repeating the steps S4 and S5 until all chip bonding pads and lead-out bonding pads are welded
The distance between the chip bonding pads is smaller than the distance between the first bonding pads and smaller than the distance between the second bonding pads and smaller than the distance between the leading-out bonding pads.
Further, when another interposer is fixed in step S4, the interposer on the upper layer is located between the first pad and the second pad of the interposer on the lower layer.
Furthermore, the chip is fixedly bonded with the PCB substrate, the connecting plate is fixedly bonded with the PCB substrate and the connecting plate through structural adhesive.
Compared with the prior art, the invention has the advantages that:
the problem that the welding is carried out with PCB to the pad of small interval is drawn forth through the mode of keysets on solving the chip, has solved multi-level bonding wire angle, problem that length is not enough, can not cause the gold thread too closely and short circuit, and the restriction on the gold thread length diminishes, and the outward appearance shape of gold thread is more controllable, and the degree of difficulty of bonding wire technology reduces in the reality.
Drawings
Fig. 1 is a schematic structural diagram of a connection structure of a small inter-pad-distance chip and a PCB according to an embodiment.
Fig. 2 is a schematic structural diagram of the step S2 of the method for processing the connection structure between the small pad pitch chip and the PCB.
Fig. 3 is a schematic structural diagram of the method for processing the connection structure between the small pad pitch chip and the PCB in step S3.
Fig. 4 is a schematic structural diagram of the method for processing the connection structure between the small pad pitch chip and the PCB in step S4.
Fig. 5 is a schematic structural diagram of the method for processing the connection structure between the small pad pitch chip and the PCB in step S5.
FIG. 6 is a schematic view of a single-layer connection structure of a second layer of connection plates.
Fig. 7 is a schematic structural diagram of the method for processing the connection structure between the small pad pitch chip and the PCB in step S6.
Fig. 8 is a schematic structural view of the connection structure processing method of the small pad pitch chip and the PCB in step S7.
FIG. 9 is a schematic view of a single-layer connection structure of a third layer of connection plates.
Fig. 10 is a schematic structural view of the connection structure processing method of the small pad pitch chip and the PCB in step S8.
Fig. 11 is a schematic structural diagram of the method for processing the connection structure between the small pad pitch chip and the PCB in step S9.
Fig. 12 is a schematic view of a single-layer connection structure of a fourth-layer connection plate.
Detailed Description
The present invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Referring to fig. 1, a connection structure of a small inter-pad-distance chip and a PCB according to an embodiment of the present invention includes a PCB substrate 1, a chip 2, and four layers of interposer 3. Four rows of lead-out bonding pads 4 are arranged on the PCB substrate 1, and the distance between the lead-out bonding pads 4 is 0.18mm. Chip 2 passes through the structure to be glued and fixes on PCB base plate 1, is equipped with multiseriate chip pad 5 on the chip 2, and the interval of chip pad 5 is 0.02mm. The four layers of the adapter plates 3 are sequentially overlapped from top to bottom from small to large and are fixed by structural adhesive, and finally, the four layers of the adapter plates are glued on the PCB substrate 1. Each layer of the interposer 3 is provided with a first pad 6 and a second pad 7 arranged in a column, and the first pad 6 and the second pad 7 are respectively located at two opposite edges of the interposer 3. The pitch of the first bonding pads 6 of the first layer of the interposer 3a is 0.04mm, the pitch of the second bonding pads 7 of the first layer of the interposer 3a is 0.15mm, the pitch of the first bonding pads 6 of the second layer of the interposer 3b is 0.05mm, the pitch of the second bonding pads 7 of the second layer of the interposer 3b is 0.09mm, the pitch of the first bonding pads 6 of the third layer of the interposer 3c is 0.07mm, the pitch of the second bonding pads 7 of the third layer of the interposer 3c is 0.09mm, the pitch of the first bonding pads 6 of the fourth layer of the interposer 3d is 0.09mm, and the pitch of the second bonding pads 7 of the fourth layer of the interposer 3d is 0.09mm. The first bonding pads 6 and the second bonding pads 7 on each layer of the interposer 3 are conducted through the printed circuit 8 on the interposer 3, and the first bonding pads 6 correspond to the second bonding pads 7 one by one. Chip bonding pads 5 on the chip 2 are respectively welded with first bonding pads 6 of a first layer of adapter plate 3a, a second layer of adapter plate 3b, a third layer of adapter plate 3c and a fourth layer of adapter plate 3d through gold wires 9, and second bonding pads 7 of the first layer of adapter plate 3a, the second layer of adapter plate 3b, the third layer of adapter plate 3c and the fourth layer of adapter plate 3d are respectively welded with four rows of lead-out bonding pads 4 on the PCB substrate 1 through gold wires 9.
The processing method of the connection structure of the small pad pitch chip and the PCB of the present embodiment is as follows:
s1, bonding chip 2' S the structure that passes through glues on PCB base plate 1, the curing condition: 85 ℃ for 2 hours; 120 ℃ for 1 hour;
s2, adhering the first layer of adapter plate 3a to the PCB substrate 1 by structural adhesive, wherein the left, right, upper and lower positions correspond to the positions of the bonding pads between the chip 2 and the PCB substrate 1, namely a first bonding pad 6 and a second bonding pad 7 on the first layer of adapter plate 3a are positioned between the chip bonding pad 5 and the lead-out bonding pad 4, the first bonding pad 6 is close to the chip bonding pad 5, and the second bonding pad 7 is close to the lead-out bonding pad 4, as shown in FIG. 2; and (3) curing conditions of the structural adhesive: 85 ℃ for 2 hours; 120 ℃ for 1 hour;
and S3, performing gold wire 9 welding on the chip bonding pad 5, the first bonding pad 6 on the first layer of adapter plate 3a and the second bonding pad 7 on the first layer of adapter plate 3a and the lead-out bonding pad 4, as shown in FIG. 3. And (3) welding wire conditions: 150-180 ℃, pressure: 25 g-45 g;
and S4, attaching the second layer of adapter plate 3b to the first layer of adapter plate 3a welded with gold wires 9, wherein the wires are welded on the two sides and the surface of the second layer of adapter plate 3b is provided with a metal circuit, so that insulating structural adhesive is used when attaching the second layer of adapter plate 3b without touching the gold wires 9 on the two sides, and curing is performed after the second layer of adapter plate is well adhered, as shown in FIG. 4. And (3) curing conditions of the structural adhesive: 85 ℃ for 2 hours; 120 ℃ for 1 hour;
and S5, performing gold wire 9 welding on the chip bonding pad 5, the first bonding pad 6 on the second-layer adapter plate 3b and the second bonding pad 7 on the second-layer adapter plate 3b and the lead-out bonding pad 4, as shown in FIGS. 5 and 6. And (3) welding wire conditions: 150-180 ℃, pressure: 25 g-45 g;
and S6, attaching the third layer of adapter plate 3c to the second layer of adapter plate 3b welded with the gold wires 9, wherein the wires are welded on the two sides and the surface of the third layer of adapter plate 3c is provided with a metal circuit, so that insulating structural adhesive is used when the third layer of adapter plate 3c is attached without touching the gold wires 9 on the two sides, and the third layer of adapter plate is cured after being bonded, as shown in FIG. 7. And (3) curing conditions of the structural adhesive: 85 ℃ for 2 hours; 120 ℃ for 1 hour;
and S7, performing gold wire 9 welding on the chip bonding pad 5 and the first bonding pad 6 on the third-layer adapter plate 3c and the second bonding pad 7 on the third-layer adapter plate 3c and the lead-out bonding pad 4, as shown in FIGS. 8 and 9. Welding wire conditions: 150-180 ℃, pressure: 25 g-45 g;
and S8, attaching the fourth layer of adapter plate 3d to the third layer of adapter plate 3c welded with the gold wires 9, wherein the wires are welded on the two sides and the surface of the fourth layer of adapter plate 3d is provided with a metal circuit, so that an insulating structural adhesive is used when the fourth layer of adapter plate 3d is attached without touching the gold wires 9 on the two sides, and the fourth layer of adapter plate is cured after being bonded, as shown in figure 10. And (3) structural adhesive curing conditions: 85 ℃ for 2 hours; 120 ℃ for 1 hour;
and S9, performing gold wire 9 welding on the chip bonding pad 5, the first bonding pad 6 on the fourth layer of adapter plate 3d and the second bonding pad 7 on the fourth layer of adapter plate 3d and the lead-out bonding pad 4, as shown in the figures 11 and 12. Welding wire conditions: 150-180 ℃, pressure: 25g to 45g.
In the embodiment, the conducting welding is realized by forming the circuit on the silicon substrate by photoetching between the chip and the PCB substrate 1 to form the adapter plate 3 and gradually releasing the distance between the bonding pads, the feasibility is improved by designing the adapter plate 3, and the problems of the length, the angle and the like of a bonding wire gold thread 9 are solved.
Claims (7)
1. The utility model provides a connection structure of little pad interval chip and PCB, its characterized in that, includes PCB base plate, a plurality of keysets and the chip of range upon range of setting, the chip is equipped with the chip pad, the PCB board is equipped with draws forth the pad, the keysets is fixed in on the PCB base plate and be located the chip with draw forth between the pad, every layer the connecting plate is equipped with a plurality of first pads and a plurality of second pads that become the row and arrange respectively, first pad with the second pad switches on through printed wiring one-to-one, the chip pad with between the first pad and the second pad with draw forth and connect through the gold thread between the pad, the interval of chip pad < the interval of first pad is not more than the interval of second pad < the interval of drawing forth the pad.
2. The small inter-pad-pitch chip-to-PCB connection structure of claim 1, wherein the first pad and the second pad are respectively disposed at opposite edges of a surface of the connection board, the connection board of an upper layer is located between the first pad and the second pad of a connection board of a lower layer, the first pad is close to the chip, and the second pad is close to the lead-out pad.
3. The small inter-pad-pitch chip-to-PCB connection structure of claim 1, wherein the chip pads and the lead-out pads are arranged in a plurality of rows, each row of the chip pads is connected to the first pad of one connection board, and each row of the lead-out pads is connected to the second pad of one connection board.
4. The small pad pitch chip to PCB connection structure of claim 1, wherein the pitch of the chip pads is not more than 25 microns, and the pitch of the lead-out pads is not less than 100 microns.
5. A method for processing a connecting structure of a small pad pitch chip and a PCB is characterized by comprising the following steps:
s1, fixing a chip on a PCB substrate, wherein the chip is provided with a plurality of chip bonding pads, and the PCB substrate is provided with a plurality of leading-out bonding pads;
s2, a layer of adapter plate is fixed between the chip and the lead-out bonding pad on the PCB substrate, and a plurality of first bonding pads and second bonding pads which are conducted through printed circuits in a one-to-one correspondence mode are arranged on the adapter plate;
s3, welding and conducting the chip bonding pad and the first bonding pad by using a gold wire, and welding and conducting the second bonding pad and the lead-out bonding pad by using a gold wire;
s4, fixing another layer of adapter plate on the lower layer;
s5, welding and conducting the chip bonding pad and a first bonding pad of the adapter plate on the top layer through a gold wire, and welding and conducting a second bonding pad of the adapter plate on the top layer and the lead-out bonding pad through the gold wire;
s6, repeating the steps S4 and S5 until all chip bonding pads and the lead-out bonding pads are welded
The distance between the chip bonding pads is smaller than the distance between the first bonding pads and smaller than the distance between the second bonding pads and smaller than the distance between the leading-out bonding pads.
6. The method as claimed in claim 5, wherein the interposer of another layer is fixed in step S4 such that the interposer of an upper layer is located between the first pad and the second pad of the interposer of a lower layer.
7. The method for processing the connection structure of the small inter-pad-distance chip and the PCB according to claim 5, wherein the chip and the PCB substrate, the connection board and the PCB substrate, and the connection board are fixed by structural adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210913549.4A CN115279020B (en) | 2022-08-01 | 2022-08-01 | Connection structure of chip with small pad spacing and PCB and processing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210913549.4A CN115279020B (en) | 2022-08-01 | 2022-08-01 | Connection structure of chip with small pad spacing and PCB and processing method thereof |
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| CN115279020A true CN115279020A (en) | 2022-11-01 |
| CN115279020B CN115279020B (en) | 2023-06-02 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202076262U (en) * | 2011-04-20 | 2011-12-14 | 坤远科技股份有限公司 | Stacked multi-chip packaging structure |
| CN106211570A (en) * | 2016-09-22 | 2016-12-07 | 京信通信技术(广州)有限公司 | Radio frequency PCB attachment structure and method of attachment |
| CN107340464A (en) * | 2016-04-29 | 2017-11-10 | 中华精测科技股份有限公司 | Stack type test interface plate and manufacturing method thereof |
| US20180063970A1 (en) * | 2016-08-30 | 2018-03-01 | Samsung Display Co., Ltd. | Display device |
| CN208622717U (en) * | 2018-07-27 | 2019-03-19 | 上海泽丰半导体科技有限公司 | A kind of chip change-over panel |
| CN110556363A (en) * | 2018-06-01 | 2019-12-10 | 三星电子株式会社 | Thin film type package and display device having the same |
| CN213071644U (en) * | 2020-09-03 | 2021-04-27 | 深圳市中深光电股份有限公司 | Adapter plate and adapter |
-
2022
- 2022-08-01 CN CN202210913549.4A patent/CN115279020B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202076262U (en) * | 2011-04-20 | 2011-12-14 | 坤远科技股份有限公司 | Stacked multi-chip packaging structure |
| CN107340464A (en) * | 2016-04-29 | 2017-11-10 | 中华精测科技股份有限公司 | Stack type test interface plate and manufacturing method thereof |
| US20180063970A1 (en) * | 2016-08-30 | 2018-03-01 | Samsung Display Co., Ltd. | Display device |
| CN106211570A (en) * | 2016-09-22 | 2016-12-07 | 京信通信技术(广州)有限公司 | Radio frequency PCB attachment structure and method of attachment |
| CN110556363A (en) * | 2018-06-01 | 2019-12-10 | 三星电子株式会社 | Thin film type package and display device having the same |
| CN208622717U (en) * | 2018-07-27 | 2019-03-19 | 上海泽丰半导体科技有限公司 | A kind of chip change-over panel |
| CN213071644U (en) * | 2020-09-03 | 2021-04-27 | 深圳市中深光电股份有限公司 | Adapter plate and adapter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115279020B (en) | 2023-06-02 |
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