CN115267327B - Harmonic wave measuring device and method for synchronous tracking - Google Patents
Harmonic wave measuring device and method for synchronous tracking Download PDFInfo
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Abstract
The invention belongs to the technical field of harmonic measurement, and particularly relates to a harmonic measurement device and method for synchronous tracking, wherein the harmonic measurement device comprises: the synchronous sampling tracking unit is internally provided with a second double-port RAM module, a clock module A, a clock module B, a data unloading module, a frequency tracking module, an ADC (analog-to-digital converter) calculation module, a frequency calculation module and an ADC controller, the clock module A and the clock module B divide the frequency of a clock by any multiple according to an input CNV (cyclic redundancy check) adjusting parameter K to obtain a target frequency clock, and the target frequency clock is input into the ADC controller to control the ADC sampling frequency; and the FFT calculation module performs Fourier transform on the read ADC sampling data and performs harmonic data processing. The invention has the advantages of high precision, easy calculation, low cost, easy expansion and high modularization degree.
Description
Technical Field
The invention belongs to the technical field of harmonic measurement, and particularly relates to a harmonic measurement device and method for synchronous tracking.
Background
In the measurement of an electric power system, harmonic measurement of alternating current voltage (or current) is an important measurement project, and particularly, for the industries of automobile electronics, photovoltaic and the like in the current positive and hot new energy fields, the harmonic measurement gradually becomes a product factory detection item in the national standard requirement, and higher requirements are provided for modular expansion and measurement accuracy in production measurement.
At present, the most applied harmonic measurement methods are two, one is a windowing interpolation method, and the other is a hardware phase-locked loop frequency multiplication sampling method.
The windowing interpolation method has the advantages that: the method has low requirements on hardware, can ensure enough calculation points through interpolation at a low sampling rate, and effectively prevents frequency leakage errors caused by barrier effect due to insufficient time points in harmonic measurement. The disadvantages of the windowing interpolation method are: although the error can be corrected through filtering algorithms such as a Hanning window and the like, due to analog interpolation, the interpolation phase has an error at last, the measurement precision is influenced, and the measurement precision is generally not high in the method and the risk of large error occurs under special frequency.
The hardware phase-locking method is to carry out frequency multiplication on fundamental waves through a hardware phase-locking circuit, and has the advantages that: the accuracy is higher, tracks the fundamental frequency at any time and carries out frequency multiplication sampling, and the response is fast. The disadvantages of the hardware phase locking method are: the method has the advantages that the requirements on the stability and accuracy of phase-locked loop frequency multiplication are high due to the restriction of hardware, if the harmonic measurement capability with the same fundamental wave frequency is achieved by a windowing interpolation method, the circuit is complex and high in cost, hardware needs to be expanded during each expansion, if multi-path asynchronous harmonic measurement is carried out, multi-path independent phase-locked loop circuits are needed, and hardware redundancy is serious. Secondly, as harmonic measurement is usually accompanied with other data measurement, the frequency multiplication of a hardware phase-locked loop directly generates sampling frequency, the sampling speed is controlled, the sampling rate is lower than normal sampling, and other numerical value precision is influenced, including an effective value Rms, a harmonic component Hrms and the like.
Therefore, how to obtain more accurate harmonic measurement, more standard modules and more convenient expansion is the problem to be solved by the invention.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a harmonic measurement method for synchronous tracking. The technical scheme adopted by the invention is as follows:
a harmonic measurement device for synchronous tracking, comprising: the system comprises a main control unit, a synchronous sampling tracking unit and an analog sampling unit, wherein the main control unit adopts an MCU (microprogrammed control unit), the synchronous sampling tracking unit adopts an FPGA (field programmable gate array), and the analog sampling unit is provided with a plurality of measurement cards; the main control unit is provided with a first double-port RAM module and an FFT (fast Fourier transform) calculation module, the synchronous sampling tracking unit is provided with a second double-port RAM module, a clock module A, a clock module B, a data dump module, a frequency tracking module, an ADC (analog-to-digital converter) calculation module, a frequency calculation module and an ADC (analog-to-digital converter) controller, and the frequency calculation module and the ADC controller are respectively in data interaction with the measurement card; the frequency calculation module reads signal zero crossing point information from the measuring card and calculates the current frequency; the ADC controller receives the clock signal after tracking processing, converts the clock signal into CNV to control the sampling speed of the ADC, and performs data transmission with the ADC through the SPI bus; the frequency tracking module synchronously tracks the frequency obtained by the frequency calculation module in real time, and controls the clock output of the clock module A and the clock module B by combining the conversion of the current harmonic frequency multiplication number; the clock module A and the clock module B divide the frequency of the clock by any multiple according to the input CNV adjusting parameter K to obtain a target frequency clock, and the target frequency clock is input into an ADC controller to control the ADC sampling frequency; the ADC controller transmits data to the ADC calculation module, the ADC calculation module simultaneously calculates a root mean square value and a peak value except for processing an original wave point, the ADC calculation module sends the data to the data dump module, the second double-port RAM module is connected with the MCU through the FSMC data bus for communication, the RAM area data reading is carried out through addressing, and ADC sampling data transmission is carried out; the first double-port RAM module reads data in the data unloading module through the second double-port RAM module, and the FFT calculation module performs Fourier transform on the read ADC sampling data and performs harmonic data processing.
A harmonic measurement method of synchronous tracking, which applies the harmonic measurement device of synchronous tracking, comprises the following steps:
(1) capturing zero crossing point information in an analog signal sampling unit, and calculating the frequency of the acquired signal by a synchronous sampling tracking unit through a frequency calculation module;
(2) calculating a target sampling frequency f in a synchronous sampling tracking unit n ，f n F is the frequency of the collected signal, and Ct is the sampling frequency in a single period;
(3) calculating the maximum sampling frequency f of FPGA in the synchronous sampling tracking unit nmax ，f nmax ＝f n ×P max ，P max Is not higher than the maximum integral multiple of the sampling capacity;
(4) calculating a CNV adjusting parameter K value, using the K value to control a clock, calculating the K value according to the measured frequency and the target sampling frequency, and K = f nmax ÷f 0 ，f 0 Equal to the maximum supported frequency of the clock module divided by the full value of the counter;
(5) switching the ADC conversion speed according to the K value, dividing the frequency of a clock module A receiving the K value to generate a target CNV and outputting the target CNV to an ADC controller, changing the sampling CNV by the ADC controller according to the signal, recalculating the K value by a frequency tracking module again in the sampling process, and transmitting the K value to a clock module B, switching the clock module B of the ADC controller when the sampling point number is reached in the period, using the clock module A and the clock module B in an interlaced manner, and quickly switching the ADC without phase delay when the sampling frequency is changed;
(6) according to the maximum sampling frequency f nmax Controlling CNV signal to carry out ADC conversion to obtain a whole-period array S (i), sf (i) = S (P) max Xi) of Sf (0) = S (0), sf (1) = S (3), sf (2) = S (6), sf (i) = S (P), respectively max Xi), … …, i refers to the nth number to obtain a new array Sf (i), i is more than or equal to 0 and less than or equal to Ct, and an original sampling point is obtained to meet the FFT operation condition;
(7) and (5) sending the Sf (i) into a main control unit, and performing FFT (fast Fourier transform) by using an FFT module to obtain harmonic data.
The invention has the beneficial effects that:
1. high precision and easy calculation: the data are guaranteed to be sampled based on integral multiples of fundamental wave frequency, FFT can be used for calculation, convenience and rapidness are achieved, accuracy is high, and measurement precision is guaranteed.
2. Low cost and easy expansion: the multipath harmonic measurement does not need to additionally increase hardware, the FPGA soft core is added, the cost and the space are saved, and the problem that the existing product is difficult to upgrade is solved.
3. The modularization degree is high, and the system architecture is clear, and scalability is strong, keeps high sampling rate, and measurement accuracy can not be influenced by the frequency reduction that the phase-locked loop brought.
Drawings
FIG. 1 is a schematic topology diagram of an embodiment of the present invention;
fig. 2 is a flow chart of measurement steps of an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Fig. 1 is a schematic topology diagram of an embodiment of the present invention, and arrows in fig. 1 indicate data transmission. The invention uses the analog synchronous tracking sampling technology, flexibly controls the sampling frequency, achieves the aim of realizing rapid harmonic measurement while ensuring the precision, and totally divides the system into three parts:
a first module: and the main control unit MCU. The main control unit MCU is provided with a first double-port RAM module (M1) and an FFT calculation module (M2), the first double-port RAM module (M1) and the FFT calculation module (M2) are both software function modules, and the first double-port RAM module (M1) carries out data interaction with a second double-port RAM module (F1) in the second module through an FSMC bus.
The FFT calculation module (M2) is mainly used for data processing, and carries out Fourier transform on ADC sampling data acquired by the M1 and carries out harmonic data processing.
Here the calculation is done using the arm official library function:
(1) The fourier transform fourier transforms the input data using the function arm _ cfft _ f32 (& arm _ cfft _ f32_ len1024, fft _ inputbuf,0,1). The input parameters of the method have the following meanings:
arm _ cfft _ f32_ len1024 is a fourier transform structure, and 1024 is the number of points to be calculated. When calculating other points, for example, 32-point FFT, arm _ cfft _ sR _ f32_ len32 can be used. fft _ inputbuf is the first address of data to be processed by fourier transform, the third parameter 0 is positive transform, 1 is inverse transform, and the fourth parameter defaults to 1.
The result after fourier transformation is still complex, and the ratio of imaginary part to real part can calculate the phase of the frequency point, which is not considered here, and directly takes the modulus of the complex number.
(2) And performing Fourier transform on the Arm _ cfft _ radix4_ f32 to obtain a real part and an imaginary part of the transformed data.
(3) arm _ cmplx _ mag _ f32 (FFT _ inputburst, FFT _ outputburst, FFT _ LENGTH) is used to calculate the modulus, perform the modulus operation, and then find the parameters such as amplitude and phase.
Wherein, ft _ inputburst source data is in a complex form, FFT _ outputburst takes the data after modulus, and in a real form, and FFT _ LENGTH is the number of modulus points.
The internal calculation formula is:
and a second module: a synchronous sampling tracking unit (FPGA). Using FPGA as hardware support, set up software function module therein, include: a second double-port RAM module (F1), a clock module A [100M ] (F2), a clock module B [100M ] (F3), a data dump module (F4), a frequency tracking module (F5), an ADC calculating module (F6), a frequency calculating module (F7) and an ADC controller (F8).
The frequency calculation module (F7) and the ADC controller (F8) are respectively in data interaction with the plurality of measuring cards, and the frequency calculation module (F7) reads signal zero-crossing point information from the measuring cards and calculates the current frequency; and the ADC controller (F8) receives the clock signal after the tracking processing, converts the clock signal into a CNV (Convst ADC start conversion signal) to control the sampling speed of the ADC, and transmits data with the ADC through the SPI bus.
Frequency tracking module (F5): and the real-time synchronous tracking frequency calculation module (F7) converts the frequency in combination with the current harmonic frequency multiplication number and controls the clock output of the clock modules A and B (F2 and F3).
The second double-port RAM module (F1) is connected with the MCU through the FSMC data bus for communication, data reading of the RAM area is carried out through addressing, and ADC sampling data transmission is mainly carried out.
The clock module A [100M ] (F2) and the clock module B [100M ] (F3) divide the frequency of the clock by any multiple according to the input CNV adjusting parameter K to obtain a target frequency clock, and the target frequency clock is input into an ADC controller (F8) so as to control the ADC sampling frequency. The two groups of clock modules F2 and F3 are alternately used, when one group is in use, the other group configures and initializes a new clock, and when the frequency is changed, the other group is quickly switched and outputs a control signal, so that the delay caused by clock initialization is avoided, and 100M is the clock which can support the frequency of 100MHz at the maximum.
The ADC controller (F8) transmits data to the ADC calculation module (F6), and the ADC calculation module (F6) needs to calculate related data such as a root mean square value, a peak value and the like besides processing an original wave point. And the ADC calculation module (F6) sends the data to the data unloading module (F4), the data unloading module (F4) is an RAM buffer area, and the data of the ADC calculation module (F6) is unloaded and waits for the MCU to read.
And a third module: and the analog sampling unit comprises n measuring cards.
The measuring card is an existing product, mainly comprises a sampling resistor, an operational amplifier and an ADC circuit, and mainly has the functions of sampling an accessed signal, wherein read-back data has two parts, one part reads the data through an ADC controller (F8) SPI bus in an FPGA, and the read-back data is AD words with a fixed number of sampling points. The other part is read back by a frequency calculation module (F7), a zero-crossing signal is read back, and frequency value calculation is carried out through the period number of the zero-crossing and the zero-crossing timing.
Because the FFT (Fast Fourier Transform) is used for harmonic calculation, the sampling number needs to be ensured to be integral multiple of the harmonic period, the measured frequency needs to be accurately tracked, and the conversion of an analog part ADC needs to be controlled in time, so that all modules in the invention need to be closely matched.
Fig. 2 is a flowchart of the measurement steps according to the embodiment of the present invention. A harmonic measurement method of synchronous tracking, which applies the harmonic measurement device of synchronous tracking, comprises the following steps:
(1) and capturing zero-crossing point information in the analog signal sampling unit, and calculating the frequency of the acquired signal by the synchronous sampling tracking unit (F5) through a frequency calculating module (F7).
(2) Calculating a target sampling frequency F in a synchronous sampling tracking unit (F5) n 。
For example: the frequency f of the collected signal is a signal of 50Hz, 100 harmonics are calculated, ct times of sampling are carried out in a single period, 1024 times of Ct are selected to ensure the accuracy of harmonic data, and therefore the target sampling frequency is as follows:
f n ＝f×Ct＝50×1024＝51.2kHz。
(3) the maximum sampling frequency of the FPGA is calculated in a synchronous sampling tracking unit (F5).
Example (c): if the maximum sampling capacity of the analog system is 200kHz, harmonic data precision is lost if the 51.2kHz sampling is directly used, and the sampling frequency can be increased to be f which is not higher than the sampling capacity n Maximum integral multiple frequency, so when f n Below 200kHz, f n Frequency f multiplied by the maximum integer nmax Comprises the following steps:
f nmax ＝f n ×P max (maximum integer multiple) =51.2 × 3=153.6khz.
Better than the frequency provided by pure phase lock.
(4) And calculating a value K of the CNV adjusting parameter, wherein the value K is used for controlling a clock, and the value K is calculated according to the measured frequency and the target sampling frequency.
Clock signals are sent to an ADC controller (F8) through the control clock modules (F2) and (F3), ADC conversion is guaranteed to be conducted fast, real-time performance and concurrency of the FPGA are well utilized, and signal sampling synchronization is guaranteed. The register and the on-chip memory (BRAM) in the FPGA belong to respective control logics, unnecessary arbitration and cache are not needed, the FPGA processes information in a single clock cycle, all operations are basically finished instantly, the real-time performance and the synchronism of the FPGA are guaranteed by combining the two points, and therefore the sampling and data processing synchronism can be guaranteed through the FPGA control.
The invention uses a 100M clock module and a 32-bit counter for timing, and the full value is 2 32 =4294967296, i.e. the counting frequency is:
f 0 ＝100000000(100MHz)÷2 32 =0.02328306Hz, f to be calculated nmax Bringing in the available value of K, coefficient K = f nmax ÷f 0 ＝153600÷0.02328306＝6597071。
(5) And switching the ADC conversion speed according to the K value.
Firstly, in the sampling process, K value K = f is calculated nmax ÷f 0 Wherein f0 is stable and constant, f nmax The frequency tracking module (F5) recalculates the K value again in the sampling process and sends the K value to the clock module B (F3), and when the period reaches the sampling point number, the clock module B (F3) of the ADC controller (F8) is switched. The CNV sampling means that the Convst ADC starts to convert a signal, is a pulse signal, is connected with a CONVST pin of the ADC and controlsAnd the ADC conversion speed is realized, and in the sampling process of using the clock module B (F3), the frequency tracking module (F5) recalculates the K value again and waits for clock switching, so that the AB clock staggered use mode ensures that the ADC can be switched quickly without phase delay when the sampling frequency is changed.
(6) Obtaining an original sampling point:
according to the maximum sampling frequency f nmax Controlling CNV signal to make ADC conversion to obtain whole period array S (i), at this time, the number of points obtained in single period is P max X Ct =3 x 1024=3072, and Sf [0 ] is taken respectively]＝S[0]，Sf[1]＝S[3]，Sf[2]＝S[6]，Sf[i]＝S[P max ×i]… … (i means the nth number) to obtain a new array Sf [ i [ -i [ ])](i is more than or equal to 0 and less than or equal to 1024), and the array is sampled for 1024 times at 50Hz in the whole period, so that the FFT operation condition is met. In the embodiment of the invention, the sampling signal is subjected to FFT conversion only by using a 51.2kHz sampling rate single cycle to carry out 1024 times of sampling, but in order to ensure the calculation accuracy of the root mean square equivalent value, the sampling frequency is increased, so 153.6k is used for sampling, namely 3 times of the sampling frequency, 3072 sampling points are finally obtained, and therefore, 1024 sampling points need to be uniformly screened out from 3072 sampling points for FFT calculation before the FFT calculation is carried out.
(7) Harmonic data calculation:
and finally, sending the Sf (i) into the MCU to perform FFT fast Fourier transform by using an FFT module (M2) to obtain harmonic data.
Claims (2)
1. A harmonic measurement device for synchronous tracking, comprising: the system comprises a main control unit, a synchronous sampling tracking unit and an analog sampling unit, wherein the main control unit adopts an MCU (microprogrammed control unit), the synchronous sampling tracking unit adopts an FPGA (field programmable gate array), and the analog sampling unit is provided with a plurality of measurement cards; the synchronous sampling tracking unit is provided with a second double-port RAM module, a clock module A, a clock module B, a data unloading module, a frequency tracking module, an ADC (analog-to-digital converter) computing module, a frequency computing module and an ADC controller, wherein the frequency computing module and the ADC controller are respectively in data interaction with the measuring card; the frequency calculation module reads signal zero crossing point information from the measuring card and calculates the current frequency; the ADC controller receives the clock signal after tracking processing, converts the clock signal into CNV to control the conversion speed of the ADC, and performs data transmission with the ADC through the SPI bus; the frequency tracking module synchronously tracks the frequency obtained by the frequency calculation module in real time, and controls the clock output of the clock module A and the clock module B by combining the conversion of the current harmonic frequency multiplication number; the clock module A and the clock module B are alternately used, when one group is in use, the other group configures and initializes a new clock, when the frequency is changed, the new clock is quickly switched and outputs a control signal, the clock module A and the clock module B divide the frequency of the clock by any multiple according to an input CNV adjusting parameter K to obtain a target frequency clock, and the target frequency clock is input into an ADC controller to control the ADC conversion frequency; the ADC controller transmits data to the ADC calculation module, the ADC calculation module simultaneously calculates a root mean square value and a peak value except for processing an original wave point, the ADC calculation module sends the data to the data dump module, the second double-port RAM module is connected with the MCU through the FSMC data bus for communication, the RAM area data reading is carried out through addressing, and ADC sampling data transmission is carried out; the first dual-port RAM module reads data in the data unloading module through the second dual-port RAM module, and the FFT calculation module performs Fourier transform on the read ADC sampling data and performs harmonic data processing.
2. A harmonic measurement method of synchronous tracking, characterized by applying a harmonic measurement apparatus of synchronous tracking as claimed in claim 1, comprising the steps of:
(1) capturing zero crossing point information in an analog signal sampling unit, and calculating the frequency of the acquired signal by a synchronous sampling tracking unit through a frequency calculation module;
(2) calculating a target sampling frequency f in a synchronous sampling tracking unit n ，f n F is the frequency of the collected signal, and Ct is the sampling frequency in a single period;
(3) calculating the maximum sampling frequency f of FPGA in the synchronous sampling tracking unit nmax ，f nmax ＝f n ×P max ，P max Is not higher than the maximum integral multiple of the sampling capacity;
(4) calculating a CNV adjusting parameter K value, using the K value to control a clock, calculating the K value according to the measured frequency and the target sampling frequency, and K = f nmax ÷f 0 ，f 0 Equal to the maximum supported frequency of the clock module divided by the full value of the counter;
(5) switching the ADC conversion speed according to the K value, receiving the clock module A frequency division of the K value, generating a target CNV and outputting the target CNV to an ADC controller, changing the sampling CNV by the ADC controller according to the signal, recalculating the K value by a frequency tracking module again in the sampling process, and sending the K value to a clock module B, switching the clock module B of the ADC controller when the period reaches the number of sampling points, using the clock module A and the clock module B in an interlaced manner, and quickly switching the ADC without phase delay when the sampling frequency changes;
(6) according to the maximum sampling frequency f nmax Controlling the CNV signal to perform ADC conversion to obtain a full-period array S (i), sf (i) = S (P) max Xi) of Sf (0) = S (0), sf (1) = S (3), sf (2) = S (6), sf (i) = S (P), respectively max Xi), … …, i refers to the nth number, a new array Sf (i) is obtained, i is more than or equal to 0 and less than or equal to Ct, an original sampling point is obtained, and FFT operation conditions are met;
(7) and (5) sending the Sf (i) into a main control unit, and performing FFT fast Fourier transform by using an FFT module to obtain harmonic data.
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