CN115241198A - Memory device based on molybdenum disulfide/germanium diselenide heterojunction and preparation method thereof - Google Patents
Memory device based on molybdenum disulfide/germanium diselenide heterojunction and preparation method thereof Download PDFInfo
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- WYDSCDJEAVCHQJ-UHFFFAOYSA-N bis(selanylidene)germane Chemical compound [Se]=[Ge]=[Se] WYDSCDJEAVCHQJ-UHFFFAOYSA-N 0.000 title claims abstract description 14
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 title claims abstract description 14
- 229910052982 molybdenum disulfide Inorganic materials 0.000 title claims abstract description 14
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 229910005866 GeSe Inorganic materials 0.000 claims abstract description 51
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000010931 gold Substances 0.000 claims abstract description 22
- 229910052737 gold Inorganic materials 0.000 claims abstract description 22
- 230000005669 field effect Effects 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 11
- 238000012546 transfer Methods 0.000 claims description 8
- 239000004205 dimethyl polysiloxane Substances 0.000 claims description 7
- 235000013870 dimethyl polysiloxane Nutrition 0.000 claims description 7
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 claims description 7
- 238000004987 plasma desorption mass spectroscopy Methods 0.000 claims description 7
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 5
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
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- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- BWGNESOTFCXPMA-UHFFFAOYSA-N Dihydrogen disulfide Chemical compound SS BWGNESOTFCXPMA-UHFFFAOYSA-N 0.000 claims 1
- XIMIGUBYDJDCKI-UHFFFAOYSA-N diselenium Chemical compound [Se]=[Se] XIMIGUBYDJDCKI-UHFFFAOYSA-N 0.000 claims 1
- 230000015654 memory Effects 0.000 abstract description 30
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- 230000000903 blocking effect Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 2
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- 238000012512 characterization method Methods 0.000 description 2
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- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
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- -1 graphite alkyne Chemical class 0.000 description 1
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- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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Abstract
The invention discloses a memory device based on molybdenum disulfide/germanium diselenide heterojunction and a preparation method thereof 2 /GeSe 2 The metal-organic field effect transistor comprises a heterojunction channel, a gold source electrode and a gold drain electrode, wherein a grid insulating layer is arranged on the grid electrode, and MoS is arranged on the grid insulating layer 2 /GeSe 2 Heterojunction channel of said MoS 2 /GeSe 2 And a gold source electrode and a gold drain electrode are arranged on the heterojunction channel. Compared with a floating gate type memory, the memory device based on the molybdenum disulfide/germanium diselenide heterojunction is simpler in structure.
Description
Technical Field
The invention relates to the field of memory structures of electrical devices, in particular to a memory device based on a molybdenum disulfide/germanium diselenide heterojunction and a preparation method thereof.
Background
Since the discovery of graphene, two-dimensional materials have been extensively studied in the scientific research community and the industrial community. Due to the characteristic of atomic-level thickness of the two-dimensional material, the electronic device based on the two-dimensional material is expected to break through the miniaturization difficulty of the existing block material device. In addition, the good mechanical strength and light transmission of the two-dimensional material make the material have good potential in the directions of flexible devices and wearable equipment. Therefore, the construction of various electronic devices with simple structure and excellent performance using two-dimensional materials has become an important research direction in recent years, in which a memory structure is one of the important electronic devices.
Van der waals heterojunctions formed by vertical stacking of different two-dimensional materials provide a broad platform for the study of two-dimensional material memories. Two-dimensional materials cover a very broad band gap range of metals, semi-metals, semiconductors, and insulators, thus offering rich possibilities for the design of van der waals heterojunctions. Taking a typical floating gate memory as an example, the structure of the memory is composed of a channel, a tunneling layer, a floating gate, a blocking layer, a control gate, and the like. The channel is typically a semiconductor material, the tunneling layer is an insulating material, the floating gate is a metallic material for storing charge, and the blocking layer is also an insulating material. Under the signal action of the control gate, charges enter the floating gate through tunneling and are stored in the floating gate, so that the storage function is realized.
For example, chinese patent publication No. CN112289864A discloses a double-ended photo memory, and a preparation method and an application thereof, where the double-ended photo memory includes a conductive channel, a blocking layer, a tunneling layer, and a top photosensitive floating gate, which are sequentially disposed from bottom to top, and the top photosensitive floating gate is graphite alkyne. The memory disclosed by the invention takes the graphdine as the top photosensitive floating gate, the graphdine has a natural band gap, strong light absorption capability and a high-density state, and generates a large number of electron hole pairs under illumination, so that more charges can be stored, and the degradation of a gate coupling ratio and the interference among units can be inhibited, thereby improving the data storage capability of the memory and reducing the working voltage.
Although the floating gate type memory based on the two-dimensional material has been widely researched and shows good performance, the structure thereof is complicated, and the fabrication of the multi-layer vertical heterojunction is more and more difficult as the number of layers increases. Therefore, the exploration of a novel two-dimensional storage device with a simpler structure has important significance for the application of two-dimensional materials.
Disclosure of Invention
The invention provides a memory device based on molybdenum disulfide/germanium diselenide heterojunction, which has a simpler structure compared with a floating gate type memory.
The technical scheme of the invention is as follows:
a memory device based on molybdenum disulfide/germanium diselenide heterojunction comprises a gate electrode, a gate insulating layer, and a MoS 2 /GeSe 2 The heterojunction field effect transistor comprises a heterojunction channel, a gold source electrode and a gold drain electrode, wherein a gate insulating layer is arranged on the gate electrode, and MoS is arranged on the gate insulating layer 2 /GeSe 2 Heterojunction channel of said MoS 2 /GeSe 2 And a gold source electrode and a gold drain electrode are arranged on the heterojunction channel.
The invention realizes the storage function based on MoS 2 /GeSe 2 The basic principle of charge transfer and confinement caused by the gate voltage between vertical heterojunctions. When a forward back voltage is applied to carry out a writing operation, electrons in the channel are driven by MoS under the action of an electric field 2 Transfer to GeSe 2 Performing the following steps; when applying negative grid voltage to carry out erasing operation, the holes are made of MoS under the action of electric field 2 Channel transfer to GeSe 2 In (1). Due to binding to GeSe 2 Electrons or holes in the layer generate a large hysteresis phenomenon in the transfer characteristic curve of the device, so that the device presents two different resistance states after the grid voltage is removed, and conditions are provided for application of the memory.
Preferably, the gate electrode is made of a P-type heavily doped silicon wafer.
The gate electrode is the first layer of the memory, is a P-type heavily doped silicon wafer, can be used as a substrate of the whole device and can also be used as the gate electrode, and is compatible with a large-scale integrated circuit.
Preferably, the material of the gate insulating layer is HfO 2 。
HfO 2 The insulating layer is the second layer of the memory, hfO 2 The insulating layer is deposited on the first gate electrode by magnetron sputtering and serves as GeSe 2 And a barrier layer between the gate electrode and the gate electrode.
Further preferably, the thickness of the gate insulation layer is 15-25nm; most preferably 20nm.
MoS 2 /GeSe 2 The heterojunction forms a channel layer, which is the third layer of the memory, moS 2 /GeSe 2 The heterojunction is prepared by a PDMS assisted mechanical stripping method and a dry transfer process, and the channel layer is used for providing channel carriers and obtaining storage information through grid electric field regulation.
Preferably, said MoS 2 /GeSe 2 The heterojunction channel comprises GeSe 2 Layer and MoS 2 A layer.
GeSe 2 A layer disposed on the gate insulating layer, moS 2 Layer arranged on GeSe 2 On top of the layer.
Further preferably, the GeSe 2 The layer thickness is 10-15nm; the MoS 2 The thickness of the layer is 3-7nm.
The gold source electrode and the gold drain electrode are the fifth layer of the memory and are prepared by a photoetching process and electron beam evaporation.
The invention also provides a preparation method of the memory device based on the molybdenum disulfide/germanium diselenide heterojunction, which comprises the following steps:
(1) Removing the oxide layer on the surface of the gate electrode;
(2) Depositing a gate insulating layer on the gate electrode by magnetron sputtering;
(3) GeSe from bulk using PDMS assisted mechanical lift-off 2 In-situ stripping to obtain GeSe 2 A layer and transferred onto the gate insulating layer;
(4) MoS from bulk using PDMS assisted mechanical stripping 2 Middle stripping to obtain MoS 2 Layer and transfer to GeSe 2 Forming a vertical van der waals heterojunction on the layer;
(5) Preparing a suitable source/drain electrode pattern by a photolithography process; and preparing a gold source electrode and a gold drain electrode by electron beam evaporation to obtain the memory device based on the molybdenum disulfide/germanium diselenide heterojunction.
Compared with the prior art, the invention has the following beneficial effects:
the invention designs MoS 2 /GeSe 2 The vertical heterogeneous structure is firm, and the novel memory device with a simple structure is provided.The simple device structure is beneficial to simplifying the preparation flow and saving the production cost. In addition, with large size MoS 2 With the continuous development of thin film synthesis technology, the memory device based on the invention is expected to realize large-scale application later.
Drawings
Fig. 1 is a schematic structural diagram of a novel memory device and a characterization of a typical device according to an embodiment of the present invention, in which: (a) a schematic view of the device structure, (b) a photo of the device optical microscope, and (c) GeSe 2 And (d) MoS 2 Atomic force microscope images of (a).
FIG. 2 is a performance characterization of the novel memory device of an embodiment of the present invention, wherein: the method comprises the steps of (a) testing a memory window of a device, (b) testing the memory window of the device along with the change of a grid voltage, (c) testing the time stability of the device, and (d) testing the cycle stability of the device.
Fig. 3 shows two comparative structures corresponding to the memory device of the present invention and experimental results thereof, wherein: (a) First comparison structure MoS of memory 2 /hBN/HfO 2 Schematic view of a device of (1), geSe 2 Substituted by hBN; (b) Memory second contrast structure MoS 2 /GeSe 2 Device schematic of/hBN HfO 2 Substituted by hBN; (c) A first comparison structure and (d) a second comparison structure.
Detailed Description
Example 1
The embodiment designs and manufactures a product based on MoS 2 /GeSe 2 A novel memory structure of heterojunction. As shown in fig. 1 (a), the device includes: si gate electrode, hfO 2 Insulating layer, moS 2 /GeSe 2 A heterojunction channel layer, a gold source electrode and a gold drain electrode.
FIG. 1 (b) is an optical microscope photograph of the device, and FIGS. 1 (c) and (d) are GeSe 2 And MoS 2 The thickness of the two films was 14nm and 5nm, respectively.
The preparation method of the novel memory structure comprises the following steps:
step 1, selecting a heavily doped P-type silicon wafer as a substrate, respectively carrying out ultrasonic cleaning for 5 minutes by using acetone, alcohol and deionized water, and then treating the substrate by using a 5% HF solution to remove an oxide layer on the surface.
Step 3, geSe is separated from the block by PDMS assisted mechanical stripping method 2 Middle stripping to obtain 14nm GeSe 2 And transferred to HfO 2 On a substrate.
Step 4, using PDMS assisted mechanical stripping method from the MoS bulk 2 Middle stripping to obtain 5nm MoS 2 And transferred to GeSe by means of fixed-point transfer 2 Vertical van der waals heterojunctions are formed in the layers.
And 5, preparing a proper source/drain electrode pattern through a photoetching process.
Step 6, preparing a gold source electrode and a gold drain electrode by electron beam evaporation to obtain the product based on MoS 2 /GeSe 2 A memory device of heterojunction.
MoS-based prepared in this example 2 /GeSe 2 The threshold voltage of the novel heterojunction memory device is obviously shifted in different scanning directions, and a huge hysteresis phenomenon is generated. As shown in FIG. 2 (a), at a scan range of +/-10V, the scan is in the forward direction (V) g Threshold voltage and reverse scan (V) when changing from-10V to + 10V) g A difference between threshold voltages when changing from-10V to + 10V) reaches 10V. According to (b) in fig. 2, the size of the memory window also changes significantly with the range of the gate voltage, indicating that the memory capacity of the device has a strong dependence on the back voltage.
The measurement result of (c) in fig. 2 shows that the gate voltage is 2 × 10 at the off state 3 After s, the erased state does not change significantly, and the current in the programmed state gradually stabilizes although it changes by an order of magnitude. The current of the erase state and the programming state is 2 x 10 3 After s, the temperature also remains over 10 2 The ratio of (a) to (b). Indicating that the memory has better temporal stability. The measurement results of (d) in FIG. 2 show that at pass 10 3 After the write/erase cycle, neither the programmed nor erased current occurs significantlyAnd the current ratio of the two states is still maintained at 10 2 The above shows good cycling stability of the memory.
To explore the source of hysteresis in the structure, we designed and prepared MoS as shown in fig. 3 (a), (b) 2 /hBN/HfO 2 And MoS 2 /GeSe 2 Control Structure of/hBN. As shown in FIG. 3 (c), in the case of using hBN instead of GeSe 2 Then, the curves of the forward scan and the reverse scan are highly overlapped, the hysteresis disappears, and the storage capacity is lost. Indicating GeSe 2 Plays an important role in the mechanism of hysteresis generation. As shown in FIG. 3 (d), hBN is used in place of HfO 2 Later, the MoS appears under a +/-15V scanning range 2 /GeSe 2 /HfO 2 The memory device is similar to a huge hysteresis phenomenon, and the size of a hysteresis window reaches 15V, indicating that MoS 2 /GeSe 2 /HfO 2 Hysteresis in the structure mainly results from MoS 2 /GeSe 2 A vertical heterojunction.
In summary, the invention provides a method based on MoS 2 /GeSe 2 A vertical heterojunction memory device that exhibits a large memory window of 10V over a gate voltage range of +/-10V. The device is 2 multiplied by 10 through the test of time stability and cycle stability 3 s and 10 3 After the secondary circulation, the product still maintains more than 10 2 The write/erase ratio of (a) shows good memory performance. In addition, by MoS 2 /hBN/HfO 2 And MoS 2 /GeSe 2 Experimental results of two comparison structures of/hBN prove that the core structure of the memory is MoS 2 /GeSe 2 A vertical heterojunction. The heterostructure has great potential in a novel memory device, and provides new ideas and help for the design and exploration of other novel memory structures.
The above-mentioned embodiments are intended to illustrate the technical solutions and advantages of the present invention, and it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the present invention, and any modifications, additions, equivalents, etc. made within the scope of the principles of the present invention should be included in the scope of the present invention.
Claims (8)
1. A memory device based on molybdenum disulfide/germanium diselenide heterojunction is characterized by comprising a gate electrode, a gate insulating layer and MoS 2 /GeSe 2 The heterojunction field effect transistor comprises a heterojunction channel, a gold source electrode and a gold drain electrode, wherein a gate insulating layer is arranged on the gate electrode, and MoS is arranged on the gate insulating layer 2 /GeSe 2 Heterojunction channel of said MoS 2 /GeSe 2 And a gold source electrode and a gold drain electrode are arranged on the heterojunction channel.
2. The memory device according to claim 1, wherein the gate electrode is made of heavily P-doped silicon.
3. The memory device as claimed in claim 1, wherein the gate insulating layer is made of HfO 2 。
4. A memory device according to claim 1 or 3, wherein the thickness of the gate insulating layer is 15-25nm.
5. The memory device according to claim 1, wherein the MoS is based on a mo disulfide/ge diselenide heterojunction 2 /GeSe 2 The heterojunction channel comprises GeSe 2 Layer and MoS 2 And (3) a layer.
6. The memory device based on the molybdenum disulfide/germanium diselenide heterojunction as claimed in claim 5, characterized in that GeSe is 2 A layer disposed on the gate insulating layer, moS 2 The layer is arranged on GeSe 2 On the layer.
7. The memory device based on the molybdenum disulfide/germanium diselenide heterojunction as claimed in claim 5, characterized in that the GeSe 2 Layer thicknessThe degree is 10-15nm; the MoS 2 The thickness of the layer is 3-7nm.
8. A method for fabricating a memory device based on a molybdenum disulfide/germanium diselenide heterojunction as claimed in any one of claims 1 to 7, comprising the steps of:
(1) Removing the oxide layer on the surface of the gate electrode;
(2) Depositing a gate insulating layer on the gate electrode by magnetron sputtering;
(3) GeSe from bulk using PDMS assisted mechanical lift-off 2 In-situ stripping to obtain GeSe 2 A layer and transferred onto the gate insulating layer;
(4) MoS from bulk using PDMS assisted mechanical stripping 2 Middle peeling to obtain MoS 2 Layer and transfer to GeSe 2 Forming a vertical van der waals heterojunction on the layer;
(5) Preparing a suitable source/drain electrode pattern by a photolithography process; and preparing a gold source electrode and a gold drain electrode by electron beam evaporation to obtain the memory device based on the molybdenum disulfide/germanium diselenide heterojunction.
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