CN115394858A - Floating gate type two-dimensional heterojunction memristor and preparation method thereof - Google Patents
Floating gate type two-dimensional heterojunction memristor and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a floating gate type two-dimensional heterojunction memristor and a preparation method thereof, wherein the memristor sequentially comprises an Ag electrode layer and SiO from bottom to top 2 Substrate layer of/Si, moS 2 Carrier transport layer, moS 2 Au electrodes are disposed at opposite ends of the upper surface of the carrier transport layer, and h-BN insulating dielectric layers are formed corresponding to the Au electrodes and the MoS 2 A groove on the upper surface formed by the carrier transport layer, an AuNPs charge trapping layer, an h-BN insulating dielectric layer and MoS 2 The carrier transmission layer forms a two-dimensional heterojunction MoS with impedance storage characteristics 2 h-BN/AuNPs. Compared with the traditional memristor based on the bulk material, the memristor is constructed by the zero-dimensional and two-dimensional nano materials, and has unique advantages in the aspects of miniaturization and flexibility. In view of the fact that the device exhibits excellent information storage and erasure performance as well as good stability and reusability, moS 2 the/h-BN/AuNPs floating gate type memristor has good development prospect and practical value.
Description
Technical Field
The invention belongs to the field of memories, and particularly relates to a floating gate type two-dimensional heterojunction type memristor and a preparation method thereof.
Technical Field
Memories based on conventional silicon and germanium semiconductors play an important role in the contemporary field of electronic information and computers. Over the past few decades, short channel effects have become more pronounced as transistor channel dimensions have continued to shrink, making it increasingly difficult to further improve memory performance by shrinking transistor dimensions. Therefore, moore's law will be difficult to maintain under von neumann computing architecture. Therefore, it is necessary to develop new material systems or to propose new device structures to meet the requirements of human society for high-performance information processing and information storage.
A memristor-based neurosynaptic device (synaptic device) is the basis for constructing a neuromorphic network, and neuromorphic calculation has the characteristics of high operation speed, low power consumption and the like, and is expected to break through the bottleneck of a Von Neumann calculation architecture. Therefore, a memristor (memristor) is expected to provide a new idea for solving the problems faced by the conventional semiconductor device. Traditional Transition Metal Oxide (TMO) -based memristors such as TiO x ，MoO x The switching mechanism of the like is mainly the formation and annihilation of an internal conductive channel. The switching mechanism will cause irreversible damage to the conducting channel, resulting in performance degradation of the device after multiple switching, thereby making the device less reusable and less stable. In addition, since the traditional bulk material is poor in mechanical flexibility, the memristor based on the bulk material is difficult to perform size reduction and heterogeneous integration. Compared with the traditional TMO memristor, the layered two-dimensional materials with atomic-scale thickness such as TMDCs, h-BN and the like are expected to realize richer and more stable device performance due to unique electrical properties, good mechanical flexibility and easy heterogeneous integration.
Therefore, in order to solve the problems of poor stability, poor reusability, difficulty in miniaturization and the like of the traditional memristor, the invention designs the memristor completely based on the two-dimensional material, and compared with the traditional TMO memristor, the memristor has the advantages of excellent stability, stronger robustness and excellent impedance switching characteristics.
Reference:
[1]Hou X,Zhang H,Liu C,et al.Charge-Trap Memory Based on Hybrid 0D Quantum Dot-2D WSe 2 Structure[J].Small,2018,14(20):e1800319
disclosure of Invention
The main innovation point of the invention is to construct a novel floating gate type heterojunction memristor (completely constructed by low-dimensional materials and having unique advantages in the aspects of miniaturization and flexibility), and the performance characteristics are as follows:
the invention discloses a floating gate type two-dimensional heterojunction memristor which sequentially comprises an Ag electrode layer and SiO from bottom to top 2 Substrate layer of/Si, moS 2 Carrier transport layer, moS 2 Au electrodes, au electrodes and MoS are arranged at two opposite ends of the upper surface of the carrier transmission layer 2 The upper surface formed by the carrier transmission layer is covered with an h-BN insulating dielectric layer which forms a structure corresponding to the Au electrode and the MoS 2 A groove on the upper surface formed by the carrier transport layer, an Au nanoparticle (AuNPs) charge trapping layer, an AuNPs charge trapping layer, an h-BN insulating dielectric layer and MoS in the groove and on the upper surface of the h-BN insulating dielectric layer 2 The carrier transmission layer forms a two-dimensional heterojunction MoS with impedance storage characteristics 2 /h-BN/AuNPs。
As a further improvement, the SiO of the invention 2 the/Si substrate layer comprises a Si substrate layer and SiO from bottom to top 2 And a passivation layer.
As a further improvement, the MoS of the invention 2 The carrier transport layer and the AuNPs charge trapping layer are separated by an h-BN insulating dielectric layer.
As a further improvement, the AuNPs charge trapping layer has the thickness of 50-100nm, and the AuNPs charge trapping layer is Au nanoparticles.
The invention also discloses a preparation method of the floating gate type two-dimensional heterojunction memristor, which comprises the following preparation steps:
1) Depositing Ag electrode on SiO by thermal evaporation 2 The back of the/Si substrate, wherein the thickness of the Ag film is controlled to be 100-200nm;
2) By Chemical Vapor Deposition (CVD) on SiO 2 Growing MoS on a Si substrate 2 A carrier transport layer;
3) Depositing Au electrode on MoS through micro-nano processing technology 2 A carrier transport layer surface;
4) Stripping the block h-BN by using PDMS by using a mechanical stripping method to obtain a two-dimensional h-BN insulating dielectric film;
5) Two-dimensional h-BN insulating dielectric film on PDMS to MoS with Au electrode deposited by using transfer platform 2 The surface of the carrier transport layer becomes an h-BN insulating dielectric layer;
6) Synthesizing Au nano particles by using a hydrothermal method, and spin-coating the Au nano particles on the surface of the h-BN insulating dielectric layer to form an AuNPs charge trapping layer of the floating gate, thereby obtaining the MoS containing the two-dimensional heterojunction 2 A floating gate type two-dimensional heterojunction memristor of/h-BN/AuNPs.
As a further improvement, the Au electrode is deposited on the MoS through a micro-nano processing technology 2 Carrier transport layer surface, subsequent transfer of h-BN insulating dielectric layer to electrode deposited MoS 2 Carrier transport layer surface to obtain MoS 2 a/h-BN heterojunction.
As a further improvement, the SiO of the invention 2 Thermal evaporation process of Ag electrode at the bottom of Si is required in MoS 2 The growth of the carrier transport layer is completed before, and the thickness of the Ag electrode is 100-200nm.
As a further improvement, the MoS in the step 2) is adopted 2 The growth of the carrier transport layer is completed in a double-temperature tubular furnace, and the specific growth parameters are as follows: the first temperature zone is provided with a precursor S of sulfur element, and the second temperature zone is provided with MoO 3 And SiO 2 a/Si substrate, wherein the temperature control program of the first temperature zone is set as follows: RT (room temperature) (5 min) → 40 ℃ (21 min) → 40 ℃ (10 min) → 175 ℃ (5 min). The temperature control program of the second temperature zone is set as follows: RT (5 min) → 60 ℃ (5 min) → 60 ℃ (20 min) → 680 ℃ (5 min) → 800 ℃, and MoS obtained under the growth conditions 2 The thickness is 1-2nm.
The invention has the beneficial effects that:
1) By the pair MoS 2 MoS can be achieved by applying negative back gate voltage to the/h-BN/AuNPs device 2 the/h-BN/AuNPs device is arranged inThe low resistance state and the application of a positive back gate voltage can place the device in a high resistance state. That is, moS can be made by applying different back gate voltages 2 the/h-BN/AuNPs device switches between different impedance states.
2) Because the Au nanoparticles have good charge capture capacity and stability, the high-resistance state and the low-resistance state of the memristor show good stability within 12000s time scale.
3) MoS, a charge trapping mechanism, benefiting from floating-gate type memristors 2 MoS of/h-BN/AuNPs device 2 The channel is not easily damaged during the switching process. Therefore, the switching ratio of the device can still be maintained at 10 after more than 3000 repeated switching 4 Magnitude.
4)MoS 2 The carrier transmission layer and the AuNPs charge trapping layer are separated by the h-BN insulating dielectric layer, so that charges of the floating gate are prevented from leaking into a channel, and the storage time is prolonged.
5) The AuNPs charge trapping layer is 50-100nm thick and is Au nanoparticles. The thickness of the AuNPs charge trapping layer is within the range, so that the floating gate layer can be ensured to have higher charge trapping efficiency, and the switching ratio is improved.
6) In the preparation method, firstly, the Au electrode is deposited on the MoS through the micro-nano processing technology 2 Carrier transport layer surface, subsequent transfer of h-BN insulating dielectric layer to electrode deposited MoS 2 Carrier transport layer surface to obtain MoS 2 The sequence of depositing the electrode and transferring the h-BN by the h-BN heterojunction ensures that the h-BN insulating layer can transfer MoS 2 The channel and the metal electrode are completely covered to ensure Au nanoparticles and MoS 2 The channels are completely spaced apart.
7)SiO 2 Thermal evaporation process of Ag electrode at the bottom of Si is required in MoS 2 The growth of the carrier transport layer is completed before the thermal evaporation of the Ag electrode is carried out and then MoS is grown 2 The process sequence can avoid MoS due to high temperature in the evaporation process of the Ag electrode 2 The channel causes damage.
8) MoS in step 2) 2 The growth of the carrier transport layer is carried out in a two-temperature tube furnace,and set specific growth parameters under which the obtained MoS grows 2 Has unique size and high carrier mobility, which ensures unique impedance storage characteristics of the memristor.
9) Compared with the traditional memristor based on the bulk material, the memristor memory is constructed by the zero-dimensional and two-dimensional nano materials, and has unique advantages in the aspects of miniaturization and flexibility. It is considered that the device exhibits excellent information storage and erasure performance as well as good stability and reusability. Thus, the MoS introduced in the present invention 2 the/h-BN/AuNPs floating gate type memristor has good development prospect and practical value.
Drawings
FIG. 1 is a MoS 2 The structure schematic diagram of the/h-BN/AuNPs memristor;
FIG. 2 is a MoS 2 the/h-BN/AuNPs memristor realizes a conversion diagram between a High Resistance State (HRS) and a Low Resistance State (LRS) under the regulation of +8V and-8V gate voltages;
FIG. 3 is a MoS 2 An I-V curve change diagram under-2V to-20V grid voltage regulation of a/h-BN/AuNPs memristor;
FIG. 4 is a MoS 2 A characteristic diagram of the change of the switch ratio of the/h-BN/AuNPs memristor along with the switching times;
FIG. 5 is a resistance stability diagram of memristors in high and low resistance states;
FIG. 6 shows the structure of the CVD apparatus and the MoS 2 A schematic diagram of growth parameters;
FIG. 7 is a MoS 2 And the plan view schematic diagram of the structure of the/h-BN/AuNPs memristor.
In the figure, 1 is h-BN insulating dielectric layer, 2 is Au electrode, and 3 is MoS 2 A carrier transport layer, 4 is a Si substrate layer, 5 is an Ag electrode layer, and 6 is SiO 2 Passivation layer, 7 is Au nanoparticles;
FIG. 8 is a MoS 2 I-V curve diagram of the device (without AuNPs and h-BN) under the regulation of grid voltage;
FIG. 9 is MoS 2 I-V curve diagram of/h-BN device (without AuNPs) under gate voltage regulation.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation case in combination with the attached drawings of the specification:
FIG. 1 is a MoS 2 The structure schematic diagram of the/h-BN/AuNPs memristor; FIG. 7 is a MoS 2 A schematic diagram of a top view of a/h-BN/AuNPs memristor structure. The memristor is formed by sequentially forming an Ag electrode layer 5 and SiO from bottom to top 2 Si substrate layer 4, moS 2 Carrier transport layer 3, moS 2 Au electrodes 2,2 Au electrodes 2 and MoS are respectively arranged at two opposite ends of the upper surface of the carrier transmission layer 3 2 The upper surface formed by the carrier transmission layer 3 is covered with an h-BN insulating dielectric layer 1, and the h-BN insulating dielectric layer 1 is formed corresponding to the Au electrode 2 and the MoS 2 A groove is formed on the upper surface of the carrier transport layer 3, an AuNPs charge trapping layer, the h-BN insulating dielectric layer 1 and MoS are arranged on the upper surface of the h-BN insulating dielectric layer 1 in the groove 2 The carrier transport layer 3 constitutes a two-dimensional heterojunction MoS having an impedance storage characteristic 2 /h-BN/AuNPs。SiO 2 the/Si substrate layer 4 is a Si substrate layer 4 and SiO from bottom to top 2 A passivation layer 6.MoS 2 The carrier transport layer 3 is separated from the AuNPs charge trapping layer by an h-BN insulating dielectric layer 1. The AuNPs charge trapping layer has the thickness of 50-100nm, and the AuNPs charge trapping layer is Au nanoparticles 7.
Prepared MoS 2 The structure and the performance advantages of the/h-BN/AuNPs memristor are as follows:
1. MoS alone in the absence of h-BN insulating dielectric layer 1 and AuNPs charge trapping layer 2 The device did not exhibit memristive properties (see fig. 8);
2. MoS in the absence of AuNPs in the presence of an h-BN insulating dielectric layer 1 2 the/h-BN heterojunction device does not show memristive characteristics (see FIG. 9);
3. transfer of h-BN to MoS by means of transfer 2 The surface of the channel avoids the damage to the channel material caused by high temperature in the thermal deposition process of the insulating dielectric layer 1, and the service life and the stability of the device are improved. In contrast, the memristor reported by Zhou et al employs A 2 O 3 As a dielectric layer [1]]The channel material needs to undergo a high temperature thermal deposition process, and thus the channel material is formedThe stability and fatigue resistance of the device are lower than those of the device.
4. Compared with a CdSe quantum dot adopted as a charge trapping layer [1] reported by Zhou et al, the Au nanoparticle 7 is adopted as the charge trapping layer, so that the stability of the memristor is effectively improved, the memristor has a longer retentime in a low resistance state, and the information storage time is prolonged.
Detailed device fabrication process
CVDMoS 2 FIG. 6 is the MoS 2 The photoetching and deposition process of the surface Au/Cr electrode is schematically shown;
firstly, siO is firstly 2 Cutting the/Si sheet into 1 cm-1 cm, performing ultrasonic treatment in ethanol and deionized water for several minutes, and drying to obtain clean SiO 2 a/Si substrate. Then MoS is treated by using a two-temperature zone tube furnace 2 Grown on SiO 2 The surface of the Si substrate. The specific growth conditions are as follows: the first temperature zone is provided with a precursor (S) of sulfur element, and the second temperature zone is provided with MoO 3 And SiO 2 a/Si substrate (as shown in figure 6). Wherein, the temperature control program of the first temperature zone is set as follows: RT (room temperature) (5 min) → 40 ℃ (21 min) → 40 ℃ (10 min) → 175 ℃ (5 min). The temperature control program of the second temperature zone is set as follows: RT (5 min) → 60 ℃ (5 min) → 60 ℃ (20 min) → 680 ℃ (5 min) → 800 ℃. MoS obtained under the growth conditions 2 The thickness is 1-2nm.
Deposition of Ag films
Selecting the growth of MoS 2 SiO of (2) 2 the/Si sheet is characterized in that a specific area on the surface of Si is shielded by using an adhesive tape as a shielding layer, and then an Ag electrode pattern is deposited on the lower surface of Si by using a thermal evaporation device.
Deposition of Au electrode 2
First, a semiconductor photoetching process is used for printing a pattern of the Au electrode 2 on the MoS 2 Surface, and depositing 20nmAu film on MoS by electron beam thermal evaporation 2 Surface, and finally stripping in acetone to deposit electrode pattern on MoS 2 A surface.
Preparation of two-dimensional h-BN insulating dielectrics
h-BN is prepared by a mechanical stripping process: firstly, using scotch tape to stick one side of the block h-BN, using PDMS to stick the other side of the block h-BN, and then quickly tearing off the PDMS so as to tear the block h-BN. This procedure was repeated several times to adhere nanometer thickness of h-BN to PDMS (near transparent under microscope).
MoS 2 Preparation of h-BN heterojunction
Transfer of h-BN to MoS with Au electrode 2 deposited Using a mechanical transfer platform 2 The surface needs to be adjusted in angle and position during the transfer process to ensure that the h-BN insulating dielectric film can transfer MoS 2 The channel region is completely covered. Firstly, the electrode is deposited on MoS 2 Surface, then the h-BN is transferred again and covers the entire MoS 2 And an electrode region ensuring the Au nanoparticles 7 and MoS of the floating gate 2 The channels are completely isolated, preventing charge leakage.
MoS 2 Preparation of AuNPs charge trapping layer on surface of/h-BN/AuNPs
The method is the whole process for preparing the MoS2/h-BN/AuNPs memristor.
MoS comprising two-dimensional heterojunction 2 Performance test and effect analysis of floating gate type two-dimensional heterojunction memristor of/h-BN/AuNPs
To test MoS 2 The electric transport characteristic and the impedance regulation characteristic of a/h-BN/Au memristor are realized by firstly using soldering tin to mix MoS 2 the/h-BN/Au memristor is integrated on a PCB, and then the device is connected into a semiconductor analyzer through a gold wire.
FIG. 2 is a MoS 2 the/h-BN/AuNPs memristor realizes a conversion diagram between a High Resistance State (HRS) and a Low Resistance State (LRS) under the regulation and control of +8V and-8V gate voltage; the process that the impedance of the device is changed from an initial state (original state) to a Low Resistance State (LRS) under the back gate voltage regulation of-8V, and then the impedance of the device is changed from the Low Resistance State (LRS) to a High Resistance State (HRS) under the back gate voltage regulation of +8V is shown.
FIG. 3 is a MoS 2 h-BN/AuNPs memristorThe I-V curve changes under the regulation of 2V to-20V grid voltage; shows the gradual change process of the device from the HRS state to the LRS state under the regulation of a series of different negative grid voltages, and indicates that the MoS 2 the/h-BN/Au memristor can be in a plurality of different stable impedance states (the characteristic enables the device to have application potential of multi-bit information storage).
FIG. 4 is a MoS 2 A characteristic diagram of the change of the switch ratio of the/h-BN/AuNPs memristor along with the switching times; FIG. 5 is a graph of resistance stability of a memristor in high and low resistance states; respectively show MoS 2 Repeated switching durability and resistance state stability of the/h-BN/Au device. The results in fig. 4 show that the switching ratio of the device remains 10 after more than 3000 switching iterations 4 And (4) the scale factor represents excellent robustness and durability. The result of FIG. 5 shows that the device exhibits good stability in a 12000s time scale when being in a high resistance state and a low resistance state, the performance index is significantly higher than that of other memristors based on two-dimensional materials, and excellent information storage stability is exhibited.
The above is the performance index of the device under the specific structural parameters in the present invention, and it should be noted that, within the framework of the core technical features of the present invention, the optimization and improvement of the device in the present invention should also be regarded as the protection scope of the present invention.
Claims (8)
1. A floating gate type two-dimensional heterojunction memristor is characterized in that the memristor sequentially comprises an Ag electrode layer (5) and SiO from bottom to top 2 a/Si substrate layer (4), moS 2 Carrier transport layer (3), said MoS 2 Au electrodes (2) are arranged at two opposite ends of the upper surface of the current carrier transmission layer (3), and the Au electrodes (2) and the MoS are arranged 2 The upper surface formed by the carrier transmission layer (3) is covered with an h-BN insulating dielectric layer (1), and the h-BN insulating dielectric layer (1) is formed corresponding to the Au electrode (2) and the MoS 2 A groove on the upper surface formed by the carrier transport layer (3), wherein the AuNPs charge trapping layer is arranged on the upper surface of the h-BN insulating dielectric layer (1) in the groove, and the AuNPs charge trapping layer, the h-BN insulating dielectric layer (1) and the MoS 2 The carrier transport layer (3) is provided withTwo-dimensional heterojunction MoS of impedance memory characteristics 2 /h-BN/AuNPs。
2. The floating gate type two-dimensional heterojunction memristor according to claim 1, wherein the SiO is 2 the/Si substrate layer (4) comprises a Si substrate layer (4) and SiO from bottom to top 2 A passivation layer (6).
3. The floating gate type two-dimensional heterojunction memristor according to claim 1, wherein the MoS 2 The carrier transport layer (3) and the AuNPs charge trapping layer are separated by an h-BN insulating dielectric layer (1).
4. The heterojunction floating gate type memristor according to claim 1, wherein the AuNPs charge trapping layer is 50-100nm thick, and the AuNPs charge trapping layer is Au nanoparticles (7).
5. The preparation method of the floating gate type two-dimensional heterojunction memristor according to the claims 1, 3, 4 or 5, is characterized by comprising the following preparation steps:
1) Depositing Ag electrode on SiO by thermal evaporation 2 The back of the/Si substrate, wherein the thickness of the Ag film is controlled to be 100-200nm;
2) By Chemical Vapor Deposition (CVD) on SiO 2 Growing MoS on a Si substrate 2 A carrier transport layer;
3) Depositing Au electrode (2) on MoS through micro-nano processing technology 2 A carrier transport layer surface;
4) Stripping the block h-BN by using PDMS by using a mechanical stripping method to obtain a two-dimensional h-BN insulating dielectric film;
5) Two-dimensional h-BN insulating dielectric film on PDMS to MoS deposited Au electrode (2) using transfer platform 2 The surface of the carrier transport layer becomes an h-BN insulating dielectric layer (1);
6) Synthesizing Au nano-particles (7) by using a hydrothermal method, and spin-coating the Au nano-particles on the surface of the h-BN insulating dielectric layer (1) to form A of the floating gateuNPs charge trapping layer, thereby obtaining a MoS containing two-dimensional heterojunction 2 A floating gate type two-dimensional heterojunction memristor of/h-BN/AuNPs.
6. The preparation method of the floating gate type two-dimensional heterojunction memristor according to claim 5, wherein the Au electrode (2) is deposited on the MoS through a micro-nano processing technology 2 The surface of the carrier transport layer (3) is transferred to the h-BN insulating dielectric layer (1) on the MoS of the deposited electrode 2 MoS is obtained on the surface of the carrier transmission layer (3) 2 a/h-BN heterojunction.
7. The method for preparing the floating gate type two-dimensional heterojunction memristor according to claim 5, wherein the SiO is 2 Thermal evaporation process of Ag electrode at the bottom of Si is required in MoS 2 The growth of the carrier transport layer (3) is completed before, and the thickness of the Ag electrode is 100-200nm.
8. The method for preparing the floating gate type two-dimensional heterojunction memristor according to claim 5, wherein MoS in the step 2) 2 The growth of the carrier transport layer (3) is completed in a double-temperature tube furnace, and the specific growth parameters are as follows: the first temperature zone is placed with a precursor S of sulfur element, and the second temperature zone is placed with MoO 3 And SiO 2 a/Si substrate, wherein the temperature control program of the first temperature zone is set as follows: RT (room temperature) (5 min) → 40 ℃ (21 min) → 40 ℃ (10 min) → 175 ℃ (5 min). The temperature control program of the second temperature zone is set as follows: RT (5 min) → 60 ℃ (5 min) → 60 ℃ (20 min) → 680 ℃ (5 min) → 800 ℃, and MoS obtained under the growth conditions 2 The thickness is 1-2nm.
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