CN114094009A - Resistive memory device based on multiple resistive layers and preparation method thereof - Google Patents

Resistive memory device based on multiple resistive layers and preparation method thereof Download PDF

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Publication number
CN114094009A
CN114094009A CN202111385644.3A CN202111385644A CN114094009A CN 114094009 A CN114094009 A CN 114094009A CN 202111385644 A CN202111385644 A CN 202111385644A CN 114094009 A CN114094009 A CN 114094009A
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China
Prior art keywords
resistive
random access
access memory
resistive random
film
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CN202111385644.3A
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Inventor
蔡一茂
王宗巍
王錡深
杨宇航
黄如
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Peking University
Beijing Superstring Academy of Memory Technology
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Peking University
Beijing Superstring Academy of Memory Technology
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Priority to CN202111385644.3A priority Critical patent/CN114094009A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/023—Formation of the switching material, e.g. layer deposition by chemical vapor deposition, e.g. MOCVD, ALD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes

Abstract

The invention discloses a resistive random access memory based on multiple resistive layers and a preparation method thereof, and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The resistive random access memory device with high retentivity is realized based on the traditional CMOS process, and the core of the resistive random access memory device is that a resistive layer is formed by alternately overlapping an interception characteristic film and a resistive material film with resistive characteristics to form a multilayer resistive layer structure. The invention can reduce or even eliminate the problem of ion migration of the resistive layer in the crossbar structure of the resistive random access memory by adjusting the potential barrier at the interface, and can effectively inhibit the low retention of the device. Meanwhile, the multilayer resistive layer structure is beneficial to increasing the state number of devices, and a road is paved for realizing large-scale integration and commercialization of the resistive random access memory.

Description

Resistive memory device based on multiple resistive layers and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor and CMOS hybrid integrated circuits, and particularly relates to a resistive random access memory based on multiple resistive layers and a preparation method thereof.
Background
As the moore's law limit approaches, the drawbacks of von neumann structures become more and more pronounced, manifested as low memory efficiency and high power consumption. Meanwhile, with the iterative update of the internet technology, the artificial intelligence technology puts higher demands on the storage device. The non-von neumann structure is embodied in that the demand of a near memory and storage and computation integrated technology on a novel nonvolatile device gradually rises, wherein a resistance type Resistive Random Access Memory (RRAM) becomes a powerful competitor for replacing a traditional flash memory by virtue of the advantages of a simple three-layer structure (an upper electrode, a resistive layer and a lower electrode), low power consumption, high-density integration, high read-write speed and the like. Under the condition of low operating voltage, the interface type RRAM has two states of high resistance HRS and low resistance LRS, which correspond to the states of 1 and 0 in a digital circuit, and the corresponding physical image is that under the action of an electric field, oxygen vacancies (oxygen ions) are subjected to migration motion to form a non-metallic conductive region; when Schottky barriers exist between the electrode and the functional layer, the accumulation of oxygen vacancies at the interface can cause the change of the barrier height so as to influence the resistance change switching process, which is similar to the control switching process of the oxygen vacancy conductive filament. RRAM of the interface type has many features, such as high erase times 1012Switching speeds less than 1ns, etc. With the optimization of the process and design, the multi-bit RRAM is gradually widely circulated, and the state number is increased from 1bit to 2bit, and the like.
However, for interface type RRAM devices, reliability has been a problem of research, such as the retentivity characteristics of the device, which is expressed as the Retention time of the states (e.g., "0" and "1" states) of the device. In a memory array, when the resistance of the device is changed by applying voltages through the word lines and bit lines, the oxygen-rich region widens, oxygen-vacancy conductive filaments form, the barrier at the interface drops, and the device changes from HRS to LRS. However, with the lapse of time, process errors and the influence of the surrounding environment, such as poor contact between layers, heat transferred from nearby devices, leakage current provided by the memory devices gated around, etc., the migration of ions in the resistive layer of the device is compounded with oxygen vacancies and the corresponding change of the conductive wires, and in a serious case, the rupture of the film may be caused, so that the stored information is changed.
In order to solve the retention problem faced by the resistive random access memory array, the current research mainly stays on changing materials or adjusting the thickness of the resistive random access memory array. For example, the mixing ratio of the resistance change layer material and oxygen is changed in the process (AO is changed)xX in (m), a variety of different materials such as (SiO) are triedx,HfOx,TaOx,VOxEtc.) or thickening the resistive layer (for example, from 10A to 100A), or adding a wrapping layer (SiNx, etc.) around the device to achieve the purpose of retentivity improvement. However, the selection of multiple materials brings respective disadvantages, such as the reduction of the state number (some materials can only reach less than 2bit state number for most parts), the improvement of retentivity is not obvious, and the like.
Disclosure of Invention
In view of the above disadvantages, the present invention provides a resistive memory device, which utilizes a conventional CMOS process to implement a resistive memory device with high retentivity, and adjusts a potential barrier at an interface to reduce or even eliminate the problem of ion migration of a resistive layer in a crossbar structure of the resistive memory.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a resistive random access memory is characterized in that a resistive layer of the resistive random access memory is formed by alternately overlapping a barrier property film and a resistive material film with a resistive property to form an n-layer resistive layer structure, wherein n is more than or equal to 3.
The resistance change material film adopts transition metal oxide with resistance change property, and the thickness is 5nm-100 nm; or organic material with thickness of 200nm-500 nm; the transition metal oxide is TaOx、HfOx、SiOxOr SrTiO3And the like, and the organic material is parylene.
The interception characteristic film adopts SiOXBN, graphene, graphite, etc., with a thickness of 1nm to 10 nm.
A preparation method of a resistive random access memory comprises the following steps:
1) defining a bottom electrode pattern, and preparing a bottom electrode on a substrate according to the pattern;
2) depositing a resistance change material film on the bottom electrode by adopting a PVD (physical vapor deposition), ALD (atomic layer deposition) or CVD (chemical vapor deposition) method;
3) depositing an interception characteristic film on the resistance change material film by adopting a PVD or ALD method, and carrying out a corresponding annealing treatment process according to the material property;
4) repeating the steps 2) and 3)
5) Defining a bottom electrode lead-out hole pattern, and etching a bottom electrode lead-out hole on the resistance change material film and the interception characteristic film according to the pattern;
6) and defining a top electrode pattern, and preparing the top electrode on the modification layer according to the pattern.
Further, the method for defining the pattern in the steps 1), 5) and 6) is to define the pattern on the photoresist by using a photolithography technique.
Further, the preparation method of the bottom electrode and the top electrode comprises PVD and evaporation deposition methods.
Further, the substrate is made of silicon or glass; the bottom electrode and the top electrode are made of active materials or inert materials, such as W, Au, TiN, Pt and the like, and the thickness of the bottom electrode and the top electrode is 10nm-400 nm.
Furthermore, the resistive material film adopts transition metal oxide with resistive property, and the thickness is 5nm-50 nm; or organic material with thickness of 200-500 nm.
Furthermore, the interception characteristic film is made of graphene, BN, SiOx and the like, and the thickness of the film is 1nm-10 nm.
The invention provides a resistive random access memory based on multiple resistive layers and a preparation method thereof. The resistive random access memory has high reliability on the basis of combining multiple advantages of interfacial RRAM, a resistive layer which originally forms a small amount of/single conductive wires is divided into a plurality of sections of conductive wires by using a film with multiple interception characteristics, and the migration probability of oxygen vacancies is reduced by adjusting the energy barrier of ion migration at the interface; the problem of the change of the resistance state due to the migration of oxygen vacancies originally is optimized, so that the low holding power of the device can be effectively suppressed. Meanwhile, the multi-resistance-change layer structure of the device is also beneficial to increasing the state number of the device. The invention paves the way for realizing large-scale integration and commercialization of the resistive random access memory.
Drawings
Fig. 1-7 correspond to implementation steps of various embodiments.
Fig. 8 is an illustration of fig. 1-7.
Detailed Description
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
This embodiment provides a resistive random access memory based on multiple resistive layers and a method for manufacturing the same, in which a silicon substrate is used, TiN is used as a bottom electrode material, and TaO is used as a bottom electrode material2(or non-stoichiometric oxide thereof) as a resistance change material film, and graphene and thin SiO layer are adopted2As the barrier property film, TiN was used as the top electrode material.
SiO2And TaO2Are all materials compatible with standard CMOS processes. Based on TaO2The resistive random access memory has the advantages of ultra-fast switching speed, high switching ratio, multiple state numbers, good holding characteristics, simple preparation and high controllability. Graphene and SiO2The ion mobility can be limited in the direction perpendicular to the plane, the advantages of the materials are combined, the reasonable design of the physical mechanism layer and the adjustment of the barrier height meet the requirements of being compatible with a CMOS (complementary metal oxide semiconductor) process, the good performance and reliability of the resistive random access memory can be realized, and the method has important significance for the improvement of the integration density of the cross bar structure array of the resistive random access memory and the large-scale production.
The preparation method of the resistive random access memory comprises the following steps:
1) defining a bottom electrode pattern on the photoresist by utilizing a photoetching technology, depositing a TiN bottom electrode material on a silicon substrate by adopting a PVD method, wherein the thickness is 70nm, and then removing the photoresist, as shown in figure 1;
2) depositing a layer of TaO on the bottom electrode by ALD2The resistance change material thin film is 6nm in thickness and is shown in figure 2;
3) depositing a layer of SiO on the resistance change material film by adopting an ALD method2The interception characteristic film is used for adjusting an interface potential barrier, and the thickness is 3nm, as shown in FIG. 3;
4) depositing a layer of TaO on the bottom electrode by ALD2A resistance change material thin film with a thickness of 6nm as shown in FIG. 4;
5) depositing a layer of multilayer graphene interception characteristic film on the resistance change material film by using an ALD method for adjusting an interface potential barrier, wherein the thickness of the multilayer graphene interception characteristic film is about 2-10 layers, as shown in figure 5;
6) defining a bottom electrode lead-out hole pattern on the photoresist by using a photoetching technology, and removing the photoresist, as shown in FIG. 6;
7) defining a top electrode pattern on the photoresist by utilizing a photoetching technology, depositing a TiN top electrode material on the energy band modification layer by adopting a PVD method, wherein the thickness is 100nm, and removing the photoresist to obtain the resistive random access memory, as shown in figure 7.
From the embodiment, the transition metal oxide resistance change material thin film and the barrier property thin film can be prepared by adopting a PVD method and an ALD method, and compared with the PVD method, the ALD method can be used for preparing thinner films; the CVD method is adopted for preparing the organic material as the resistance change material film.
The above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person skilled in the art can modify the technical solution of the present invention or substitute the same without departing from the spirit and scope of the present invention, and the scope of the present invention should be determined by the claims.

Claims (10)

1. A resistive random access memory is characterized in that a resistive layer of the resistive random access memory is formed by alternately overlapping an interception characteristic film and a resistive material film with a resistive characteristic.
2. The resistive random access memory according to claim 1, wherein the resistive random material film is made of a transition metal oxide having a resistive property, and has a thickness of 5nm to 100 nm; or organic material with thickness of 200-500 nm.
3. The resistive random access memory according to claim 1, wherein the blocking characteristic film is made of SiOXBN, graphene or graphite material with a thickness of 1nm to 10 nm.
4. The resistive-switching memory according to claim 2, wherein the transition metal oxide is TaOx、HfOx、SiOxOr SrTiO3The organic material is parylene.
5. A preparation method of a resistive random access memory comprises the following steps:
1) defining a bottom electrode pattern, and preparing a bottom electrode on a substrate according to the pattern;
2) depositing a resistance change material film on the bottom electrode by adopting a physical vapor deposition, atomic layer deposition or chemical vapor deposition method;
3) depositing an interception characteristic film on the resistance change material film by adopting a PVD or ALD method;
4) repeating the steps 2) and 3) to form a resistance change layer structure formed by alternately overlapping the interception characteristic film and the resistance change material film;
5) defining a bottom electrode lead-out hole pattern, and etching a bottom electrode lead-out hole on the resistance change material film and the interception characteristic film according to the pattern;
6) and defining a top electrode pattern, and preparing the top electrode according to the pattern.
6. The method for preparing a resistive random access memory according to claim 5, wherein the pattern is defined in the steps 1), 5) and 6) by using a photolithography technique.
7. The method for manufacturing a resistive random access memory according to claim 5, wherein the substrate in the step 1) is made of silicon or glass.
8. The preparation method of the resistive random access memory according to claim 5, wherein the bottom electrode and the top electrode in the steps 1), 5) and 6) are made of W, Au, TiN or Pt, and the thickness is 10nm to 400 nm; the preparation methods of the bottom electrode and the top electrode comprise PVD and evaporation deposition methods.
9. The method for manufacturing a resistive random access memory according to claim 5, wherein the resistive random material film in the step 2) is made of a transition metal oxide having a resistive characteristic, and has a thickness of 5nm to 100 nm; or organic material with thickness of 200-500 nm.
10. The method for manufacturing a resistive random access memory according to claim 5, wherein the blocking characteristic film is made of SiOXBN, graphene or graphite material with a thickness of 1nm to 10 nm.
CN202111385644.3A 2021-11-22 2021-11-22 Resistive memory device based on multiple resistive layers and preparation method thereof Pending CN114094009A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115472643A (en) * 2022-09-27 2022-12-13 厦门半导体工业技术研发有限公司 Semiconductor integrated circuit device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115472643A (en) * 2022-09-27 2022-12-13 厦门半导体工业技术研发有限公司 Semiconductor integrated circuit device and method for manufacturing the same
CN115472643B (en) * 2022-09-27 2023-12-19 厦门半导体工业技术研发有限公司 Semiconductor integrated circuit device and method for manufacturing the same

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