CN115224953B - Multi-output synchronous buck converter and converter control method - Google Patents
Multi-output synchronous buck converter and converter control method Download PDFInfo
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- CN115224953B CN115224953B CN202211146620.7A CN202211146620A CN115224953B CN 115224953 B CN115224953 B CN 115224953B CN 202211146620 A CN202211146620 A CN 202211146620A CN 115224953 B CN115224953 B CN 115224953B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33561—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having more than one ouput with independent control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33571—Half-bridge at primary side of an isolation transformer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The application discloses a multi-output synchronous buck converter and a converter control method, wherein the converter control method comprises the following steps: in a control period T of the multi-output synchronous buck converter, the switching tube circuit is controlled in an FCCM (fast switching mode) working mode, when the switching tubes of the switching tube circuit of the multi-output synchronous buck converter are all cut off in the control period T, the multi-output synchronous buck converter is controlled in a DCM (discontinuous conduction mode) working mode, wherein the directions of output currents of primary side output subunits of the multi-output synchronous buck converter are opposite to each other in the FCCM working mode control and the DCM working mode control. Because the multi-output synchronous buck converter is controlled by adopting two working modes of FCCM and DCM in a control period T, the technical problem that the conversion efficiency of the multi-output synchronous buck converter is reduced when the multi-output synchronous buck converter is in light load is solved, and the output of an isolation side can have good load regulation rate.
Description
Technical Field
The invention relates to the technical field of direct current conversion, in particular to a multi-output synchronous buck converter and a converter control method.
Background
With the rapid development of power electronic technology, people's demand for various electronic products is increasing day by day, and demand for dc power supply is also increasing. For example, many specific devices require a plurality of isolated power supplies to be turned on simultaneously for synchronous operation, such as ground data terminals, rf controllers, etc. The technical problem of synchronously turning on equipment or synchronously turning on a power supply is used in many fields. In the prior art, a mode of a forced current continuous conduction mode (FCCM) is generally adopted for a multi-output synchronous buck converter, however, when the FCCM mode is in a light load condition, because a switching frequency is kept unchanged, a ratio of a switching loss to a total loss is increased, and efficiency is reduced. If the operating frequency is reduced along with the reduction of the load when the controller is in light load in order to improve the light load efficiency, the conduction time of the lower tube is insufficient, the charge compensation of the output capacitor on the isolation side is less than the charge consumption, and the output voltage on the isolation side is unstable or even cannot meet the requirement.
Disclosure of Invention
The technical problem that multi-output synchronous buck converter is low in electric energy conversion efficiency under the condition of light load in an FCCM (frequency control modulation) working mode is mainly solved.
According to a first aspect, there is provided in one embodiment a multi-output synchronous buck converter comprising a loop control logic output circuit and an isolated multi-output synchronous buck circuit;
the loop control logic output circuit is used for sending an upper tube driving signal HG and a lower tube driving signal LG to a switching tube circuit in the isolated multi-output synchronous buck circuit so as to realize the switching control of a power switching tube of the switching tube circuit;
the isolated multi-output synchronous voltage reduction circuit also comprises a primary side output subunit and n secondary side output subunits, wherein n is a natural number; the switching tube circuit comprises an upper switching tube Q1 and a lower switching tube Q2; the switch control electrodes of the upper switch tube Q1 and the lower switch tube Q2 respectively respond to the upper tube driving signal HG and the lower tube driving signal LG to realize switch control so as to output the electric energy of the first direct current Vin to the primary side output subunit and each secondary side output subunit;
the primary side output subunit is used for converting the electric energy output to the primary side output subunit by the switching tube circuit into a second direct current Vout0 and outputting the second direct current Vout 0;
each secondary output subunit is used for converting the electric energy output to the secondary output subunit by the switching tube circuit into third direct current Vout1 and outputting the third direct current Vout 1;
the upper tube driving signal HG comprises an upper tube on level signal and an upper tube off level signal, the upper switch tube Q1 is on when the upper tube driving signal HG is maintained at the upper tube on level signal, and the upper switch tube Q1 is off when the upper tube driving signal HG is maintained at the upper tube off level signal;
the lower tube driving signal LG comprises a lower tube on level signal and a lower tube off level signal, the lower switch tube Q2 is turned on when the lower tube driving signal LG is maintained at the lower tube on level signal, and the lower switch tube Q2 is turned off when the lower tube driving signal LG is maintained at the lower tube off level signal;
at any time, when the upper tube driving signal HG is the upper tube conducting level signal, the lower tube driving signal LG cannot be the lower tube conducting level signal, so as to ensure that the upper switch tube Q1 and the lower switch tube Q2 cannot be simultaneously conducted;
in each signal period T, the upper tube driving signal HG includes a continuous upper tube conduction duration period and a continuous upper tube shutdown duration period, the upper tube driving signal HG is kept as an upper tube conduction level signal during the upper tube conduction duration period, and the upper tube driving signal HG is kept as an upper tube shutdown level signal during the upper tube shutdown duration period;
during the signal period T, the lower tube driving signal LG comprises a first lower tube on duration period and a second lower tube on duration period which are continuous, and the lower tube driving signal LG is kept to be a lower tube on level signal during the first lower tube on duration period and the second lower tube on duration period;
in the signal period T, the upper tube on duration and the first lower tube on duration are consecutive in time, and when the upper tube driving signal HG is in the upper tube on duration and the lower tube driving signal LG is in the first lower tube on duration, the direction of the output current of the primary side output subunit is a first direction; when the down tube driving signal LG is turned on for a second down tube duration, the direction of the current output by the primary side output subunit is a second direction, and the directions of the first direction and the second direction are opposite.
According to a second aspect, there is provided in an embodiment a converter control method for use in a multi-output synchronous buck converter as defined in the first aspect, the control method comprising:
in a control period T of the switching tube circuit, the switching tube circuit is controlled in an FCCM (flash control cm) working mode, so that the direction of the current output by the primary side output subunit is a first direction;
in the control period T, when both the upper switching tube Q1 and the lower switching tube Q2 of the switching tube circuit are turned off, the switching tube circuit is controlled in a DCM operation mode, so that the direction of the current output by the primary side output subunit is a second direction, wherein the first direction and the second direction are opposite.
In one embodiment, the inverter control method further comprises:
in each control period T, the DCM operation mode is set before or after the FCCM operation mode.
According to the converter control method of the embodiment, two working modes of FCCM and DCM are respectively adopted to control the multi-output synchronous buck converter in one control period T, so that the technical problem that the conversion efficiency of the multi-output synchronous buck converter is reduced under light load is solved, and the output of the isolation side has good load regulation rate.
Drawings
FIG. 1 is a block diagram of a multi-output synchronous buck converter in one embodiment;
FIG. 2 is a schematic diagram of the circuit connections of the isolated multi-output synchronous buck circuit in one embodiment;
FIG. 3 is a schematic diagram of the circuit connections of the output circuit of the loop control logic according to one embodiment;
FIG. 4 is a schematic diagram of the circuit connections of the feedback signal obtaining circuit in one embodiment;
FIG. 5 is a schematic diagram of the logic control of the switching tube circuit in one embodiment;
FIG. 6 is a schematic diagram showing waveforms of the switch control signals of the switch circuit according to an embodiment;
FIG. 7 is a schematic diagram of the logic control of a switching tube circuit in another embodiment;
FIG. 8 is a schematic diagram of the logic control of the switching tube circuit in a first additional on-time setting mode according to an embodiment;
FIG. 9 is a schematic diagram illustrating logic control of a switching tube circuit according to a second additional on-time setting mode in an embodiment;
FIG. 10 is a logic control diagram of a switching tube circuit in a third additional on-time setting mode according to an embodiment;
fig. 11 is a flowchart illustrating a converter control method according to an embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments have been given like element numbers associated therewith. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the description of the methods may be transposed or transposed in order, as will be apparent to a person skilled in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The ordinal numbers used herein for the components, such as "first," "second," etc., are used merely to distinguish between the objects described, and do not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
The multi-output synchronous buck converter disclosed in the embodiment of the application comprises a loop control logic output circuit and an isolation multi-output synchronous buck circuit, wherein the loop control logic output circuit is used for outputting an upper tube driving signal HG and a lower tube driving signal LG to an upper switch tube Q1 and a lower switch tube Q2 of a switch tube circuit in the synchronous buck circuit to carry out switch control, so that the electric energy of a first direct current Vin is output to a primary side output subunit and each secondary side output subunit of the isolation multi-output synchronous buck circuit. In a control period T of the switching tube circuit, on the premise of ensuring that the output voltage of each secondary output subunit on the isolation side is within a preset output range, the lower switching tube Q2 is additionally conducted for a period of time so as to supplement charges to the output capacitor of each secondary output subunit, and therefore the purpose of improving the electric energy conversion efficiency of the multi-output synchronous buck converter when the multi-output synchronous buck converter works under the condition of light load is achieved.
Example one
Referring to fig. 1, a block diagram of an embodiment of a multi-output synchronous buck converter includes a loop control logic output circuit 100 and an isolated multi-output synchronous buck circuit 200. The loop control logic output circuit 100 is configured to send an upper tube driving signal HG and a lower tube driving signal LG to a switching tube circuit in the isolated multi-output synchronous buck circuit 200, so as to implement switching control on a power switching tube of the switching tube circuit.
Referring to fig. 2, which is a schematic diagram of a circuit connection of an isolation multi-output synchronous buck circuit in an embodiment, the isolation multi-output synchronous buck circuit 200 includes a switching tube circuit 210, a primary side output subunit 220, and n secondary side output subunits 230, where n is a natural number. The switching tube circuit 210 includes an upper switching tube Q1 and a lower switching tube Q2, and switching control electrodes of the upper switching tube Q1 and the lower switching tube Q2 respectively respond to the upper tube driving signal HG and the lower tube driving signal LG to realize switching control so as to output the electric energy of the first direct current Vin to the primary side output subunit 220 and each secondary side output subunit 230. The primary side output subunit 220 includes a primary side inductor L0, a primary side output capacitor C0, and a primary side output terminal for outputting the second direct current Vout 0. One end of the primary side inductor L0 is connected to the switching tube circuit 210, and the other end is connected to the primary side output terminal. One end of the primary side output capacitor C0 is connected with the primary side output end, and the other end is grounded. The primary side output subunit 220 is configured to convert the electric energy output by the switching tube circuit 210 to the second direct current Vout0, and output the converted electric energy. Each secondary output subunit 230 includes a secondary inductor L1, a secondary diode D1, a secondary output capacitor C1, and a secondary output terminal for outputting a third direct current Vout 1. One end of the secondary inductor L1 is connected to the anode of the secondary diode D1, and the other end is grounded, and the secondary inductor L1 is used to obtain electric energy from the switching tube circuit 210 through the primary inductor L0 by applying the mutual inductance principle. And the cathode of the secondary side diode D1 is connected with the secondary side output end. One end of the secondary output capacitor C1 is connected with the secondary output end, and the other end is grounded. Each secondary output subunit 230 is configured to convert the electric energy output from the switching tube circuit 210 to the secondary output subunit 230 into a third direct current Vout1, and output the third direct current Vout 1. The upper switch tube Q1 and the lower switch tube Q2 of the switch tube circuit 210 respectively include a control electrode, a first connection electrode and a second connection electrode, the first connection electrode of the upper switch tube Q1 is used for connecting a first direct current Vin, the second connection electrode of the upper switch tube Q1 is connected with the first connection electrode of the lower switch tube Q2, and the second connection electrode of the lower switch tube Q2 is grounded. The second connection pole of the upper switching tube Q1 is further connected to one end of the inductor L0 of the primary side output subunit 220.
Referring to fig. 3, which is a schematic diagram illustrating circuit connections of a loop control logic output circuit in an embodiment, the loop control logic output circuit 100 includes an On-Time generating circuit 110, a feedback signal acquiring circuit 120, a switch trigger signal generating circuit 130, and a control signal output circuit 140. The On-Time generating circuit 110 is connected to the control signal output circuit 140, and the On-Time generating circuit 140 is configured to generate the switch driving signal HSD _ OFF to the control signal output circuit 140. The feedback signal acquiring circuit 120 is respectively connected to the primary side output subunit 220 and the switch trigger signal generating circuit 130, and the feedback signal acquiring circuit 120 is configured to sample the second direct current Vout0 output by the primary side output subunit 220 and output a feedback signal obtained by sampling to the switch trigger signal generating circuit 130. The switch trigger signal generating circuit 130 is connected to the control signal output circuit 1440, and the switch trigger signal generating circuit 130 is configured to output the switch trigger signal HSD _ ON to the control signal output circuit 140 according to the feedback signal. The control signal output circuit 140 is configured to send an upper tube driving signal HG and a lower tube driving signal LG to the switching tube circuit 210 according to the switching tube driving signal HSD _ OF and the switching trigger signal HSD _ ON.
In one embodiment, the switch trigger signal generating circuit 130 includes a ripple generating circuit 131, an error amplifier 132, a comparator 133, and a ramp generating circuit 134. The error amplifier 132 is connected to the feedback signal obtaining circuit 120, and the error amplifier 132 is used for amplifying the feedback signal. The ripple generating circuit 131 is configured to generate a ripple signal, the ramp generating circuit 134 is configured to generate a ramp signal, and the comparator 133 is configured to compare a signal obtained by synthesizing the ripple signal and the feedback signal with a signal obtained by synthesizing the ramp signal and the amplified feedback signal, and send a comparison result signal obtained by the comparison to the control signal output circuit 140 as the switch trigger signal HSD _ ON.
Referring to fig. 4, which is a schematic diagram illustrating a circuit connection of the feedback signal obtaining circuit in an embodiment, the feedback signal obtaining circuit 120 includes a sampling input terminal, a sampling output terminal, a first resistor R1, and a second resistor R2. The input terminal is connected to the primary side output subunit 220, and is used for inputting the second direct current Vout 0. The sampling output terminal is connected to the switch trigger signal generating circuit 130, and the sampling output terminal is used for outputting a feedback signal to the switch trigger signal generating circuit 130. One end of the first resistor R1 is connected with the sampling input end, the other end of the first resistor R1 is connected with the sampling output end, one end of the second resistor R2 is connected with the sampling output end, and the other end of the second resistor R2 is grounded.
As shown in fig. 2, in the output synchronous buck converter, the second direct current Vout0 output by the primary side output subunit 220 is in closed-loop control, and the third direct current Vout1 output by each secondary side output subunit 230 on the isolation side is in an open-loop state, so that the output voltage accuracy is difficult to be ensured. It is common practice to operate the output side (primary side) of the second dc power Vout0 in a Forced Continuous Conduction Mode (FCCM), but the forced continuous conduction mode is inefficient at light load and is not suitable for all operating scenarios.
Referring to fig. 5 and fig. 6, which are a schematic diagram of a logic control of a switching tube circuit and a schematic diagram of a waveform of a switching tube control signal in an embodiment respectively, after initialization of the multi-output synchronous buck converter IS completed, if there IS no error, the switch trigger signal HSD _ ON triggers conduction of the upper switching tube Q1, at this time, the secondary diode D1 of each secondary output subunit 230 ON the isolation side IS in an off state, the secondary inductor current IS1 of the secondary output subunit 230 ON the isolation side IS 0, and the output current of the secondary output subunit 230 ON the isolation side IS provided by the secondary output capacitor C1. On the non-isolation side, a first direct current Vin and a second direct current Vout0 are superposed to two ends of a primary side inductor L0, and the current of the inductor rises linearly; after the dead time is over (the upper switch tube Q1 and the lower switch tube Q2 are both turned OFF), the lower switch tube Q2 is opened, the inductive current freewheels through the lower switch tube Q2, and the secondary side diode D1 of the isolation side secondary side output subunit 230 is in a positive-going conducting state to supplement charges for the secondary side output capacitor C1 of the isolation side secondary side output subunit 230; the primary side inductive current IP IS equal to the sum of each secondary side inductive current IS1 multiplied by the turn ratio coefficient of the transformer and the primary side exciting current; in this process, the inductor current is in a forced conduction state, which is called forced current continuous conduction mode (FCCM); in this mode, the charge on each isolation-side secondary output capacitor C1 is replenished during the on period of the lower switch Q2, and the output voltage of the isolation-side secondary output subunit 230 is substantially stable.
In an embodiment of the present application, the multi-output synchronous buck converter operates in a hybrid control mode (FCCM + DCM) under light load, so that efficiency reduction under light load is solved, and good load regulation on the output of the isolation side is achieved.
Referring to fig. 7, which is a logic control diagram of a switching tube circuit in another embodiment, the top tube driving signal HG includes a top tube on level signal and a top tube off level signal, the top switching tube Q1 is turned on when the top tube driving signal HG is kept at the top tube on level signal, and the top switching tube Q1 is turned off when the top tube driving signal HG is kept at the top tube off level signal; the lower tube driving signal LG comprises a lower tube on level signal and a lower tube off level signal, the lower switch tube Q2 is switched on when the lower tube driving signal LG is kept at the lower tube on level signal, and the lower switch tube Q2 is switched off when the lower tube driving signal LG is kept at the lower tube off level signal. At any moment, when the upper tube driving signal HG is an upper tube conduction level signal, the lower tube driving signal LG cannot be a lower tube conduction level signal, so that the upper switch tube Q1 and the lower switch tube Q2 cannot be conducted simultaneously. In every signal cycle T, the upper tube drive signal HG includes continuous upper tube conduction duration and continuous upper tube closing time, and the upper tube drive signal HG keeps being the upper tube conduction level signal when the upper tube conduction duration, and the upper tube drive signal HG keeps being the upper tube closing level signal when the upper tube closing duration. In the signal period T, the lower tube driving signal LG includes a first lower tube on duration and a second lower tube on duration which are consecutive, and the lower tube driving signal LG is maintained as a lower tube on level signal during the first lower tube on duration and the second lower tube on duration. In the signal period T, the upper tube conduction duration and the first lower tube conduction duration are consecutive in time, and when the upper tube driving signal HG is in the upper tube conduction duration and the lower tube driving signal LG is in the first lower tube conduction duration, the direction of the current output by the primary side output subunit is the first direction. When the down tube driving signal LG is conducted for a continuous time period at a second down tube, the direction of the current output by the primary side output subunit is a second direction, and the first direction is opposite to the second direction.
In one embodiment, the second lower tube conduction duration and the upper tube conduction duration are consecutive in time and precede the upper tube conduction duration.
In one embodiment, the second downcomer conduction time period is temporally continuous with and subsequent to the first downcomer conduction time period.
In one embodiment, the second lower tube on duration is temporally discontinuous from the first lower tube on duration and the upper tube on duration between the first lower tube on duration and the upper tube on duration.
In the above embodiment, in order to implement the logic control of the switching tube circuit, a variable k may be input through an external pin input or a built-in control manner, where the input variable k may be an analog input quantity or a digital input quantity, the controller may operate in an FCCM mode, a PFM mode, or a CCM + DCM mixed mode (frequency is higher than a certain value), and when the multifunctional input variable k is used as the mixed operation mode, the switching period of the controller is set to be shorter than T. The method is realized by additionally turning on the lower switch tube Q2 for a period of time for a controller operating in Discontinuous Current Mode (DCM), and the method for setting the additional on-time includes:
1) When the lower switching tube Q2 is conducted, the current of the primary side output subunit on the non-isolation side is conducted for a period of time t after zero crossing;
referring to fig. 8, a logic control diagram of a switching tube circuit according to a first additional on-time setting manner in an embodiment of the invention is shown, where the logic control diagram of the switching tube circuit can achieve that a second lower tube on duration and a first lower tube on duration are continuous in time and are subsequent to the first lower tube on duration.
2) The upper switching tube Q1 and the lower switching tube Q2 are both switched off for a period of time t additionally;
referring to fig. 9, a switching tube circuit logic control diagram of a second additional on-time setting manner in an embodiment is shown, where the switching tube circuit logic control diagram can implement that the second lower tube on duration time period is not continuous in time with the first lower tube on duration time period and the upper tube on duration time period, and is between the first lower tube on duration time period and the upper tube on duration time period.
3) Before the lower switch tube Q2 is turned on, it is additionally turned on for a period of time t.
Referring to fig. 10, a switching tube circuit logic control diagram of a third additional on-time setting manner in an embodiment is shown, where the switching tube circuit logic control diagram can realize that the second lower tube on duration and the upper tube on duration are continuous in time and before the upper tube on duration.
In the above three extra conduction periods of the lower switching tube Q2, the flow direction of the inductor current of the primary side output subunit on the non-isolation side is the direction (second direction) from the second direct current Vout to the switching tube circuit, and the rectifier diode (secondary side diode D1) of the secondary side output subunit on the isolation side is in the forward conduction state to supplement the charge to the output capacitor (secondary side output capacitor C1), so as to keep the output voltage stable. When the lower switch tube Q2 is turned off, the inductive current of the primary side output subunit on the non-isolation side cannot change suddenly, and continues to flow current by turning on the body diode of the upper switch tube Q1 or the upper switch tube Q1, and the rectifier diode of the secondary side output subunit on the isolation side is continuously in a forward conduction state to supplement charges for respective output capacitors. In this embodiment, by adjusting the input variable k, the longest switching period of the controller is always smaller than a value T0, so as to ensure that the voltage output by the secondary output subunit on each isolation side is within a required range. And the duration t of the second lower tube conduction duration period is related to the capacity value of the capacitor in the primary side output subunit.
Referring to fig. 11, a flow chart of a converter control method in an embodiment is shown, and in an embodiment of the present application, a converter control method applied to the multi-output synchronous buck converter is further disclosed, the control method includes:
and step 1000, adopting FCCM working mode control.
And in a control period T of the switching tube circuit, the switching tube circuit is controlled in an FCCM (flash control cm) working mode, so that the direction of the current output by the primary side output subunit is a first direction.
And step 2000, adopting DCM working mode control.
In the control period T, when the upper switching tube Q1 and the lower switching tube Q2 of the switching tube circuit are both cut off, the switching tube circuit is controlled in a DCM working mode, so that the direction of the current output by the primary side output subunit is a second direction, wherein the directions of the first direction and the second direction are opposite.
In one embodiment, the DCM operation mode is set before or after the FCCM operation mode in each control period T.
The converter control method disclosed by the application is characterized in that in a control period T of the multi-output synchronous buck converter, the switching tube circuit is controlled in an FCCM (frequency control modulation) working mode, and when the switching tubes of the switching tube circuit of the multi-output synchronous buck converter are all cut off in the control period T, the multi-output synchronous buck converter is controlled in a DCM (discontinuous conduction mode) working mode, wherein the directions of output currents of primary side output subunits of the multi-output synchronous buck converter are opposite to each other during FCCM (frequency control modulation) working mode control and DCM working mode control. Because the multi-output synchronous buck converter is controlled by adopting two working modes of FCCM and DCM in a control period T, the technical problem that the conversion efficiency of the multi-output synchronous buck converter is reduced when the multi-output synchronous buck converter is in light load is solved, and the output of an isolation side can have good load regulation rate.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (7)
1. A multi-output synchronous buck converter is characterized by comprising a loop control logic output circuit and an isolation multi-output synchronous buck circuit;
the loop control logic output circuit is used for sending an upper tube driving signal HG and a lower tube driving signal LG to a switching tube circuit in the isolated multi-output synchronous buck circuit so as to realize the switching control of a power switching tube of the switching tube circuit;
the isolated multi-output synchronous voltage reduction circuit also comprises a primary side output subunit and n secondary side output subunits, wherein n is a natural number; the switching tube circuit comprises an upper switching tube Q1 and a lower switching tube Q2; the switching control electrodes of the upper switching tube Q1 and the lower switching tube Q2 respectively respond to the upper tube driving signal HG and the lower tube driving signal LG to realize switching control so as to output the electric energy of the first direct current Vin to the primary side output subunit and each secondary side output subunit;
the primary side output subunit is used for converting the electric energy output to the primary side output subunit by the switching tube circuit into a second direct current Vout0 and outputting the second direct current Vout 0;
each secondary output subunit is used for converting the electric energy output to the secondary output subunit by the switching tube circuit into a third direct current Vout1 and outputting the third direct current Vout 1;
the upper tube driving signal HG comprises an upper tube conduction level signal and an upper tube closing level signal, the upper switch tube Q1 is turned on when the upper tube driving signal HG is kept at the upper tube conduction level signal, and the upper switch tube Q1 is turned off when the upper tube driving signal HG is kept at the upper tube closing level signal;
the lower tube driving signal LG comprises a lower tube on level signal and a lower tube off level signal, the lower switch tube Q2 is turned on when the lower tube driving signal LG is maintained at the lower tube on level signal, and the lower switch tube Q2 is turned off when the lower tube driving signal LG is maintained at the lower tube off level signal;
at any time, when the upper tube driving signal HG is the upper tube conducting level signal, the lower tube driving signal LG cannot be the lower tube conducting level signal, so as to ensure that the upper switch tube Q1 and the lower switch tube Q2 cannot be simultaneously conducted;
in each signal period T, the upper tube driving signal HG includes a continuous upper tube on duration period and a continuous upper tube off duration period, the upper tube driving signal HG is kept as an upper tube on level signal in the upper tube on duration period, and the upper tube driving signal HG is kept as an upper tube off level signal in the upper tube off duration period;
within the signal period T, the down tube driving signal LG comprises a first and a second consecutive down tube on duration, and the down tube driving signal LG remains as a down tube on level signal during the first and the second down tube on duration;
in the signal period T, the upper tube on duration and the first lower tube on duration are consecutive in time, and when the upper tube driving signal HG is in the upper tube on duration and the lower tube driving signal LG is in the first lower tube on duration, the direction of the output current of the primary side output subunit is a first direction; when the lower tube driving signal LG is conducted for a second lower tube lasting time period, the direction of the current output by the primary side output subunit is a second direction, and the directions of the first direction and the second direction are opposite;
the loop control logic output circuit comprises an On-Time generating circuit, a feedback signal acquiring circuit, a switch trigger signal generating circuit and a control signal output circuit;
the On-Time generating circuit is connected with the control signal output circuit and is used for generating a switching tube driving signal HSD _ OFF to the control signal output circuit;
the feedback signal acquisition circuit is respectively connected with the primary side output subunit and the switch trigger signal generation circuit, and is used for sampling a second direct current Vout0 output by the primary side output subunit and outputting a feedback signal obtained by sampling to the switch trigger signal generation circuit;
the switch trigger signal generating circuit is connected with the control signal output circuit and is used for outputting a switch trigger signal HSD _ ON to the control signal output circuit according to the feedback signal;
the control signal output circuit is used for sending the upper tube driving signal HG and the lower tube driving signal LG to the switching tube circuit according to the switching tube driving signal HSD _ OF and the switching trigger signal HSD _ ON.
2. The multi-output synchronous buck converter of claim 1, wherein the second down tube conduction duration is temporally consecutive to and precedes the top tube conduction duration.
3. The multi-output synchronous buck converter of claim 1, wherein the second down tube conduction duration is temporally continuous with and subsequent to the first down tube conduction duration.
4. The multi-output synchronous buck converter of claim 1, wherein the second down tube conduction duration is temporally discontinuous from both the first down tube conduction duration and the up tube conduction duration, and between the first down tube conduction duration and the up tube conduction duration.
5. The multi-output synchronous buck converter according to claim 1, wherein a duration t of the second down tube conduction duration is related to a capacitance value of a capacitor in the primary side output subunit.
6. The multi-output synchronous buck converter according to claim 1, wherein the switch trigger signal generating circuit includes a ripple generating circuit, an error amplifier, a comparator and a ramp generating circuit;
the error amplifier is connected with the feedback signal acquisition circuit and is used for amplifying the feedback signal;
the ripple generating circuit is used for generating a ripple signal;
the ramp generating circuit is used for generating a ramp signal;
the comparator is used for comparing a signal synthesized by the ripple signal and the feedback signal with a signal synthesized by the ramp signal and the amplified feedback signal, and sending a comparison result signal obtained by comparison to the control signal output circuit as the switch trigger signal HSD _ ON.
7. The multi-output synchronous buck converter according to claim 1, wherein the feedback signal acquisition circuit includes a sampling input, a sampling output, a first resistor R1 and a second resistor R2;
the sampling input end is connected with the primary side output subunit and is used for inputting the second direct current Vout 0;
the sampling output end is connected with the switch trigger signal generating circuit and used for outputting the feedback signal to the switch trigger signal generating circuit;
one end of the first resistor R1 is connected with the sampling input end, and the other end of the first resistor R1 is connected with the sampling output end;
and one end of the second resistor R2 is connected with the sampling output end, and the other end of the second resistor R2 is grounded.
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| CN102723856B (en) * | 2012-07-02 | 2014-06-25 | 矽力杰半导体技术(杭州)有限公司 | Synchronous rectifier control circuit and switch power supply employing same |
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