WO2008047374A2 - Switched resonant-tank, cell based power converter - Google Patents

Abstract

A DC to DC converter comprising building blocks removably connected to each other. Each block includes generic power-processing witching means with means for connecting their energy storage (51) elements in series or in parallel. The energy storage (51) elements each comprises a capacitor or a capacitor in series with an inductor. Each block includes generic power-processing switching means with means for connecting their energy storage elements (51) in series or in parallel, wherein the switching means comprise three power switches and the energy storage elements each comprise a capacitor. It includes control means for initiating a series connection for a time period of a series stroke wherein the storage elements are connected in series, or a parallel connection for a time period of a parallel stroke wherein the storage elements(51) are connected in parallel.

Description

Switched Resonant-Tank, Cell Based Power Converter

Cross-Reference to Related Applications

The present application is related to, and claims priority from, the provisional patent application US 60/862,243 filed on October 20, 2006 in U.S.A. by the present applicant and entitled "Switched Resonant-Tank, Cell Based Power Converter".

The present application is also related to, and claims priority from, the provisional patent application US 60/973,029 filed on September 17, 2007 in U.S.A. by the present applicant and entitled "Switched Resonant-Tank, Cell Based Power Converter and its Extensions".

Field of the Invention

This invention relates to switched DC to DC converters, and more particularly to a high efficiency, modular, switched resonant tank, cell-based power converter.

Background of the Invention

The invented converter is a power electronics system or converter, which belongs to the DC to DC converters family. Implementations may include low power, medium and high power applications, fuel-cell power converters for commercial applications, low voltage sources interface to electronics, step-up or step-down converters, Charger applications, Point Of Load (POL) energy conversion methods, etc. It also relates to Application Specific Integrated Circuits (ASIC) and low voltage analog electronics.

Stepping up or stepping down a voltage or current with high conversion ratios is known to be a challenge, especially where no transformers are used for this purpose and efficiency must be kept high at large conversion ratios. Good examples for such cases are voltage boosting of a micro fuel-cell, a solar cell or a single cell battery from its low terminal voltage (0.3 V to 1.5 V) to voltage levels typically used in electronic circuits or to charge a higher-voltage battery (3.3V-12V etc.). Another typical application is the power supply and regulation for a high performance micro-processor where a 10- 12V power source is stepped-down to feed the processor core at IV or less. For these and many other applications - maintaining the highest possible efficiency is a primary concern. High efficiency combined with high conversion ratio is important in many other applications, like lighting apparatus, welding apparatus and more.

Low voltage sources or load conversion are particularly problematic, as in order to supply them with even moderate powers, high current levels are required at the low voltage port of the converter. Therefore - ohmic losses, which are related to the square of the current involved, are a major factor in the overall losses of the converter and system.

Even for low powers of 1 - 2W at 0.3 - 0.5V, in order to achieve moderate efficiency, the total resistance in the power path of the converter at the low voltage side should not exceed an order of a few milli-ohms. Even when using advanced power electronic discrete components, achieving these low resistances is a challenge. More so for a converter integrated in an ASIC, where the actual transistor resistances is only one of a series of factors affecting the total resistance such as bond and internal metal conductor resistances, terminals resistance, and so on. The high currents within the ASIC are extremely problematic as they may lead to electro-migration sensitivity of the design, soldering and bonding problems, and combined with the resistances - to hot spots. Externally to the chip, more problems due to the high currents manifest themselves in the soldering quality and area, reliability issues, etc.

In prior art power conversion topologies used for similar cases, like the BOOST or BUCK topology, etc., some of the power elements must deal with both high voltage and high currents. This leads to increased losses, both ohmic and switching. Moreover, most of today's converter technologies suitable for high-conversion ratio and/or conversion of low voltage sources or loads are unidirectional, meaning that the direction of power flow is from the source to the load only. Therefore - prior conversion technologies are less suitable for operation with 5 renewable energy sources where the source supplies energy and is also recharged. For such cases - a bidirectional power flow feature is preferred.

Prior art converters for low-voltage conversion are usually not modular in nature. Therefore - the flexibility of these prior art converters is low and iO expandability may not be achieved. The known topologies may not readily be expanded to form a single-input multi-output converters or multi-input single-output converter. Therefore - in systems where a few voltages are required, each voltage calls for a separate converter or the compromising of other design goals in order to provide several outputs (for instance - using a

[ 5 Flyback transformer with multiple windings to produce several voltages while compromising efficiency and compactness).

Finally, known (prior-art) technologies for low- voltage conversion usually require either large inductors and/or large high quality capacitors (with very JO low ESR). Using such components in the converter calls for higher volume, more losses, degraded efficiency (due to inductors saturation) and/or higher cost (due to high-end capacitors prices).

J5 Summary of the Invention

The present disclosure relates to improvements in switched DC to DC converters. The new converter may achieve a higher efficiency and has a modular structure. It uses a switched resonant tank, cell-based power iO converter structure system and method.

The new converter was devised with the goal of addressing and solving prior art performance and design-related problems as detailed above.

The converter includes various innovative aspects, including among others: A. Innovative aspects of the new converter system and method

B. Innovative aspects of Power converter topologies

C. Innovative aspects of Power Switch Control methods

D. Innovative aspects of System-Level Control loop system and method.

The benefits of the novel system and method include, inter alia:

High efficiency capability for low voltage conversion; It may achieve even an efficiency above 90%.

Splitting the low voltage side current into smaller, more manageable currents, at the PCB/Interconnect level of the converter implementation.

A Modular approach, suitable for discrete parts and/or ASIC implementation

The ASIC and/or power electronics components do not have to deal with the high currents of the low- voltage side of the converter. Rather, the power components and ASIC must deal only with the lower, split current. - New methods of control algorithms suitable for the operation of the disclosed invention. The disclosed topology and control are designed to support Zero Current Switching (ZCS) and/or Zero Voltage Switching (ZVS) for to reduce losses and increase efficiency and reliability.

A design which enables the use of lower cost components. - Wide range of Power handling capability, from sub-watt to hundreds of watts.

Regulation capability for the various system signals like output voltage, input voltage, etc., and regulation control algorithms/methods.

The new design may be able to support recycling of the gate energy for its power switching elements, where applicable and beneficial (like in the case of a IW or sub-Watt converter).

Bidirectional power flow, and/or multi-input multi-output capabilities.

Capability of immediate load or source disconnect, inherently built into the network.

Capability for use of multiple instances of the network in interleaving in order to achieve reduced input current ripple, reduced output current ripple, improve the network's dynamics, etc., similar with the benefits achievable by interleaving customary, prior-art Buck or Boost converters.

Capability of ground-separation between the source and load circuits. Such separation is needed in order to open ground loops, in various applications, for example where low frequency noise is a performance issue.

The new step-up and step-down DC to DC power converter and control scheme can achieve excellent power conversion efficiency, in some instances more than 90% . High efficiency may be maintained even for high voltage-conversion ratios.

The new converter is suitable, among other uses, for stepping up power sources with very low output/terminal voltage levels to a more useful voltage level, or conversely - to step down a high input voltage to a useful lower voltage level.

In cases where the power source is of very low terminal voltage, a power converter must deal with quite high currents even when drawing low power from the source.

The new converter is unique in its ability to handle these large currents efficiently. The disclosed power conversion technology can divide the large source current among several conversion cells, thus reducing the stress on each individual cell; each cell now has to deal with only a fraction of the source current. Similarly - for the step-down converter, the load current is divided evenly between the converters cells, and each cell must deal only with a fraction of the total load current.

The new converter allows for a bidirectional power flow, from source to load and vice versa (the converter can source or sink current at both its input and output). Additionally, the load and source terminals of the disclosed converter are interchangeable, and may be swapped. In such case - step up operation will change to step down operation. Natural ASIC implementation exists for the disclosed converter.

The new converter can be implemented using a combinations of disclosed basic series resonant cells. Each cell is made of power switches and a series, L-C resonant tank. The inductive part of thereof may be based on independent inductors or coupled inductors (with or without a mutual magnetic core). The inductors of the various cells may also be lumped into a single input and single output inductors, thus realizing different optimization goals. Each cell may have its own controller to operate its power switches, or a plurality of cells may share a single controller. At each switching interval the basic cells rearrange their connections with other basic cells - thus achieving the desired conversion ratio. A new method and algorithm performs automatic switching timing for the cells. When the algorithm goal is reached - zero current switching is achieved on all power switches of each cell. Zero voltage switching is also possible, using one embodiment or a variation of the technology. 5

Many combinations of the basic cells are possible, each achieving different rational conversion ratios, or other desirable goals, as detailed below.

Because of the modular approach of the new converter, tailoring a solution for specific .0 power conversion problems is easier. For instance - using 2-3 basic cells in a series- parallel configuration step-up converter may be ideal for boosting a single fuel-cell terminal voltage to a level high enough for consumer applications electronics. Using 8-9 basic cells in a series-parallel configuration step-down converter may be beneficial for Point Of Load (POL) conversion, targeting microprocessor systems. [5

The new technology may be combined with control loops, the combined system can perform regulation, stabilization or tracking of a desired signal.

The new converter structure is capable of fully utilizing an adiabatic gate .0 drive for the power switching elements; it is attractive for ASIC or discrete implementations. Utilizing this switch-driving technique recovers most of the gate drive energy to achieve increased efficiency. In some cases, however, adiabatic gate drive is not required or goes against other system-level goals. In these cases, the optional adiabatic gate drive can be omitted. 15

Typical ASIC implementation of the new converter includes several basic cells electronics, control algorithm electronics and gate drivers for each cell's power switches. The required power switches and/or resonant tanks may be implemented on or off the packaged chip. The inductors of the resonant 50 tanks may be lumped into input and output inductors, or connected at each cell. Several ASICs may be operated in unison to produce a larger converter. The new converter may be used in an interleaving mode, similarly to what is been done in prior art Interleaved Boost or Interleaved Buck converters. The same benefits achieved by interleaving for the prior art can also be achieved in the disclosed invention.

5 The new converter can support ground separation, a feature needed from the power supply in many applications.

Further objects, advantages and other features of the present invention will become obvious to those skilled in the art upon reading the disclosure 0 set forth herein.

Brief Description of the Drawings

5 Fig. 1 illustrates a simplified, top level block diagram of the new converter.

Fig. 2 illustrates a simplified, top level block diagram of the converter with full-wave rectification and an auxiliary input support.

,0 Fig. 3 shows a schematic of a converter embodiment having a single input and a single output.

Fig. 4 presents known solutions for the characteristic R-L-C series resonance circuit current waveform, for various Q values. :5

Fig. 5 presents characteristic waveforms measured at various test points of the disclosed topology.

Fig. 6 shows an implementation of the SPST power switches and power switch driver.

Fig. 7 discloses a converter having a single input and multiple outputs.

Fig. 8 discloses a third variant of the converter, with two networks working in parallel and anti-phase and intermediate storage capacitors. Fig. 9 presents a low-cost converter with a single input inductor and a single output inductor.

5 Fig. 10 discloses a preferred method of stroke timing used to control the power switches.

Fig. 11 presents characteristic waveforms measured at various test points of the disclosed topology.

0 Fig. 12 discloses a preferred method of stroke timing used to control the power switches.

Fig. 13 discloses a subsystem connected at the N+l outputs of the invented converter topologies 2 and 3 for coarse regulation of the output voltage.

5 Fig. 14 discloses a subsystem connected at the N+l outputs of the invented converter topologies 2 and 3 for fine regulation of the output voltage.

Fig. 15 discloses a preferred implementation of the coarse regulation method used for coarse output voltage regulation. ;0

Fig. 16 shows typical regulation results for the coarse voltage regulation scheme of Fig. 15.

Fig. 17 discloses a preferred implementation of the fine output voltage '.5 regulation, which includes a power routing network.

Fig. 18 discloses the internal connections of the two routing networks, the m:l and m:2 routing networks, used for regulation.

iO Fig. 19 presents a typical usage of variant 4 of the invention as Step-Up converter, utilizing two converter networks operated in parallel and anti-phase.

Fig. 20 presents characteristic waveforms measured at various test points of the disclosed topology of Fig. 19. Fig. 21 presents a typical usage of variant 4 of the disclosed invention working as a Step-Down converter, utilizing two converter networks operated in parallel

, and anti-phase.

5

Fig. 22 presents typical waveforms measured at various test points of the disclosed topology in the 4th variant operating in parallel and anti-phase Step-Down and with high value of Q in the charging path.

[0 Fig. 23 presents typical waveforms measured at various test points of the topology in the 4th variant operating in parallel and anti-phase and with low value of Q in the charging path.

Fig. 24 presents the utilization of the 4th variant of the disclosed 15 invention topology with an Auxiliary connection, useful for voltage tuning.

Fig. 25 presents the utilization of the 4th variant of the disclosed invention topology with an Auxiliary connection, useful for voltage tuning.

JO Fig. 26 presents the range of gains achievable using the fine-tuning AUX input.

Fig. 27 presents a topology with Fine voltage regulation and a control loop for performing output voltage regulation.

£5 Fig. 28 presents the waveforms sampled by the CDS module incorporated into the control loop of Fig. 27, when the Capacitors voltage sampling is done on the output side of the Step-Up converter described in Fig. 27.

Fig. 29 presents the waveforms sampled by the CDS module incorporated into 50 the control loop of Fig. 27, when the Capacitors voltage sampling is done on the input side of the Step-Up converter described in Fig. 27.

Fig. 30 details typical implementations of the tuning networks used in Figs. 27 and 31. Fig. 31 presents the Step-Down variant of topology Fig. 27 with Fine voltage regulation and control loop.

Fig. 32 illustrates Ground Separation using the 4th variant of the new 5 converter topology having an AUX input in the Step-Up configuration.

Fig. 33 shows an Example of interleaving of the basic converter.

Fig. 34 illustrates Interleaving: Start signals instructing each interleaved 0 converter to start a charge stroke, and the resulting current waveforms in Network A and Network B of each interleaved converter.

Fig. 35 discloses a control scheme for generating Switch-control pulses (Φi-j) to use with the converter. 5

Fig. 36 presents an example of a Step-Down configuration including the control circuitry required for converter's operation.

Fig. 37 presents three implementations of the power switches gate drivers, in a :0 structure and method that recycles the gate energy.

Fig. 38 presents another option which provides both fine-tuning and coarse-tuning of the output voltage.

^•5

Detailed Description of the Preferred Embodiments

A preferred embodiment of the present invention will now be described by way of example and with reference to the accompanying drawings. i0

Glossary of terms

DC - direct current

PID - proportional, integral and differential [control method] PWM - pulse width modulation RMS - root mean square ZCS - zero current switching ZVS - zero voltage switching

Notes:

1. The power switches described in the patent may or may not include anti-parallel diodes. The switch symbol we have used includes a diode but this is not mandatory; rather, other solid state switch means may be used . Power switches that do not include diodes are also possible and are part of the present disclosure.

2. The various embodiments presented may include the application of negative voltages at the AUX input or at the in/out terminals.

Following is a summary description of innovative aspects of the present invention (A-D) which are further detailed elsewhere in the present disclosure.

A. Innovative aspects of the new converter system and method

1. The new converter comprises simple building blocks, which are the cells. If the cells do not include an inductor, then two inductors are available at the input and output terminals of the entire converter.

5 The cells are generic power-processing switching molecules. The cells allow series or parallel connection of their energy storage elements (i.e. capacitor or capacitor+inductor). The time interval for a connection is called a stroke. Thus, the system alternatively activates a parallel stroke and a series stroke. The invention is a switch-mode power converter.

)

2. Optionally, there may also be a dead time between the strokes. This dead-time may offer various advantages, for example:

a. Allocating sufficient time to perform the switching commands in a sequence that enables performing ZVS or ZCS for all switches of the converter.

b. Allocating sufficient time for adiabatic/energy recycling gate drive, where applicable (especially important for handheld, low power converters).

c. Allocating sufficient time for Soft-switching to take place for the power switches of the converter.

3. A chain comprising basic cells in the manner described in the present application allows shifting between series-stroke and parallel-stroke of the energy storage elements

4. The transition from series-stroke to parallel-stroke or vice versa is done in such a manner as to minimize losses during the transition.

5. The newly introduced inductors comprise an improvement over prior art switched-capacitor converters. Such prior art converters could not achieve the minimization capabilities of the present invention, unless maybe the capacitors chosen are very big, and operating with very low voltage ripple on the capacitors.

6. The series and parallel strokes: a. When the capacitors are connected to the energy source (in series or in parallel) this may also be called the Charge stroke

b. When the capacitors are connected to the load (in series or in parallel) this may also be called the Discharge stroke

c. Important: It is desirable to have a charge stroke and discharge stroke which take nearly the same time. Prior art configurations cannot do that and therefore their current waveform RMS/ Average ratio is bad. In the disclosed invention, this is not the case, since the invention permits having a charge stroke similar in its duration to the discharge stroke.

7. Unlike prior art systems, our invention works with: a. Low voltage ripple on the inductances of the converter. This causes a lower volt-second product and allows operating with smaller inductances, a big advantage. b. The resonance frequency of the invented converters' reactive elements (capacitors and inductances) can be chosen to be close to the stroke-switching rate. This makes the natural dynamics of the invented converter much faster with respect to the prior art. 5 c. In order to operate properly, the values of Q required from the R-L-C equivalents (of the networks' capacitors switch resistances and inductances) can be quite low. Because this is the case - the new converter may use the natural power-switches resistance for most of the needed damping, without relaying on 0 the load, damping network or global feedback for external damping.

8. The input and/or output terminals of the converter can both source or sink power, thus having a bidirectional power flow. The series-stroke or parallel- stroke of cells is capable of both sourcing and sinking power.

5

9. The energy conversion in the converter is mainly done by switching the capacitors connection while the inductors serve to solve the problems and shortcomings found in (state of the art) switched-capacitor converters.

:0 10. Unlike in prior-art, where the same two terminals are used to access the series- and parallel-connection of capacitors, the new converter has two terminals connecting the series-connection to the outside (via an additional power switch) and two other terminals connecting the parallel-connection to the outside. Therefore - we may have differential access to the series and parallel connections of basic cells. This way we may separate the

'.5 high current path (associated with the parallel connection) and the low current path

(associated with the series connection) inherently, and without additional power switches. This resembles a DC-capable transformer that has two separate sets of terminals. We may also connect one terminal of the input and one terminal of the output and have a structure resembling an auto-transformer.

10

11. Important: our technology separates the high current associated with the low voltage side of the converter from the lower (by the reciprocal of the conversion gain) current associated with the high voltage side of the converter. 12. Important: One of the terminals of the series-connection may be used as an Auxiliary connection (AUX), thus enabling power-efficient fine tuning of the conversion ratio of the network. Without an Aux input, the conversion ratio is an integer. The Aux input allows a non-integer conversion ratio AND to maintain higher overall converter

5 efficiency. Prior art systems (linear regulation, frequency change, etc.) cannot achieve such tuning in an efficient manner .

13. Important: Applying a tunable voltage source at the Aux terminal allows for continuous conversion ratio tuning. The power drawn from the voltage source is low,

0 compared to the output powers drawn from the converter. This tuning ability may be used by an external control loop to achieve a control goal (like output voltage regulation).

14. Novel features in the present disclosure: a. Inductance or inductors specially chosen for the series-stroke or the 5 parallel-stroke. Each stroke is done through an equivalent R-L-C network, which we specifically design its Q and ω₀. The R-L-C network selection for the 1^st and 2^nd strokes may be different. Our innovation is the option to have same or separate selection of Q, ω₀ for the series- and parallel-strokes.

10 b. The inductance selection allows to have special current waveform shaping with current waveform zero crossings (high Q, ω_o close to the stroke repetition rate)

c. The inductance selection allows to have special current waveform shaping with current waveform decay (low Q, ω₀ close to the stroke repetition rate)

15. Novel features may achieve the following advantages, which are related to the novel topologies:

a. Almost Zero-power switching. Each stroke can operate under zero-current or »0 zero-voltage switching.

b. In the series-stroke - one switch may have ZVS and the rest - may switch at ZCS (when current handover is applied between two networks) c. In the parallel-stroke - one set of switches may have ZCS and the second set of switches - may switch at ZVS (when switching at the zero-crossings of the stroke current)

d. In the series-stroke - all switches may have ZCS (when switching at the 5 zero-crossings of the stroke current)

e. In the parallel-stroke - one set of switches may have ZVS and the second set of switches - may switch at ZCS (when current handover is applied between two networks)

0 f. In the series-stroke - all switches may have ZVS (when switching at the zero-crossings of the stroke voltage).

g. In the parallel-stroke - one set of switches may have ZCS and the second set of switches - may switch at ZCS (when current handover is applied between two networks) 5

16. The power switches of the invented converter may operate using a new controller. This controller times the switching commands, controlling all the power switches in an innovative manner: a. Predetermined timing of the switches programmed by the designer, implemented ;0 (for example) by an external oscillator and counter, and a logic device.

b. A control loop which, through inspection of the stroke current (directly or indirectly), estimates the timing for switching the power elements.

,5 c. A control loop which combines oscillator and current inspection or measurement in order to control the power switches of the converter switching instances.

17. Important: operation of two basic networks of cells in parallel and in anti-phase. This may give, for example, the following advantages:

0 a. During the time one of the two networks is connected to the input port, the other network is connected to the output port.

b. Control of the input port or output port current ripple, reducing it to almost zero. This is done through:

1) Using a common inductor for the two networks operating in parallel and anti-phase and selecting it to have ω₀ much lower than the stroke repetition rate), and

2) Fast current-switching (handover) between the two networks. 5 c. There can be a current-handover behavior for one port (two terminals) and zero-current switching for the other port (two terminals). For example - the charge-stroke may be done with zero-current switching while the discharge-stroke may be done through current-switching (handover between the networks operating in parallel and anti-phase).

0 d. There can be current-handover behavior for both ports (input and output).

e. There can be zero-current switching behavior for both ports (input and output).

5 f. If each of the networks working in parallel and anti-phase has an AUX input, both AUX inputs may be connected together. Like in the case of a single network, the AUX input may be used for non-integer conversion gain tuning and/or regulation input.

18. Important: The duration of the two strokes may be identical or - two O strokes of different durations may be used, in order to trade-off silicon

(power switch) area and other converter parameters (frequency, complexity, average to RMS current ratio etc.). In order to do so - the timing controller may require adjustments. This can effect the selection of Q and ω₀ for each stroke.

'.5 19. Like for Boost or Buck regulators, interleaving (multiphase) is possible for the new converter, where the basic converter interleaved is a single network or the two networks operating in parallel and anti-phase. Interleaving is a new feature in our topology.

20. Innovation: our new topologies with input-output isolation. !0

21. Innovation: dynamically changing the number of series-connected basic cells in order to select different gains (N+ 1, N₅N-I,...) during converter operation.

This can be used for coarse-gain tuning. 22. Innovation: using coarse gain tuning alone or using coarse-gain tuning and fine-tuning together, in the same implementation of the converter.

23. The input and outputs may be voltages that are slowly varying.

a. If the input is slowly varying the output will also be slowly varying (if no additional regulation measures are taken), like in a transformer. Therefore - the invention may be treated as transformer capable of transferring DC with low current ripple at both sides.

b. If the input is slowly varying and the output is required to be fixed, regulation is needed through fine-regulation or coarse-regulation as disclosed.

24. Innovation: if the power elements are implemented without anti-parallel diodes - the converter may process AC input and produce AC output, i.e. - to operate as an AC to AC converter.

25. Innovative features relating to operation of the converter

a. The disclosed topologies usage as a DC to DC converter

b. The disclosed topologies usage as a charger for batteries, fed from a low voltage source

c. The disclosed topology operated with a fixed conversion gain while output voltage tuning is performed by tuning the input voltage to the disclosed topology.

d. Bidirectional energy flow, from input to output port and vice versa, for any implementation of the new converter. The direction of energy flow may be made to adapt itself to the external conditions imposed on the input and output ports.

B. Innovative aspects of Power converter topologies 1. Fig. 9 - using a basic cell comprising of 3 power switches and an energy storage element (capacitor), the basic cell has power switches allowing parallel or series connection between the cells. Two inductors may be used. One inductor is utilized when operating the cells in a parallel connection and

5 the other inductor is utilized when operating the cells in series connection. The inductor used for the parallel connection must deal with the current found at the Io w- voltage side of the converter. The inductor used for the series connection must deal with the much smaller current of the high- voltage side of the converter.

0

2. Major Innovative feature: Fig. 9 - two current paths exist - one for a high current associated with the low voltage side (Vs) and one for a low current associated with the high voltage side (Vo). Each current path has its own degree of freedom (through Ll or L2 tuning and switches resistance), therefore - the current waveforms of these two paths may

5 be shaped independently.

3. Fig. 9 is a step up example. The step down example is readily obtained by exchanging the source and load, plus the load capacitor locations.

0 4. Fig. 9 shows a bidirectional converter therefore each side may be sourcing or sinking power (i.e. function as a source or load). This is true for all other topologies as well.

5. Fig. 9 shows the input to the lower terminal of the series connection may be

;5 connected before (365) or after (364) the inductor Ll, thus including or excluding it in the series-connection current path.

6. Fig. 11 shows an example of the current waveform possible with the topology of Fig. 9, with Ll, L2 selection that causes current waveforms with zero crossings in the

O charge and discharge strokes.

7. Fig. 19 shows two networks of fig. 9 connected in parallel and operated in antiphase. This way - at any given time one network is feeding the load and one network is being charged from the source. 8. Fig. 20 shows the current waveforms possible with the topology of Fig. 19, and a selection of Ll₅ L2 that causes a current waveform with zero- crossings at the charge stroke, and current handover at the discharge stroke

5 (output side of the converter).

9. Fig. 20 shows the drawing, also discloses the power-switches control signals that end the charging stroke at the zero-current instance and the current-handover at the output side. This is done by specific switch-control signals Φl, Φ2 and Φ2-1, Φ2-2 with delays

0 between them. This may provide the advantage of ZVS and ZCS of the series connected power switches.

10. Fig. 21 shows a step down converter using two networks of fig. 9 operated in parallel and anti phase.

5

11. Fig. 22 shows the current waveforms possible with the topology of fig. 21, and a selection of Ll, L2 that causes a current waveform with zero- crossings at the charge stroke, and current handover at the discharge stroke (output side of the converter).

•0

12. Fig. 22 shows the drawing, also discloses the power-switches control signals that end the charging stroke at the zero-current instance and the current-handover at the output side. This is done by specific switch-control signals Φ1-1A, Φ1- 2A and Φl-1, Φl- 2 with delays between them. This may provide the advantage of ZVS and ZCS of the

^•5 series connected power switches.

13. Fig. 23 shows waveforms for the network of Fig. 21, with low Q charging stroke. This shows a novel feature of low Q strokes, for all power topologies. In the low Q case we present a special control feature too.

IO Other, prior art converters, cannot operate with low Q strokes in such manner. ZCS is usually performed with high Q in the prior art.

14. Fig. 24 describes one of our major Innovative features - the AUX input to the series-connection. It is important to recognize this feature for the step-up and the step-down variants of the converter.

15. Fig. 25 details the AUX input when using two networks operated in parallel and anti-phase.

5

16. Fig. 26 shows the resultant linear tuning of gain when using an input voltage between 0 and 2Vs (or less or more) at the AUX input.

17. Fig. 32 shows ground separation between the input and output of the 0 converter, for reasonable CM voltages, within the safe voltage range of the converters' power transistors.

18. Fig. 32 illustrates a differential input and differential output terminals from the converter.

5

19. Fig. 33 illustrates interleaving of implementations of the disclosed converter, where each implementation consists of two networks operating in parallel and anti-phase.

20. Fig. 33 also illustrates interleaving of implementations of the disclosed 0 converter, where each implementation consists of a single network only, for example - like the network of Fig. 9.

21. Fig. 33 shows the synchronization of disclosed converters while operating them in interleaving, using a Stroke synchronization system producing Start signals

:5 which initiate strokes.

22. Fig. 34 discloses typical waveforms of the interleaved converter of Fig. 33 and the Start control signals.

i0 23. Fig. 38 illustrates the ability to dynamically change the number of cells connected in series during converter operation in order to enable the use of power switches rated for lower voltages. This is useful, for example, when the low- side connected power supply voltage increases but the high-side voltage is required to remain fixed. The gain may be changed in order to provide that and this feature allows us to change gain and still have power switches rated for the lowest possible voltage and an unnecessary increase of transistor breakdown voltage overhead may be avoided.

5 24. Fig. 38 shows the ability to connect the output port at the output of the Nth¹ cell, (N-l)th¹ cell,..., etc. in order to provide high- efficiency coarse-regulation/tuning.

25. Fig. 38 shows how the converter connects all cells in parallel during

0 the parallel-connection stroke. For the series connection stroke - we present the possibility to connect only a smaller group of series-connected cells, thus obtaining lower conversion gain (controlling the gain in integer steps).

26. Fig. 6 presents the use of adiabatic gate drive in order to drive the 5 gates of the various power switches of the various disclosed converter implementations of this patent.

27. Fig. 37 presents several typical adiabatic gate drive methods. Another method presented illustrates how to hold the intermediate internal converter voltages

0 (capacitor voltages) in separate capacitors in order to create adiabatic gate drive signals using these capacitors.

28. Fig. 3 discloses the invented converter topology with the inductances appearing embedded in each cell. The inductances may be implemented using

,5 discrete or integrated magnetics (uncoupled or coupled).

29. Fig. 5 shows inductors' current and capacitors' voltage waveforms for the topology of Fig. 3, where Q is high and ω₀ is close to the stroke repetition rate.

0 30. Fig. 7 details the power converter topology with the basic cell indicated in the drawing, allowing multiple outputs or inputs (bidirectional ports) from the converter.

31. Fig. 8 details the extension of the topology of Fig. 7 to include two networks working in parallel and anti-phase.

32. Fig. 13 details means of regulating/controlling the output voltage using a routing network which selects one of the intermediate converter

5 voltages Vs₅ Voutl, ... Vout(n) according to a control rule (controller)

33. Fig. 14 details means for regulating/controlling the output voltage using a two-output routing network which selects two consecutive intermediate converter voltages from Vs, Voutl, ... Vout(n), and using PWM control between

0 these two voltages - regulates the output voltage of the converter.

34. Fig. 15 details coarse voltage regulation using the m: 1 routing network connecting the intermediate outputs Vs, Voutl, ... Vout(n) to a smoothing filter. The routing network is controlled via a control loop in a manner that 5 regulates the output voltage. Fig. 16 - presents typical waveforms possible with the topology of Fig. 15.

35. Fig. 17 details output voltage regulation implementation using a m:2 network and PWM control in order to provide fine-regulation of the output voltage. We also present the

:0 use of a PID controller (implemented via analog, digital or other means) in order to control the PWM modulator, and an up- down counter and comparators controlling the m:2 routing network. Other control means exist for the routing network and PWM switch. We present the use of them with our network connected at the ports of the m:2 network. We also present the use of the disable signal in order to disconnect the PWM power switch

'5 while the routing networks seeks the correct position through the adaptation of its control loop.

36. Fig. 18 presents the topologies of the routing networks as disclosed in this drawing. The power switches may be any power switching element with !0 bidirectional current flow and blocking capabilities.

C. Innovative aspects of Power Switch Control methods 1. Fig. 36 shows the automatic adjustment of the stroke time based on sensing the inductor current (equivalent to inductor energy) during the stroke, in order to achieve ZCS at the strokes' end.

5 2. Fig. 36 shows the control scheme detects the actual and specific rate at which ZCS conditions appear for strokes and tunes the strokes time intervals in order to achieve that rate.

3. Fig. 36 shows the operational cycle is of two strokes and an optional dead 0 time after each stroke, where the stroke time is determined automatically and the dead time may be selected.

4. Fig. 36 shows the first stroke in a bi-stroke cycle is initiated by the control scheme and ends according to zero inductor current/energy detection.

5 The second stroke time may be controlled in two major manners/methods of operation:

a. Mode 1 : The 2nd stroke may be initiated at the end of the dead time appearing after the 1st stroke and ended according to zero inductor current/energy detection.

:0 b. Mode 2: The 2nd stroke is initiated inside the dead time and through current handover between Network A and Network B.

5. Fig. 36 shows, at steady state, the control scheme creating self oscillations of !5 the system with a fixed stroke repetition rate.

6. Fig. 36 shows the control responding to inductor current zero crosses in any direction (positive to negative and negative to positive going current). Therefore - the control can handle bidirectional energy flow automatically.

IO

7. Fig. 36 shows a stroke startup mechanism ensuring that the converter will start the strokes sequence, at a predetermined initial rate. After startup - the current/energy sensing mechanism takes over. 8. Fig. 36 shows, in case current sensing fails (due to low load levels for example), the control folds back to the initial stroke repletion rate.

The control loop has a means for masking falsely detected zero-crossings, thus preventing premature stroke termination and undesired high-rate oscillations. 5

9. Fig. 36 shows a control loop having a means for masking falsely detected zero- crossings, thus preventing premature stroke termination and undesired high- rate oscillations.

0 10. Fig. 36 shows a logic unit incorporated in the control loop for generation of gating signals to all the power switches of the converter, with specific delays and dead times between each gating signal that ensure ZCS or ZVS for some or all the power switches of the converter.

5 11. Fig. 36 shows a logic unit incorporated in the control loop for generation of gating signals to all the power switches of the converter, with specific delays and dead times between each gating signal that ensures switching at low losses for some or all the power switches of the converter.

0 12. Fig. 36 shows a logic unit incorporated in the control loop for generation of gating signals to all the power switches of the converter, with specific delays and dead times allowing soft switching of the power switches of the converter.

13. Fig. 36/35 shows synchronization of the stroke beginning time to an external ,5 Sync signal.

14. Fig. 35 shows control of the stroke timings and dead time intervals using a fixed and pre-determined time intervals.

i0 15. Fig. 35 shows a logic unit incorporated in the control scheme for generation of all gating signals to all the power switches of the converter with specific predetermined delays and dead times between each gating signal that may achieve switching at low losses for some or all the power switches of the converter. 16. Fig. 35 shows a logic unit with a Sync input enabling synchronization of the stroke beginning to an external signal.

17. Fig. 35 shows a logic unit with a functional input which makes the control capable of turning the converter on or off. This may be used as an On/Off switch, a response to overload or over- voltage or any other external condition.

18. Fig. 35 shows a control scheme for fixed stroke interval timing for the converters' implementations which utilize low Q R-L-C networks.

19. Fig. 12 shows stroke timing through the use of a PLL or delay-locked loop

20. Fig. 12 shows detection of inductor current RMS value and activation of an auxiliary load in cases where the RMS value is not enough for reliable zero- crossing detection of the inductor current. The auxiliary load is inhibited after the control loop has estimated the proper stroke time.

21. Fig. 10 shows a simple control scheme for ZCS timing of the stroke end through a zero-crossing detector imposed on the sensed inductors' current signal.

D. Innovative aspects of System-Level Control loop system and method

1. For the Step-up and Step-down:

a. Figs. 27, 31 show the use of current-mode control and the Auxiliary input to the converter in order to fine-tune and regulate the output voltage of the converter.

b. Figs. 27, 31 show the use of current mode control with an additional Integral and Proportional control paths used in conjunction with the disclosed converter. c. Figs. 27, 31 - achieving the differential part of the current-mode controller by sampling of the converters capacitors' voltage at proper times and measuring the difference between samples. d. Figs. 27, 31 - achieving the differential part of the current-mode controller by sampling of the converters capacitors' voltage at the series or parallel stroke. The sampling point may be chosen in order to achieve a measurement close to the input or output current of the converter. 5

2. Figs. 28, 29 show waveforms of inductors' current and capacitors' voltage for the topologies of figs. 27, 31

3. Fig. 30 shows Examples of AUX connected tuning networks which can be used in [0 conjunction with our invented converter.

One of the goals of the new converter is to eliminate the high- current path within the ASIC or power elements of the converter. In the presented invention,

15 the high current exists only at the low voltage side PCB traces. The current is split or combined at the PCB level only, thus - the ASIC or power elements must deal only with the split low current levels. This differs from prior art, in which additional converter phases are used in order to split up the low voltage side current, see multiphase BUCK or BOOST converters, sometimes called also

JO Interleaved converters, which constitute the major body of the prior art.

Because the ASIC or external power elements now deal with only a fraction of the total low voltage side current, the requirement for extremely low resistances of the ASIC internal or external power elements is relaxed enough J5 to enable the use of existing, conventional power ASIC technology for efficient low voltage converter implementation.

In the disclosed invention, each power element deals only with low currents and no one power element must deal with the overall current. 10

In addition to the ohmic losses reduction by the disclosed invention, other means incorporated into the disclosed invention, such as Zero Current Switching (ZCS), Zero Voltage Switching (ZVS), energy-recovering gate drive for the converter power switches and adaptive control, further enhance its performance and may achieve high efficiency and reliability for various loads.

Unlike prior art converters used for low voltage conversion, the disclosed invention allows bidirectional power flow, a feature which is important for renewable energy applications, where at some times the source provides the energy to the load and at different times, the source is charged and becomes a load of the converter. The disclosed invention allows for bi-directional power flow, where the power flow direction adapts itself according to the instantaneous circuit conditions. This is beneficial for cases where rechargeable energy sources drive the converter or for cases where dynamic changes exist in the load causing the load to both sink and source power, quite rapidly.

Also unlike prior art low-voltage converters, the present invention is highly modular. Four basic topologies (presented in Figs. 3, 7, 8 and 9) are disclosed, showing a modular expandability. The design revolves around a basic cell structure which may be duplicated and connected in various ways with other similar cells, in order to perform various power conversion tasks.

The modular approach is also unique in its ability to produce multi-output voltages or accept multiple inputs and convert them to a single output. All of the multiple outputs of the converter track one another and each can source or sink energy to or from the converter.

Modular implementations of the disclosed invention may be done in various ways. One way is to create an ASIC incorporating a single basic cell, internal power switches and control. The ASICs are connected together to form the converter topology on the PCB. The control may be distributed or one of the ASICs' may contribute its control circuit to generate the switching commands to all of the incorporated ASICs. Another way is to use a single ASIC which is the controller and power switches gate driver and the actual power switches are external to the ASIC. This way, a single ASIC may control several basic cells. The ASIC is designed in a manner that will enable it to communicate with other similar ASICs which control other basic cells, thus producing a larger topology. Moreover, unlike prior art, the new invention magnetic elements are of relatively small values of inductance, and may be easily integrated on a single small magnetic core and work in unison, or split to discrete magnetic elements with lower value and thus inexpensive construction and low size.

Fig. 1 illustrates a simplified, top level block diagram of the disclosed invention. A block diagram of the disclosed invention is provided. A Power stages block (050) comprising N basic cells with active power switches and power switches gate drivers is connected between the power source (053) and the load (054), converting the power source voltage to levels suitable to the load. An energy bank (051) comprised of N capacitors may be connected to the power stages in some of the disclosed invention implementations, for the purpose of producing intermediate output voltages (at each basic resonant cell output). A control system (052) monitors various signals (055) measured at the power stages and produces the switch-control signals Φl (056) and Φ2 (057), which control all the active power switches of the basic resonant cells.

Fig. 2 illustrates a simplified, top level block diagram of the disclosed invention variant illustrating full- wave rectification and an auxiliary input support. A power stage block (061) comprised of N basic cells with active power switches and power switches gate drivers is connected between the power source (063) and the load (064), converting the power source voltage to levels suitable to the load. An energy bank (062) comprising N capacitors may be connected to the power stages in some of the disclosed invention implementations, to produce intermediate output voltages (at each basic resonant cell output).

An Auxiliary bidirectional power terminal, labeled AUX (065), is also available and is used for fine voltage tuning and regulation support. A control system (060) monitors various signals (066) measured at the power stages and produces the switch-control signals Φl-1 (067), Φ2-1 (068), Φl-2 (069), Φ2-2 (070), which control all the active power switches of the basic resonant cells. Four control signals are needed, (067)-(070) in order to support special features like ZVS control, as disclosed hereafter. If interleaving support is not required - only two control signals, for example (067) and (068) may be used.

Referring to the disclosed invention block diagram in Fig. 1, following is a detailed explanation of the structure and operation of the power stages block

(050). This block may be implemented in various ways, producing various topologies as disclosed in Figs. 3, 7, 8 and 9.

Additional advanced disclosed topologies exist, which relate to the inventions¹ extended block diagram of Fig. 2. These topologies are presented in Figs. 19, 21, 24, 25, 27, 31, 33, and 38. Some of these extensions require additional control signals as disclosed in their respective figures.

Fig. 3 shows a schematic of the disclosed invention topology in the first preferred variant. This variant is referred to as 'Topology 1'. It has a single input and a single output.

The embodiment in Fig. 3 is presented as an example, and it should not be interpreted as limiting the scope of the present invention. Expansion of the explanation to include the topologies of the other drawings is straight-forward and will be discussed briefly for the rest of the disclosed implementations. In all the drawings, the source and load may be connected to input and output terminals in a manner that will give step-up voltage conversion, except where explicitly stated otherwise in the drawing. In order to achieve step-down conversion, input and output terminals must be interchanged, i.e. - the load and source in all drawings must be swapped, and the direction of the power switches must be checked, and altered where needed.

Referring to Fig. 3 which presents Topology 1 of the invented converter, multi- stage converter power stages are presented. Each stage is a duplicate of the disclosed basic cell, denoted (102). The first cell in the topology is connected to the power source (100), and the last stage is connected through power switch (108) to the load (101) and load bulk capacitor (111).

Each cell may comprise three, single-pole single-throw (SPST) power switches (103), (104) and (105). The disclosed converters' topology allows the use of power switches with two-quadrant (meaning that each power switch allows bidirectional current flow in the ON position but can block only a single polarity voltage in the OFF position) or four-quadrant (meaning that the power switch can block/conduct bidirectional current flow and block bidirectional voltage) elements.

A series resonant tank (106), (107) is also present at each cell. Power switch (103) connects the cell to the output of the previous cell in the topology. Power switch (104) connects the resonant tank of the basic cell to the negative supply bar (113). Power switch (105) connects the resonant tank of the basic cell to the positive supply bar (114). Control of the power switches is done by two logic control signals - Φl and Φ2, (109) and (110) respectively. Fig. 3 presents only the logical nature of the control signals while later drawings disclose means of implementing the actual power switches gate drive signals. Φl and Φ2 take logic levels of logic T and logic '0' and must be non-overlapping.

A plurality of the disclosed basic cells may be chained to produce the desired topology which has a voltage conversion ratio of N+l, where N is the number of basic cells used. The capacitor Cout (111) holds the output voltage while power switch (108) is in the off position.

Fig. 3 demonstrates how an immediate source or load disconnect is possible in the present invention. Disabling the power switches immediately disconnects between source and load. This principle remains in force for the other disclosed topologies described herein. The disclosed converter operates in a cyclic, switching manner. Each complete cycle of the operation includes two strokes:

The first stroke occurs when all the switches connected to Φl are closed (in the ON position) and all the switches connected to Φ2 are open (in the OFF position). This state of the switches of all basic cells creates a topological structure of N branches of LC resonators connected in parallel to the input power source. The input current from the DC bus is split to N, approximately equal currents flowing via the LC resonators. The currents may differ from one another, ie due to tolerances in the respective LC resonators' component and switch resistance values.

Each resonant tank and the accompanying switches connected to it constitute a > series R-L-C circuit. Such a circuit can be mathematically represented by the Laplace equation of the form:

D We use also the acceptable values known in the art as ω_o = \HLC - the angular natural

frequency of the resonant tank, and Q = — J the quality factor of the resonant tank.

Assuming excitation of the RLC circuit by a step voltage and solving for I(s) we get:

/(s) = v(s)- — = V_x — = V_x -= [Eq. 1] s²LC + sRC + l s s²LC + sRC + l ^x s²LC + sRC + ϊ

During the first stroke, Vx is the input voltage (100) minus the residual capacitor voltage (remaining in the capacitor from the previous stroke). During the second stroke Vx is V_o (112) minus the residual capacitor voltage (remaining in the capacitor from the previous stroke). Performing an inverse Laplace transform, we get the time signal of the :0 said resonant tank current (assuming that the initial current at the strokes' beginning is 0):

This expression may be written in terms of ω_o,Q as: 5

Kt)

These expressions for i(t) are true for Q>0.5 or 4LC≥(CR)². For this range of Q, the current waveform begins at 0 and crosses zero again after T₀ time, where T₀ is:

In the normalized current waveform is presented, for Q=I (see (125)) ,2,5 and 10 (see (126)). The waveform shown is a decaying sinusoidal. For Q values lower than 0.5, Eq. 3 is not suitable and a different solution exists for the inverse Laplace transform of Eq. 1. This solution is of the form:

Eq. 4 waveforms are also presented in (see for example (127), (128), showing an exponential rise and decay of the current waveform. There is no definite zero-crossing of the current waveform for this case. Both ranges of Q (Q>0.5 and Q<0.5) are useful for this invention, but may require different control means.

Fig. 5 presents characteristic waveforms that may be measured at various test points of the disclosed topology in the first variant (Fig. 3).

In Fig. 5 we present the waveforms of the resonant tank inductor current and capacitor voltage, for the case of sufficiently high Q (Q>0.5). Networks with lower value of Q are also useful as presented later. At steady state, at the beginning of the first stroke (Fig. 5, (153)), the current through all resonators' inductors is zero. Therefore - each resonator begins conducting (charging) with an approximate-half sine wave, typical of series LC resonant circuit, see Fig. 5, (156) and the analysis above ( [Eq. 3]). A control system (disclosed hereafter) may estimate the time or detect when the half sine wave current reaches zero again (157) and end the stroke at this instant. Other control methods may be possible, some of which are also disclosed hereafter.

The capacitors of each basic cell resonant circuit are charged by the approximate- half sine wave current and at the end of the first stroke (approximate-half sine wave); the voltage of each capacitor is increased by a constant ΔV (162). An arbitrary dead-time (151) may be inserted by the control system separating the first stroke from the second stroke. During the dead-time, the voltage on the capacitors is maintained (if self discharge is neglected) (161).

The dead-time (151) may be used by the gate energy recycling driver which drives the converters' power switches. As the recycling operation usually takes time, from a few tens of nanoseconds up to several microseconds, depending on implementation variations, providing dead-time capability between strokes makes headroom for the recycling gate driver to operate in. The dead-time may be reduced to virtually zero when gate energy recycling is not required. The dead-time also allows for the system to settle down before the next stroke, so various switching noises and spikes happen before any logic decision of the converters' controller.

In a preferred embodiment, one should not excessively increase the dead-time, as dead-time is an inactive portion of the switching cycle. During the dead-time the converter does not supply energy to the load, and in order to supply the load requirements - RMS current will increase naturally during the rest of the switching cycle, to compensate.

The second stroke (154) occurs when all the switches connected to Φ2 are closed (turned ON) and all the switches connected to Φl are open (turned OFF). The resulting topological structure is of one branch composed from N sections of LC resonators connected in series between the input power source (100) and the load (101). The series connection is equivalent to a single resonant branch composed of all the inductors in series (Ltotal=N-L) and all the capacitors in series (Ctotal=C/N). The equivalent resonator has the same resonance frequency as every resonant section of the first stroke. Typical waveforms of the combined resonator can be analyzed using the same equations as for the first stroke.

At steady state, an approximate half sine wave current flow through the equivalent resonant branch (152) with direction opposite to the direction of

5 current flow in each resonator at the first stroke. Therefore, all the capacitors are discharged into the load, while connected in series, and their voltage is decreased by the same amount ΔV (162), which was charged during the first stroke. A control system monitors the equivalent resonator current and ends the second stroke when the current reaches zero (158). After the secondO stroke, the capacitors reach the initial voltage, V(O), (164) which existed before the first stroke. This completes the two stroke cycle at the same working point of the cycles' beginning. Before the next cycle begins, a dead-time may be inserted after the second stroke (155). During this dead-time the voltage on the capacitors (163) is maintained at their initial voltage (164).

5

The arbitrary dead-time may be added at the end of the first (151) and second stroke (155) because the current through the resonators is zero at both beginning and end of each stroke. This feature may be utilized to operate the power switches by adiabatic gate drive, which trades-off gate charging time and

'.0 power losses. Some of the converters' power losses are due to gate energy, recovering of which is extremely important for low power (typically 2-3Watts and below) conversion applications or for some choices of power switching elements.

At steady state, output voltage Vo (112) asymptotically reaches (N+1)-Vs. This :5 value can be reached only at no load (Zero current at all the resonators). As the load increases, a small voltage drop occurs. This is due to the increase in the currents at both strokes through the equivalent series resistance (ESR) of the power switches and the resonator components. Ideally, zero current switching (ZCS) occurs at all power switches so reducing ESR is the main 0 significant factor required in order to get good power conversion efficiency.

For implementation reasons, it may be preferable for the resonators of the basic cells top be identical, i.e. - with the same inductor and capacitor. This is useful for the reducing switching losses to a minimum, as the zero-crossings of all branches currents in the first stroke will be practically equal, and the discharge of the capacitors at the second stroke will be practically the same amount, ΔV. Further equalization of the basic resonant cells currents may be achieved by introducing coupling between the various inductors L(k), k=l..N. This coupling may ease implementation as all inductors will share the same magnetic core.

An additional inductor (winding), not associated with the basic cells may share the same core and be used as waveform monitoring means for the control loop of the converter. This is beneficial as this inductor is not directly in the power conversion path of the disclosed converter.

A different approach for reducing inductors tolerances is to use two inductors instead of multiple inductors and place one of them in series with the source Vs (100) and one - in series with the load Vo (112). This will eliminate the inductors tolerances and also have other beneficial advantages, utilized in different disclosed topologies, presented later.

Fig. 6 shows, by way of example, an implementation of the SPST power switches

(104), (105), etc., and power switch driver used in the drawings that disclose the various topology variants.

This is a preferred implementation of each of the power switches in the basic resonant cell. The symbol denoting the power switch (200) is equivalent, in this implementation to a power N-channel MOSFET semiconductor device (201) driven by a Gate Driver (202). The Gate driver is controlled by either Φl or Φ2 (204). The Gate Driver may require its own power supply (bias) denoted by (203). For a simple, non-energy recycling driver - a single power supply may be used.

In case of an energy-recycling, adiabatic Gate Driver - a plurality of bias ports may be required, as disclosed and demonstrated later.

Other semiconductor devices may be used as the power switches operating the disclosed invention, instead of a N-channel MOSFET, including P-channel MOSFETS, LDMOS transistors, Bipolar transistors, IGBT's or other devices. In some cases special provisions for driving these semiconductor devices will be required or some of the inventions¹ properties might not exist with different semiconductor devices.

Fig. 7 discloses the second embodiment of the invented converter. This variant or embodiment is called 'Topology 2'. It has a single input and multiple outputs. In this implementation - changing the basic resonant cells' structure allows for the extraction of the voltages at each cells' output.

The basic cell (253) now comprises of four power switches (256) - (259) controlled by the same control signals Φl (260) and Φ2 (261). A capacitor (262) is connected in parallel between the output of the 2nd and 1st basic cells (or - k'th and (k-l)'th basic cells), thus producing output terminals Vout(2) (263) or for the k'th cell - Vout(k).

Operation of the converter is similar to the operation of the Topology of

Fig. 3 with the exception that when Φ2 causes the switches connected to it to turn OFF - the outputs of all the cells, Vout(k), are disconnected from their resonant tanks and may hold their voltage, charged in the output capacitances

(262). At this time - Φl causes the resonant tanks of all basic cells to be connected in parallel with the source (250), in the same manner which was explained for the topology of Fig. 3. Capacitors (262) may be connected between each cell's' output (263) and ground, instead of connecting them between two consecutive cells' outputs. The voltage at the k'th cell output is

Vout(k) »Vs-(k+l). Also we observe that Vout(k+1)-Vout(k) «Vs for k=0..N (where

Vout(0)=Vs). The equality is not accurate due to ohmic losses in the power switches of the topology.

Fig. 8 discloses the third variant of the invented converter, named 'Topology 3'. This variant uses two instances of topology 2's variants, working at interleaving. It presents an adaptation of the topology of Fig. 7 (Topology 2), where the basic cell (302) is comprised of two basic cells of Fig. 7, working in anti-phase. When the first sub-cell comprising of switches (305) ( connected in parallel with the input source (300), the second sub-cell comprising of switches (309) - (312) is feeding the load and voltage holdup capacitor (303). This achieved by the special connection of Φl and Φ2 to the sub-cells' power switches as disclosed in Fig. 8. A bulk capacitor may be added in parallel with the load in order to provide filtering and ripple smoothing.

Fig. 9 presents and discloses the 4th variant, named 'topology 4'. This variant is an adaptation of topology Ts variant, but with a single input inductor and a single output inductor. This variant may be used for cost-critical applications.

It is not mandatory to produce an output Vout(k) from every cell, k. When Vout(m) for a specific cell, m (m is chosen from [1 ... N]) is not needed - three switches per basic cell m are required instead of four, and connection between both anti-phase sub-cells m, (317), are not required either). In case where multiple inductors implementation is costly or inconvenient, the topology of Fig. 9 (Topology 4) may be used. Fig. 9's arrangement has additional benefits discussed hereainfter. The basic cell (353) now contains only the capacitor part, (357), of the resonant tank and the power switches (354),(355) and (356), while the inductive part of the resonant tanks is comprised of two separate inductors.

Inductor (360) is used during the first stroke, when charging the capacitors in parallel to the source (350). The shared inductor (360) supplies the current for all cells which are connected in parallel at this stroke. At the second stroke, the cells are connected in series, and the capacitors are discharged through both input Ll=LZN (360) and output L2=L-(N-1/N) (361) inductors, where connection (364) is used. When connection (365) is used, the capacitors are discharged through L2 (361) alone. The inductors Ll and L2 values noted above are not mandatory. Different inductors selections may now be used in order to pursue various design goals, see additional drawings described hereafter.

When using the inductors selection described above (i.e. L1=L/N and L2=L*(N- 1/N)), at the first stroke, N capacitors are connected in parallel, showing an equivalent capacitance of Ctotal=C-N, and they are charged through a L/N inductor, thus - the typical resonant frequency is the same as for the case of Fig. 3. During the discharge stroke (stroke two) - the capacitors and inductors are all connected in series, thus having Ltotal =

L1+L2=L/N+L-(N- 1/N)=L-N and Ctotal=C/N, again reaching the same equivalent resonant frequency. Inductor Ll (360) should be designed to cope with the total low voltage side current but the needed inductance is quite small (L/N).

Inductor L2 (361) should be designed to cope with the total high voltage side current but the inductance is somewhat larger (L-(N-1/N)). Therefore - implementation of both inductors requires roughly the same effort, and they will exhibit roughly the same losses.

The topology of Fig. 9 may be expanded to include interleaving (operation in anti-phase), in similar manner by which the topology of Fig. 7 was expanded to produce the topology of Fig. 8.

The control scheme for the disclosed power converter topologies is based on a process in which the first stroke initiation (see Fig. 5, (156)) is forced, and end of the first stroke is timed to merge with zero-crossing of the resonator current (see Fig. 5, (157)). Similarly, the second stroke initiation is forced, and the end of the second stroke is timed to merge with the zero-crossing of the LC resonators current (see Fig. 5, (158)).

Fig. 10 discloses another preferred embodiment of a method of stroke timing that may be used in order to control the power switches of all disclosed variants of the invented converter. This control scheme may be used for simple loads, as described herein.

In Fig. 10 part 1, the block diagram of the controller (400) is disclosed, having three inputs - the LC resonators signal sample (401), usually the current, is the driving signal for the controller, the system clock (403) is timing the control function and the dead-time amount (404). The controller produces the two signals Φl and Φ2 (402) discussed above. Instead of sampling the current of the LC resonator directly, one can measure the voltage of the inductor or capacitor and integrate or differentiate it to obtain the current. In the case of integrated magnetics (i.e. - incorporation of all the inductors on a single magnetic core), a separate, special winding may be used to estimate the resonators current.

Various methods may be used for implementing this control process. The difference between these methods is mainly in the detection or estimation of the zero-crossing time of the said LC resonators current waveforms. Selection of the preferred implementation depends mainly on the type of the load and its dynamic behavior.

The typical and most common loads have unidirectional power flow. Moreover, the minimal current consumption of the load is sufficiently high in order to enable simple zero crossing detection. A load meeting both criteria is said to be a "simple load". Fig. 10 part 2 gives an example of the control scheme that may be used in this case.

The system clock (405) is connected to a frequency divider and logic block (411) producing the signal ¹G¹ (418) (which controls directly a D-type Flip-Flops (409) and inversely - another D-type Flip-Flops (410)) and the signal 'block' (417) (which controls the D-type Flip-Flops' Reset port blocking gates (415) and (416)). The LC resonators signal sample (401) is chosen in this case to be the current of the LC resonators (406). This signal is fed to a zero crossing comparator (412), which controls the Reset port of the D-type flip flops, directly for Flip-Flop (409) and inverted for Flip-Flop (410), using inverter (413).

The system clock, (405), having frequency fl, is divided by the frequency divider block (411) to form the cycle clock, a signal with frequency f2 (418) and 50% duty cycle. The frequency f2 approaches the series resonators resonance frequency from below, and may be approximated by:

Λ ≤

/ 1/ f - ⁺i- 9^Δ • ^l T dead time •> res

Where f_res is the said resonance frequency of a LC resonator and Tdead-time is the time between strokes, chosen by the constant (420) (see also Fig. 5, (151) and (155)). The chosen dead-time is achieved in practice only if the implemented LC resonators resonance frequency does not deviate from the designed resonance frequency fres. If deviations exist, for instance - due to tolerances in the inductors and capacitors values used, the actual measured dead-time will be smaller or larger than the constant Tdead-time. This, however, does not disturb normal operation of the disclosed converter, as long as sufficient dead-time remains.

The logic circuit in (411) also generates the blocking signal (417). This signal when low (¹O¹) blocks the reset port of the D-type Flip-Flops (409) and (410). When the Reset port is blocked the controller disregards the comparator (412) decisions. The blocking instances are timed to take place slightly before and after the edges of the cycle clock f2 (418). This is needed because the Reset input of the D-type Flip-Flops (409, 410) is asynchronous. Therefore - the Flip-Flops will not be triggered by f2 cycle clock if a Reset happens during clock transition.

Fig. 11 presents characteristic waveforms that may be measured at various test points of the disclosed topology in the first variant (Fig. 3) operated under the control scheme of Fig. 10. Fig. 11 gives typical waveforms for the control scheme of Fig. 10, 2. IL(k) is the current waveform of the LC resonators. This waveform is the one that is sampled by the control scheme of Fig. 10. During the first stroke (453), the cycle clock f2 (459) is high (T) and Φl is high (T). The comparator resets the D-type Flip-Flop (409) when the sampled current reaches zero (457). This causes Φl to go low (¹O¹).

The second stroke (454) is initiated after the first dead-time (451) by the falling edge of f2 which causes Φ2 to go high (T). The comparator then resets Flip-Flop (410) when the current during the second stroke reaches zero (458), after the LC resonators' capacitors have been discharged into the load and bulk capacitor. The rising edge of f2 starts the next cycle, after the second dead-time (455). The drawing also presents the blocking signal (460), which blocks the comparators' output from reaching both Flip-Flops (409) and (410), during the rising and falling edges of £2. The control scheme presented in Fig. 10 may be enhanced by adding protection circuitry for ensuring that Φl and Φ2 are not active simultaneously, working with window comparators in order to fine-tune the switching instance selection, or improvements in the implementation of the LC resonators signal sampling and zero- crossing instant estimation, as disclosed by the example shown in Fig. 12.

The load connected to the disclosed converter isn't always a simple load. Therefore we define a "Complicated Load" as a load not meeting at least one of the requirements from a simple load. Therefore - a load with bidirectional power flow and/or with current consumption whose zero crossings cannot be practically detected by a comparator is a complicated load. For complicated loads, the control scheme disclosed in Fig. 12 may be used in order to control the disclosed power converter. Other control schemes are possible for dealing with complicated loads. An example is shown in Fig. 36.

Fig. 12 discloses a preferred embodiment of a method of stroke timing that may be used in order to control the power switches of all disclosed variants of the invented converter. This control scheme may be used for complicated loads. This architecture is capable of dealing with bidirectional load and low load conditions. When the load is low - the current waveform of the basic resonant cell may be very low, making the zero-crossing detection of the previous control scheme (Fig. 10) unreliable. Moreover - the scheme of Fig. 10 is sensitive to the current and energy flow direction, which may not be easily detected in low load conditions or may change abruptly for a bidirectional load. Fig. 12 improves the control scheme, with the expense of more hardware, and relieves these limitations.

The basic resonant cells' current is sensed using a current sensor (500) or equivalent methods. The sensed signal (517) is fed to a zero crossing detector (501) which output (514) generates a short pulse for every zero crossing. This short pulse is fed into a counter (503) through an AND logic gate (502), which passes the zero crossing signal only within a specific time window (513) and if the RMS value (509) of the sampled current (517) is above a certain predetermined value. Stroke timing logic (513) initiates each stroke by a designated short Φ1/Φ2 Start pulse (515), timed by the system high-speed clock (504). When the Φ1/Φ2 Start pulse rises, the counter begins to count clock pulses. The Stroke Timing Logic (513) generates the time window in which the end of the stroke is most likely to appear, based on previously detected stroke time (516). If a zero crossing of the basic cells' current is detected within this window, a signal (508) is passed to the counter at the Stop terminal. This causes the counter to stop counting. Also, the same signal (508) is passed to a Sample/Hold system (506) which captures the counter value (505). The output of the Sample/Hold system is averaged (507) and fed to the Stroke Timing Logic (513) as the estimated stroke duration (516).

The Stroke Timing Logic (513) generates the stroke control signals Φl and Φ2 as follows: at the rise of the Φ1/Φ2 Start signal (515), the respective Φl or Φ2 is driven high. This causes the basic resonant cells' current to start rising (with (+) or (-) sign) from zero. The Stroke Timing Logic then waits until the estimated stroke time for the respective stroke to pass, and then - it drives the respective Φl or Φ2 low.

When the load is low, the RMS measurement (509) of the sampled current (517) is quite low also. In this case, the Stop input to the counter (503) will be blocked by the logic gate (502) and the control will continue to operate according to the previously estimated stroke time. Other methods of estimating the waveforms' intensity other then RMS measurement may be good enough also.

When the load suddenly turns low, the Stop signal to the counter (503) might not appear. The counter will continue to count until it overflows its internal register. In such case - the Overflow output (518) of the counter will signal the overflow condition.

The Auxiliary Load Connection decision system (510) receives the RMS measurement and the Overflow output of the counter (518). If the RMS measurement (509) is too low for too much time or the Overflow signal (518) appears too often, the Auxiliary Load Connection decision system output (512) will go high and remain high for a predetermined time. When high, this output causes the connection of a dedicated load in parallel with the actual load. The dedicated auxiliary load connection has the effect of increasing both strokes resonators current. The auxiliary load is high enough for the reliable estimation of the stroke time by the disclosed zero-crossing instant estimation scheme.

The system designer must be aware that the auxiliary load and actual load may draw instantaneous currents of different directions and choose the auxiliary load such that it will deal with this effect.

Note that the Sample/Hold (506) and Averaging (507) system and the estimated stroke duration signal (516) may be multiplied in order to enable different stroke times estimation, for the first and second stroke. A selector is then needed at the input of the Sample/Holds in order to route the different counter estimates to each Sample/Hold at each stroke. This may be very useful when using Topology 4 (see Fig. 9) which allows for different Ll and L2 values, and therefore - allows different stroke durations.

Later drawings (ie Figs. 20 and 22) disclose another example of a control method and scheme that may be used to drive the power network switches. Other schemes are also possible.

The disclosed invention topologies share the feature of fixed voltage-conversion ratio, which is determined by the number of basic resonant cells used. Some loads, however, require an operation voltage within a certain range, therefore - a variable voltage- conversion ratio may be needed in order to drive these loads. Figs. 13 through 17 show methods or techniques that enhance the basic converter topologies by adding the feature of variable voltage conversion ratio, in a manner that preserves overall efficiency (in contrast to linear regulation that may effects overall efficiency dramatically). Additional techniques exist for conversion gain control and fine- regulation, which will also be disclosed by later drawings.

Fig. 13 discloses a subsystem that may be connected at the N+l outputs of the invented converter topologies 2 and 3, and enable coarse regulation of the output voltage or other measurable quantities. The regulation is based on the controlled operation of a routing network. In Fig, 13, a simple coarse voltage regulation scheme is disclosed. This scheme can interface with the topologies disclosed in Figs. 7 and 8. A Routing network with m inputs (m=N+l, where N is the number of basic cells in the power conversion topology used) and one output (550), comprised of SPST power switches connected as an analog power multiplexer, with a control input (559).

The inputs of the routing network (550), (556) etc., are connected to the basic resonant cells' outputs of the disclosed converter topologies. The output of the routing network feeds the load (554) through a smoothing filter (552) and optional decoupling capacitor (553). A controller (551) measures the difference between a reference voltage (557) and a controlled voltage (558) and selects the appropriate routing network path that minimizes the said difference. The controlled voltage (558) may be the loads' voltage or any other related controlled signal. The Smoothing Filter (552) may be passive or active and at steady state approaches a short circuit between its input and output (emulated by a saturated pass transistor).

Fig. 14 discloses a subsystem that may be connected at the N+l outputs of the invented converter topologies 2 and 3, and enable fine regulation of the output voltage or other measurable quantities. The regulation is based on the controlled operation of a routing network and a fast power SPDT switch. Fig. 14 discloses a more complex, fine voltage regulation. A routing network (600) with n inputs and two outputs (612), (613) is used. The inputs of the routing network ((606), (607) and so on) are connected to the basic resonant cells' outputs, in a similar manner to Fig. 13. The routing network has the internal structure of two independent m:l routing networks (like network (550) of Fig. 13). Each m:l internal routing network is connected to m inputs and to a unique output of the m:2 network. The outputs (612) and (613) from the m:2 network (600) are connected to a duty cycle controlled (PWM, hysteresis or other control) high speed SPDT power switch (602), LC filter ((603) and (604)) and the load (605). A controller (601) is used to control the routing network through the control interface (611) and the SPDT power switch control input (610). The SPDT power switch has a disable input (614). The controller first selects the position for each internal routing network of the m:2 routing network, thus routing two unique inputs of the routing network to its unique outputs. The selection is performed according the error signal generated from the Controlled Voltage (609) and Vref (608) inputs. This

5 selection normally does not change often, and reselection happens only when significant load or input changes happen. Also, in normal operation the controller will select outputs (612) and (613) so that they are connected to subsequent outputs of converter (for instance: Vout(m+1) and Vout(m)) . The controller also modulates (610), the high speed switching of the SPDT power

0 switch (602). This modulated switching allows fine regulation between the two outputs (612) and (613) voltage. For example, in PWM control, and at steady state, the average load voltage will be:

V_load = V(6l2)-D + V(613)- (l-D) = F(613) + [F(612) -F(613)]-D

5

Where D is the duty cycle, and V(612), V(613) are the voltage of the selected outputs from the routing network (600).

Because the voltage difference between outputs (612) and (613) differs only by :0 Vs, approximately, losses in the fast SPDT switch (602) are low and efficiency does not degrade much due to non ZVS or ZCS operation of the said SPDT switch (602).

The control system may use the disable feature (614) of the SPDT power switch (602) to disconnect the load when the output voltage is not between the two \5 routing network outputs (612) and (613) voltage. Such conditions may appear, for short periods of time, during transients.

Fig. 15 discloses a preferred implementation of the coarse regulation method used for coarse output voltage regulation. The regulation is done using comparators, an encoder i0 and a decoder, controlling a power routing network.

The simple, coarse voltage regulation scheme of Fig. 13 may be controlled in the manner depicted in Fig. 15. In Fig. 15 an example of a feed-forward control law is disclosed, used to control the Routing network (650) in order to implement output voltage regulation. Other measurable quantities may be regulated using similar methods, like the input voltage to the disclosed converter, the power drawn from the source driving the converter, etc.

In Fig. 15, the m: 1 routing networks' inputs (657) are connected to Vs, Voutl through

Vout(N) and the N+l comparators (656) at the negative (-) input.

The positive (+) input of all the comparators is connected to a voltage signal equal to the desired output voltage (658). Therefore - the output of the k'th comparator will be T if the k'th input is below the desired output voltage. As a result - all inputs from (657) having a voltage above the desired input voltage will cause their respective comparator to output ¹O¹.

The outputs of the N+l comparators are fed into a logic priority encoder (651), having h outputs where h=log2(N+l). This encoder will give at its output (660) the number (code) of the highest comparator with 'T at its output. For example if Vs=O.5 V the voltages at the input to the routing network will be:

V(k)=Vs-(k+l)=0.5-(k+l)

Where k=0..N+l. If, for example, the desired output voltage is 3.2V, comparators 0 through 6 will have ¹T at their output, and comparator 7 through N+l will have an output of logic ¹O¹. The priority encoder, therefore, will have 6 encoded to binary (i.e. 1,1,0) at its output.

The output of the priority encoder (660) is connected to a logic decoder (652) which outputs control the routing network (650). The decoded code word causes the routing network to connect to its output the input V(k) which is closest to the desired output voltage (658). If, for example, the input voltage to the converter changes, this will effect all V(k)'s. As a result - some comparators may change state causing the control to route another of the routing networks' inputs to the load. Similarly - if the load current changes, this might have an effect on the voltages V(k), due to parasitic series resistances of various power switches (like MOSFETS RDS,on) in the converter. The change in some or all of the V(k)'s may cause the comparators to change state and the control to route a different V(k) to the load. Note that additional means may be added to this control scheme in order to prevent fluttering of the routing network (650) near the cross-over of the control, for example - adding hysteresis to the control loop.

Fig. 16 shows typical regulation results for the coarse voltage regulation scheme of Fig. 5 15. At one plot the load voltage is shown versus the source voltage and at the other - the load voltage is shown versus the load current, where constant series impedance is assumed as the source of ohmic losses per each basic resonant cell.

Fig. 16 presents the load voltage (Vout,load) for the disclosed converter with coarse 0 regulation as depicted in Figs. 13 and 15. In the left graph (700) - the load voltage (704) is presented versus the source voltage of the converter (702) - Vs. Output voltage is chosen to be 5V and the input voltage to the converter, Vs, is swept from 0.3 to IV. As the source voltage (702) change - the control (Fig. 13, (551)) together with the routing network (Fig. 13, (550)) routs different converter outputs to the load in order to compensate for the [5 source voltage changes. Because there are only N+l discrete outputs to choose from - accuracy of the regulation is limited to multiplication of Vs, the source voltage.

In the right graph of Fig. 16 (701), the effect of load current on the output terminal voltage at the load (705) is presented, for the same converter topology and coarse regulation. In

.0 this example, Load current (703) is swept from 0 to 2 ampere, and the output voltage is selected to be 5V. Total series resistance (ESR) for each basic cell is chosen to be 20mOhm. The voltage drop on the total ESR of the entire converter and regulation system is reducing the load terminal voltage (705). Eventually - this voltage drop causes a change in the selected output of the routing network (Fig. 13, (550)) in order to compensate for 5 the voltage drop.

Fig. 17 discloses a preferred implementation of the fine output voltage regulation, which includes a power routing network with two outputs and a high speed power SPDT and their controls. It discloses another method of regulating the output voltage of the disclosed 0 converter, in a continuous manner. This scheme is a Feedback control scheme (unlike the Feed-Forward scheme presented in Fig. 15) and is an implementation of Fig. 14.

The m:2 routing network (750) is controlled by an up/down counter (754). At every clock (766) rise, the counter either increases its stored value or decreases it or does not change it, according to the signals received at it's up and down inputs. For a particular clock rise, the following equation describes the output of the up/down counter:

^Cθlint _previ_ou_s Up = ¹ O ¹; dOWH = ' 0 '

^CθUnt pr_evi_ou_s + ¹ Up = ¹V; doWH = ' 0 '

Concurrent

^CθUnt previous ~ 1 Up = ¹ O ¹; doWH = ' 1 '

^CθUn * _previ_ous Up = ¹V; dOWlt = ¹I '

The counter receives up or down commands only during the rising edge of the clock (766). The up and down signals are produced by comparators (760) and (761). These comparators compare the higher output (764) and the lower output (763) of the m:2 routing network, to the desired output voltage (759).

Therefore - if the desired output voltage (759) is not between the higher and lower outputs of the routing network, the counter (754) will count up or down and shift the position of the routing network in the direction that brings the desired output voltage (759) between the higher and lower outputs of the routing network.

When the desired output voltage (759) is between the higher (764) and lower (763) outputs of the m:2 routing network (750), both comparators outputs are logic ¹O¹ and the counter holds its value.

The higher (764) and lower (763) outputs from the routing network (750) are connected to the high speed SPDT power switch (754). During adaptation of the counter (754) (i.e. - when the counter counts either up or down) the SPDT power switch (754) is disabled, thus the higher (764) and lower (763) outputs of the routing network (750) are disconnected from the load. This is useful since during counter adaptation, voltages higher than the desired output voltage may appear at the higher (764) and lower (763) outputs, which may cause damage to the load.

The SPDT power switch (754) is connected to an L-C smoothing filter (755), (756) and to the load (757). For output voltage regulation, the load voltage (758) is measured and fed into a PID (Proportional, Integral, and Differential) controller (753) along with a reference signal representing the desired output voltage (759). The output of the PID controller is fed into a PWM modulator (752) as the duty cycle command. The PWM modulator controls the SPDT power switch. The use of PWM modulation or PID controller is not mandatory, and serves only for examples' sake. Any other control method typical for power converters' voltage regulation is applicable.

Fig. 18 discloses the internal connections of the two routing networks, the m: 1 and m:2 routing networks, used for regulation according the schemes of

Fig. 13 and Fig. 14. Fig. 18 presents a possible implementation of the routing networks of Figs. 13, 14, 15 and 17. In Fig. 18 drawing 1, the m:l routing network (800) is presented. N+l bidirectional power switches (801) connect the various inputs (802) to the output (803). Each switch is controlled by a dedicated control line from the control interface

(804). At any given time, only one control line from [controlO, control 1, ,control(n)] may be active.

Fig. 18 drawing 2 presents the m:2 routing network (805). This network may be implemented by a combination of two m:l routing networks (809) and (810), with inputs (811) and (812) connected to the same [Vs,Voutl,...Vout(N)] outputs of the invented power converter topology and two unique outputs (806) and (807). The control of the routing networks is done by two control interfaces (808). When the control interfaces are connected in the manner depicted by the drawing, the m:2 routing network (805) outputs (806) and (807) will always be one tap apart.

The regulation schemes described so far allow for tuning and regulation of a circuit parameter (like the output voltage) in response to circuit parameter changes. These schemes may respond to changes covering a wide range of voltages. Additional regulation and tuning methods are presented that can cope with narrower range of voltages, but with improved efficiency and power-element count (less power elements). These methods are disclosed later in additional drawings.

Fig. 19 presents a typical usage of variant 4 of the disclosed invention, where two networks of the 4th variant that operate in parallel and anti-phase, working as a Step-Up converter. Fig. 19 presents another embodiment of the 4th topology variant (presented in Fig. 9). In this drawing, two networks (Network A and Network B) of Topology 4 are used, (858) and (859), and operated in parallel and anti-phase. A single input inductor Ll (854) and a single output inductor L2 (855) are used by both networks. Like in the basic Topology 4, the input of the series connected power switches may be connected after Ll, using (857) or before Ll, using (856). Note also the two switches (880) and (881) connected at the output of each network and their special control signals (882) and (883). The description of the topology waveforms that follows in Fig. 20 relates to the connection using (856) option.

The separation of inductors to an input and an output inductor allows us to choose different current-waveform shaping for the 1st and 2nd strokes and achieve ZCS or ZVS, as needed.

Fig. 20 presents characteristic waveforms that may be measured at various test points of the disclosed topology in the 4th variant operating in parallel and anti-phase Step-Up (Fig. 19) and with high value of Q in the charging path. Fig. 20 presents the current waveform in the internal capacitors of each network (858) and (859). Network A capacitors are charged in the first stroke (900) and discharged in the 2nd stroke (901). Network B capacitors are charged in the 2nd stroke (901) and discharged in the 1st stroke (900).

For the charging strokes, the input inductor is so selected as for the current waveform to have two zero-crossings (for instance: (905) and (906)). Therefore - ZCS is achieved on all the switches involved in charging the capacitors (for the step-up variant of Fig. 19 - these are all the parallel-connecting switches). For the discharge stroke - the preferred choice of output inductor is one that lowers the output current ripple. This is beneficial as it relaxes the output filtering capacitors requirements.

Therefore - the current waveform at the discharge stroke inductor (L2, see Fig. 19 (855)) is close to a constant current. This calls for an almost-rectangular capacitors current waveform at the discharge strokes (see (907) and (909)) of both networks. The two networks, A and B exchange connection to the load at instant (908) and (914). Because the two networks exchange the connection to the load at the same moment - there can not be Zero-Current switching at the discharge phase. However, since each networks' capacitors are only slightly discharged during the discharge stroke - the voltage difference exhibited on the output power switches, (880) and (881) in Fig. 19, is very small and ZVS is almost achieved.

0 Fig. 20 further discloses the power switches control signals used in this operational regime. Other variants of the control signals are possible, depending on the actual design requirements.

In this drawing, a high control signal means that the power switch connected 5 to it is ON (conducting) and a low control signal means that the power switch connected to it is OFF (not conducting).

The charging strokes are controlled by Φl-1 for Network A and Φl-2 for Network B, and operate in a non-overlapping manner (keeping a dead time (902) and (903)

,0 between them). The discharge strokes switches are controlled by Φ2-1 and Φ2-2 which change state during the beginning of the dead time. The last power switch of each network (switch (880) and switch (881) of Fig. 19) are controlled separately by the special control signals Φl (882) and Φ2 (883) of Fig. 19. Signals Φl and Φ2 are delayed versions of signals Φ2-1 and Φ2-2. The reason for

15 this delay is further disclosed by the following explanation:

In the discharge stroke, the power switches of each network which connect the internal capacitors in series undergo substantial voltage variations when they are toggled by Φ2-1 and Φ2-2. Therefore - in order not to create losses on i0 these switches they need to toggle while their current is zero. This is done by delaying the connection of the last switch of each network, namely (880) and (881). After the series connection of network A or B capacitors has been established - the voltage difference between the terminals of the output switch of that network is small. This allows for its connection at almost-ZVS conditions by applying Φl or Φ2 respectively to the output switch.

Fig. 21 presents a typical usage of variant 4 of the disclosed invention, where two networks of the 4th variant that operate in parallel and anti-phase,

5 working as a Step- Down converter.

Fig. 21 discloses the use of the disclosed Topology 4 networks connected in parallel and anti-phase and operated as a Step-Down converter. The input voltage source Vs (950) and input inductor Ll (955) are connected to the series-path of the power- conversion networks A and B. the load, (951) and

0 filter capacitor (953) are connected to the parallel-path of the power-conversion networks A and B through the output inductor L2 (954). The Step-Down operation requires unique operation of the parallel connection high switches S(k)H similar to switches (982) and (983). This is done through special control signals Φ1-1A (980) and Φ1-2A (981).

[5

Fig. 22 presents typical waveforms that may be measured at various test points of the disclosed topology in the 4th variant operating in parallel and anti-phase Step-Down (Fig. 21) and with high value of Q in the charging path. Fig. 22 discloses typical waveforms of the Step-Down converter disclosed in

_0 Fig. 21. Ll (input inductor (955) in Fig. 21) is selected in a manner that will cause a capacitor current waveform with two zero crossings (1005) and (1006) when all capacitors of each network are connected in series with the source, Vs. Similar to the Step-Up case described above, the discharge Stroke is performed under almost constant current, in both discharge strokes, see

25 (1007) and (1009).

In the charge stroke, the power switches connecting the capacitors in series are switched at the zero crossings (like (1005) and (1006)) of the charge current, therefore - undergo ZCS. Signals Φ2-1 (1010) and Φ2-2 (1012) control 30 the (series) switches responsible for charging the networks' capacitors (here also - when a control signal is high - the power switch connected to it is ON and conducting. When the control signal is low - the power switch connected to it is OFF and non-conducting). The discharge stroke of Network A begins when turning ON the low parallel switches of Network A by raising Φl-1 (1011), slightly after the beginning of the dead time zone (1002). After a short delay (1008), Φ1-1A (1015) is turned ON and at the same time Φl-2 (1013) and Φ1-2A (1016) are turned OFF. This creates a make-before-break switch-over of the discharge process from Network B to Network A (Fig. 21,(951)). A similar process happens at the discharge stroke of Network B, which begins when turning ON the low parallel switches of Network B by raising Φl-2 (1013), slightly after the beginning of the dead time zone (1003). After a short delay (1014), Φ1-2A (1016) is turned ON and at the same time Φl-1 (1011) and Φl-1 A (1015) are turned OFF. This creates a make-before-break switch-over of the discharge process from Network A to Network B (Fig. 21, (951))

The described process, disclosed in Fig. 22 and its explanation creates the conditions for ZCS for all the parallel low-side switches of networks A and B, namely S(k)L (k=l,2,...,n), and almost-ZVS for all the parallel high-side switches of networks A and B, namely S(k)H (k=l,2,...,n) and ensures a continuum of almost-constant current supply to the load, at both strokes. This allows for the reduction of output side inductors' current and output capacitor (953) current ripple, which is beneficial, for the same reasons discussed above for the Step-Up case disclosed in Fig. 19.

The delays shown in Fig. 20 (908), (917), (914), (918) and in Fig. 22 (1008), (1017), (1014), (1018), (1019) and (1020) should be chosen large enough to allow the power switches enough time to make the transition from the ON to the OFF position or vice versa. Switching transitions may be performed with or without gate energy recovery. Performing the switching without gate energy recovery usually takes less time than with gate energy recovery. Moreover, the switching characteristics of the power switches with gate energy recycling, is usually softer than without gate energy recycling.

Referring to Fig. 22 dead time (1002) - if recycling is needed, it is best to add delay between the turn off of Φl-2 and Φl-2 A when they are turned OFF. This way - the set of switches connected to Φl-2 undergo fast turn-OFF, and the set of switches connected to Φ1-2A may undergo gate energy recycling process. Similarly, for the dead time (1003) it is best to add delay between Φl-1 turn-OFF and Φ1-1A turn-OFF. This way - the set of switches connected to Φl-1 undergo fast turn-OFF and the set of switches connected to Φl-1 A may 5 undergo gate energy recycling process. The subject of gate energy recycling, as far as it involves the disclosed invention is discussed later, and several methods are disclosed suitable for performing this task for the various disclosed converter technologies.

0 Fig. 23 presents typical waveforms that may be measured at various test points of the disclosed topology in the 4th variant operating in parallel and anti-phase (Fig. 19) and with low value of Q in the charging path. The drawing also suits the topology disclosed in Fig. 21. These typical charge and discharge capacitor current and voltage may be measured at the

5 capacitors of Fig. 19 or Fig. 21 cells, when selecting input inductors that cause a low value of Q (Quality Factor) for the charge Stroke (1100) R-L- C equivalent circuit (formed by, for example Ll (854), the parallel connected capacitors C(k) and the ESR's of the switches connecting them in parallel, like (865) and (867) of Fig. 19).

,0 The charging stroke current waveform (1102) is characterized by a single zero crossing point (1103) at the beginning of the charging stroke (1100), and an exponential- like decay of the current waveform, in accordance with Eq. 4. The exponential-like decay do not reach zero exactly, and some control decision must be made in order to terminate the stroke, other than detect the

:5 zero-crossing instant. A typical control law for terminating the charging stroke is to compare the charging current with a low value (1110) and end the stroke when the capacitors' current has reached this value and cross it from above.

An example of such an instance is (1104). A different control law that 10 may be used is to use a predetermined charge and discharge stroke times (and thus - fixed frequency of stroke switching). The charge stroke time is chosen in advance to match the time it takes the charging current to diminish significantly. Both of these disclosed control laws disturb the ZCS process of the power switches, and only almost-ZCS transitions are now possible. The discharge stroke denoted (1105) follows the same explanation provided for Fig. 20.

Fig. 24 presents the utilization of the 4th variant of the disclosed invention topology with an Auxiliary connection, useful for voltage tuning. Fig. 24 discloses further improvement to the invention, which extends its capability to include continuous regulation of a desired signal, like the output voltage. This extension is first disclosed as an expansion of the 4th variant topology disclosed at Fig. 9, and later (in additional drawings) presented for other cases. The topology (similarly to Fig. 9) has an input inductor (1152), and output inductor (1153) and a basic cell (1150) which includes a capacitor and power switches.

The first series-connection power switch in the topology (1154) is now connected to an Auxiliary input (in accordance with the block diagram of Fig. 2) (1151) labeled AUX. At this terminal one can connect a fixed or variable voltage source and using it - one can perform various tasks of tuning and regulation during the discharge phase. The voltage source applied at the AUX input should be able to provide\absorb power. It is beneficial to apply only a small voltage at the AUX input, just enough to allow the desired tuning or regulation function to take place. The AUX input is incorporated during the series- connection phase of the operation of the disclosed converter.

Therefore - the current drawn of sank into it relates to the higher-voltage side of the converter (the input at Step- Down or the output at Step-Up) which has the lower current. Due to that the AUX input has both low voltage (related only to the tuning-range) and low current (the current drawn/sank at the high voltage side of the converter) - therefore - it processes only a low amount of power. Thus - the effect of this tuning method on overall efficiency is small, and in most cases - negligible. As further disclosed in a later drawing, the voltage source applied to the AUX input may be a tunable power supply, a duty-cycle controlled power electronics system (like a buck converter), etc..

Fig. 25 presents the utilization of the 4th variant of the disclosed invention topology with an Auxiliary connection, useful for voltage tuning, in accordance with Fig. 2 block diagram. This is the expansion of the topology disclosed in Fig. 19 to include the tuning input AUX.

The method and principle disclosed in Fig. 24, is used to form the converter disclosed in Fig. 25, which is an embodiment of the block diagram disclosed in Fig. 2. Fig. 25 may also be seen as an expansion of Fig. 19s¹ topology.

In Fig. 25, two networks (Network A, (1200) and Network B, (1201)) work in parallel and anti-phase, much like in Fig. 19. An AUX input (1202) is connected to the first power switch of the series connection of each network, (1203) and (1204). When the topology of Fig. 25 is operated, the following relation exists between Vs (1206), Vo (1205) and V_AUX , the voltage applied at the AUX (1202) terminal (neglecting ohmic losses throughout the circuit):

Where N is the number of basic cells connected in the topology. The conversion gain of the disclosed topology is thus:

G = ÷f = N + ÷F

V. K AUX Eq. 6

S S

Fig. 26 presents the range of gains one can obtain when using the fine-tuning AUX input at topology Fig. 25, and sweeping VA_UX from 0 to 2VS.

For Example, when operating the topology with 0<V_AUX <VS, the gain (and tuning) range is N<GKN+1.

Control of the internal power switches of the converter disclosed in Fig. 25 may be done similarly to the way described for the converter of Fig. 19, see Fig. 20 for typical waveforms and control signals.

Fig. 27 presents the topology of Fig. 25 with Fine voltage regulation and a control loop for performing output voltage regulation. Three possible options for the voltage tuning at the

Aux input are included. Fig. 27 discloses a circuit and method for implementing output voltage, Vo (1301) line and load regulation, using the topology of Fig. 25. The disclosed circuit comprises of two networks of the 4th variant of the disclosed converter including an AUX input (see Fig. 24), named Network A (1302) and network B (1303), which operate in parallel and anti-

5 phase as described above. The Auxiliary input AUX of the two networks is connected to the output port (port 3) of a tuning network. The input port (port 1) of the Tuning Network (1304) is connected to Vs (1300). The ground port (port 2) of the tuning port is connected to Ground. The tuning port has an additional tuning terminal (port 4) used to fine-tune its output voltage. Three options are possible for the tuning network - Tuning Network

0 (1304), which will be disclosed later.

The Tuning Network (1304) is controlled using a control loop (1307), which is a PID controller. The control loop receives as input a Vref reference signal (1321), and makes Vo (1301) track this reference signal. The Control network error signal is found at the 5 output of the first summing node (1320). This error signal is integrated using an integrator (1322) and summed up with itself by the 2nd summing node (1318). Therefore - creating the proportional and integral parts of the PID controller. The differential part is produced by a Capacitor Double-Sampling block (1315), in a manner explained hereafter.

\0 The selector (1308), (1309) represents two options for non-direct sensing of the input or output current. If selection (1308) is implemented - the output current is sensed. If selection (1309) is made - the input current is sensed.

Current sampling is done by taking a Double sampling of the basic cells' capacitors voltage immediately before and after a Stroke transition (i.e. before and after time instant

^•5 (908) or (914) of Fig. 20). Therefore the CDS (1315) emulates the following equation:

^•* C ~~ ^ L j, *^• V C, before transition "cqftertnmsition/ iiq. 6

Hence, using the CDS (1315) - we obtain the differential part of the PID controller (1307), !0 which is equivalent to current mode control. The CDS is operated using two sampling control signals, Samplel and Sample2 (1311), firing before and after the stroke transition instant. The CDS output is updated after the 2 consecutive samples. The signal at the CDS (1315) output (1316) is the difference between the signals (1312) and (1313) held on the two hold capacitors. These signals are sampled using the CDS control signals (1311), disclosed in Fig. 28.

5 Fig. 28 presents the waveforms sampled by the CDS module incorporated into the control loop of Fig. 27, when the Capacitors voltage sampling is done on the output side of the Step-Up converter described in Fig. 27. The CDS control signals Samplel (1352) and Sample2 (1353) are disclosed, along with the sampled capacitors voltage signal (1354). This is

0 true for the connection (1308) of Fig. 27 where the capacitors voltage is sampled at the output port of the converter, so the measurement is done while all the capacitors are in a series combination - therefore - we measure the sum of voltages of the capacitors, plus V_AUX • The CDS takes the difference between the two samples, therefore - V_AUX is canceled out and the signal injected into

5 the control loop of Fig. 27 by the CDS (1316) is proportional to the current flowing in the discharge stroke. If option (1309) is used at Fig. 27, the

CDS may still be used, but this time - the measurement performed is proportional to the input (charging) current.

:0 Fig. 29 presents the waveforms sampled by the CDS module incorporated into the control loop of Fig. 27, when the Capacitors voltage sampling is done on the input side of the Step-Up converter described in Fig. 27. These are the waveforms that exist in Fig. 27 for operation under option (1309) where the CDS samples the input capacitors voltage, (Vs-VLl),

J5 marked in the drawing as (1400). The Average voltage at the sampling point is Vs (1401). The drawing further discloses the sampling control signals, Sample 1 (1406) and Sample 2 (1407), which operate the CDS, and the output signal from the CDS (1404). The CDS output signal (1404) is found in the circuit of Fig. 27 at node (1316). The 1st sample is performed just before the dead time

50 (1402), and the 2nd sample is performed just after the dead time (1403). Note that the CDS output is updated at the end of the Dead time periods, after the 2nd sample, (1405).

Fig. 30 details typical implementations of the tuning networks used in Fig. 27 and in Fig. 31. Fig. 30 discloses the remaining block of Fig. 27 that was not addressed until now - the Tuning Network (see Fig. 27, (1304)). Referring to the Tuning Network 1, a power SPDT switch (1450) connects port 3 to either port 1 or port 2, according to a control command at port 4.

5 Usually - the control command is a high speed PWM signal, with switching frequency higher than the strokes rate. The average contribution of Tuning Network 1 to the output voltage is avg(V_Aυx)= D-Vp_{0n 1}+(l-D)-V_pOrt2. Tuning network 1 does not introduce any additional filtering elements, thus - it allows for the fastest closed-loop dynamic performance.

[0

The Tuning Network 2, which constitutes a Buck converter. This converter has an input port 1, a common port 2 and an output port 3, and a control port 4. A power SPDT switch, (1451) is controlled by a digital signal at port 4, causing it to connect either port 1 or port 2 to one terminal of the

.5 inductor (1452). The 2nd terminal of the inductor (1452) is connected to the output port 3 and one terminal of the filter capacitor (1453), whose other terminal is connected to the common port 2. This tuning network is similar to Tuning Network 1, except for its output filter (1452) and (1453). The network is operated in a similar manner to Tuning Network 1, although it is slower (due

'.0 to the output filter) and thus - slows down closed loop dynamic performance. The switching signal controlling the power switch (1451) is usually a PWM signal, which can have a frequency higher or lower than the stroke repetition rate of the invented converter networks it is connected to.

,5 Further with reference to Fig. 30, Tuning Network 3 constitutes a general controlled (tracking) power supply/amplifier (1454), having an input port 1, a common port 2 (usually Ground), an output port 3 and a control/track port 4. The power supply implementation can be arbitrary: a linear power regulator, a switch-mode power supply with tuning control like Boost, SEPIC, Buck, Buck-Boost, etc. Each

0 implementation has an impact on overall system performance like efficiency, dynamics, tuning range and so on.

Fig. 31 presents the Step-Down variant of topology Fig. 27 with Fine voltage regulation and control loop. In a manner similar to Fig. 27, Fig. 31 discloses the Step-Down variant of the invented converter in its 4th variant. In the drawing, The voltage source Vs (1500) and charge stroke inductance L2 (1501) are connected to the right port of the dual network converter, and the load (1504) with output voltage Vo (1503) is connected through the discharge inductor Ll (1502) on the left of the drawing. The conversion ratio may be tuned between l/N>G>l/(N+V_Aux /VO) . As in Fig. 27, two converter networks of Fig. 24 , denoted here (1506) and (1507), are operated in parallel and anti-phase. A Tuning Network (1508) is connected to the AUX terminal of both Network A and Network B, as in Fig. 27.

The tuning network input, port 1, is connected to Vo (1503), its common or Ground terminal, port 2, is connected to Ground, the output of the tuning network (port 3 of (1508)) is connected to the AUX terminal of the converter's network A and network B. The tuning (control) port of the tuning network (port 4 of (1508)) is connected to the output of a PID controller (1509). The PID controller operate in the same manner that a similar block is operated in Fig. 27. Like in Fig. 27, two possible sample points are available for the CDS module (1514) - these are the input (1510) sample point or the output (1511) sample point, enabling sensing of the input or output current.

Many applications exist where ground separation between input and output may be required. For instance - audio applications require the separation of ground loops in order to reduce low frequency noise in the system. The disclosed invention supports ground loop separation, and is capable of handling a certain common-mode voltage (the amount of common mode voltage the invented converter can handle depends on the actual implementation of its power switches and control circuitry).

Fig. 32 Ground Separation using the 4th variant of the invented converter topology having an AUX input (see Fig. 24), in the Step-Up configuration. Fig. 32 discloses an embodiment of the invented converter operated as a Step- Up converter, with the ground separation quality. Similar techniques shown in this drawing may be readily implemented, i.e. in the examples shown above. The input circuit is reference to one ground (1552) while the output circuit of the invented converter is reference to another ground (1551). Between the two grounds - a Common Mode voltage VCM (1550) may be present (the voltage

5 source (1550) in the drawing represent the Common Mode voltage, which is, in most cases due to noise or parasitic circuit elements). The Common Mode voltage is limited by the blocking capability of the power switches and control circuitry used in the topology and their exact implementation. The AUX input (1554), as for the previous examples, refers to the series connection of basic

0 cells, therefore - the Auxiliary power source, V_AUX (1553), is connected between the output ground (1551) and the AUX port (1554). Implementing ground isolation for the parallel and anti-phase expansion in the Step-Up and Step-Down topologies follows directly from this drawings' example.

5 Fig. 33 Shows an Example of the Interleaving of the invented converter.

Multiple instances of the Step-Up converter are synchronized and interleaved. Fig. 33 discloses and demonstrates interleaving of the disclosed converter. In the drawing three instances of the Step-Up topology (like Figs. 19, 25, 27, etc.) are interleaved to achieve various benefits (like reduction

:0 of inductors' ripple current, improved dynamics, etc.). The drawing demonstrates interleaving of three converters. It is possible to interleave less or more than three converters, as long as additional synchronization pulses are provided. It is also possible to interleave the Step- Down implementation of the disclosed invention.

>5

Each of the instances of the disclosed invented converter, (1606), (1607) and (1608), includes two networks: Network A (1609) and Network B (1610) that operate in parallel and anti-phase, as explained above, see for example Fig. 19. The three interleaved converters use three input side inductors: LI l (1615), L12 (1616) and L13 (1617) and a

50 single output inductor L2 (1603).

Three input inductors are required in order to maintain, for each interleaved converter the charge stroke current waveform with zero- crossing termination (see Fig. 20, (906)) which is useful for internal control of each converter network, as described above. The output inductor may be shared, as Fig. 33 discloses, or - conversely - three separate output inductors may be used, one for each instance of the disclosed invented converter. Moreover - Integrated magnetics may be used instead of discrete inductors, for the interleaved converters, much like in the prior- arts' 'Interleaved Boost' or 'Interleaved Buck¹ converters.

The stroke Synchronization block (1611) produces three Start signals: Startl (1612), Start2 (1613) and Start3 (1613). The start signals tell each interleaved converter when to initiate the Charge stroke.

Fig. 34 illustrates Interleaving: Start signals instructing each interleaved converter to start a charge stroke, and the resulting current waveforms in Network A and Network B of each interleaved converter. Fig. 34 presents the waveforms for the Interleaved topology of Fig. 33. Each Start signal (Startl, (1652), Start2 (1653) or Start3 (1654)) triggers a Charge stroke by the converter its' connected to. Startl (1652) initiates the charge stroke of the 1st interleaved converter, who's current waveform is given by (1655). The discharge stroke follows immediately after the charge stroke (1660).

Afterwards, the 1st interleaved converter (Fig. 33, (1606)) waits for another Startl pulse. The 2nd start pulse, Start2 (1653) makes converter 2, (Fig. 33, (1607)) start a charge stroke. The current pulse of the charge stroke is given by (1656). The discharge stroke follows the charge stroke. The 2nd converter than waits for another Start2 pulse. This is also true for Start3 (1654) and the 3rd converter, (1608) of Fig. 33. (1657) is the charge stroke of the 3rd converter and its discharge stroke (1659).

Fig. 35 discloses a control scheme for production of Switch-control pulses (Φi-j) to use with the converter of Fig. 21. The converter is operated with low-Q in the charge stroke, resulting in Fig. 23 s' waveforms. The drawing discloses an Open-loop control, with fixed stroke timing and a Start input (enabling interleaving). This control scheme enables to control the Step-Down converter of Fig. 21 without Charge-stroke zero-crossing detection, if low Q values are used in the charge stroke (by choosing proper Ll, the capacitances of the network and the power switches ON resistance). The current waveform obtained in at the capacitors is that of Fig. 23. When the 5 low-Q condition is met, a simple, fixed and predetermined stroke times may be used for the charge and discharge strokes. The control topology disclosed in Fig. 35 enables fixed stroke time control.

The controller may comprise a digital counter (1700) that keeps track of 0 stroke time, a logic device (CPLD, FPGA, etc.) (1701), a Reset circuit comprised of Cl (1721), Rl (1722) a PNP device and a pull-up resistor R2 (1724). The logic device (1701) supervises the counter and produces the proper control signals for the power converter (Fig. 21) switches, i.e. - the signals Φl-1, Φl-1 A, Φl-2, Φ1-2A, Φ2-1 and Φ2-2. This is done according to the 5 truth table (1718).

Two clock generators may be used in the system, Fl is a fast clock generator (1702) used to drive the CLK inputs of the counter (1706) and the Logic Device. The second clock is a slow stroke timing clock (1703). When this clock ticks - the \0 logic device (1701) is signaled to start a charge stroke for Network A of Fig. 21. The stroke timing tick may be triggered by an external Start pulse (1704). An example for the implementation of the slow, Stroke timing, clock (1703) is given by (1725).

.5 When power is applied to the control circuit (VCC (1720) turned on) - a reset pulse resets the Digital Counter (1700) to output Q=O. The logic device (1701) is also reset at this stage. After reset, the digital Counter (1700) is halted until a START (1709) command is given or a LOAD (1711) command is issued. Both the START and LOAD commands are synchronous inputs that update the counter atO the clock rise time. The load command causes the digital counter to load input D (1707) into its internal register and output terminal Q (1708) and halt, waiting to a START (1709) command. Additional RESET commands may be issued to the counter (1700) by the logic device (1701) through the RESET CMD (1717) port. This is useful, for example, when the user issues a Functional Input (1714) to shut down the power converter.

When the digital counter has reached Q=I the controller stops and waits for a Start pulse to reach the logic device (1701) through connection (1705). The 5 start pulse enables counting in the counter until the next time the counter is at Q=I, or a RESET or LOAD conditions has occurred.

When Q=2 the system initiates the charging stroke of Network A (discharge on Network B), which takes the up to the predetermined count Q=Nl. Than the system

0 transits to a discharge state on Network A (charge on Network B). after a while, when the 2nd charge stroke has passed, at the predetermined count Q=N2 the system transits again from the 2nd charge stroke to state Q=I. There it halts and waits for another Stroke Timing Clock pulse (1703) to reach the logic device (1701) through (1705). The counts Nl and N2 are determined in advance

5 and are programmed into the control logic of (1701). Nl and N2 are related to the charge stroke times for Network A and Network B.

Synchronizing the Charge strokes to an external Start pulse (1704) is possible by tuning F2, the Stroke timing Clock rate to slightly less than the rate of Start pulses (1704).

-0

Fig. 35 may be used in the Step-Up version of the disclosed converter as well, with adaptation only to the Power Switch Control Truth Table (1718). Other ways may exist for the implementation of this control scheme, too, although this method gives the designer plenty of flexibility and also may be

:5 implemented in an ASIC with relative ease. An additional control scheme which may be used to control the Charge-stroke timing and produce the required power-switch control signals is disclosed in Fig. 36. The control scheme example is drawn for the Step-Down configuration of the disclosed converter, according to Fig. 21. The adaptation of the disclosed scheme to the Step-Up

10 or any other embodiment of the invented converter readily follows from the scheme drawing.

Fig. 36 presents an example of a Step-Down configuration (like in Fig. 21) including the entire control circuitry required for operation of the disclosed invention, with automatic stroke timing control based on stroke current sensing to detect the zero crossing point which ends the charge stroke. Fig. 36 may be explained as follows: The Step-Down converter (1750) shown in the drawing, has two internal networks (Network A, (1751) and Network B (1752)). The positive terminal of the low voltage side of both networks is connected to

(1753) and to L2 (1758) and the load and Vo (1755). The high voltage side is connected together (1773) and to the charge inductor Ll (1757) and the power source Vs (1756). Both input and output of the Converter (1750) share the same ground (1754).

While one of the converters' internal networks (A (1751) or B (1752)) is in the charging state (with all of its cells connected in series) the other network is in the discharge state, therefore their operation is in parallel and anti-phase.

The charge current is being sensed by a current sense amplifier or Current Sensor (1759), which is connected between the output Vo (1755) and the series-connection port of the networks (1761). The sampled Charge-Stroke current (1760) (having a shape resembling (1004) of Fig. 22) is compared to zero by a Comparator (1762) which has a small hysteresis (for flickering prevention). The output of the comparator is logic T if the zero crossing of the current is detected, and logic '0' if the current is larger than zero (plus the hysteresis window). The output of the comparator (1762) is fed into a Rise/Fall detector (1763) which emits a short ¹T pulse for every transition in the comparator's output.

Therefore - at the output of the Rise/Fall detector a pulse appears at instances of change at the comparators' output. These short pulses are fed into a One-Shot circuit (1764) having a time constant Tos, which conditions the pulses. It is required for masking high-speed oscillations that may be present at the output of the Comparator (1762) and Rise/Fall detector (1763). The One-Shot also extends the width of the pulses to Tos.

The output of the One-Shot is driving a logic frequency divider (1765), which may be easily implemented by an ordinary D-type Flip-Flop. The output of the logic frequency divider (1765) is in the stroke-switching frequency. The stroke-switching signal is fed, through a OR gate (1767) to a rise/fall detector (1769) and from there - to the Stroke indicator input (1771) of a logic device (1770). The logic device uses the pulses fed to its Stroke indicator input (1771) to produce the control signals (1775) to the power switches of the converter (in a manner similar to the way the logic device of Fig. 35 (1701) produces similar pulses). The logic device (1770) also produces an Osc RESET (1772) every time it initiates a charge stroke. This causes the Free-Running Oscillator with Reset input (1766) to start a new cycle (and output logic ¹O'). The Free-Running Oscillator and why it is needed is explained hereafter.

If no zero-crossings are detected by the comparator (1762) (due to, for example, low load conditions) there will be no state changes at the output of the frequency divider (1765) and therefore - no pulses at the 1st input of the OR Gate (1767). This will cause the converter to stop switching. In order to prevent this condition, a free-running oscillator is connected to the 2nd input of the OR Gate (1767). The Free running oscillator may be RESET by a RESET signal (1768). When the oscillator is RESET, it returns its output to ¹O' and starts a new timing cycle. The frequency of the free running oscillator is predetermined by the designer to be the lowest stroke repetition rate desirable.

Therefore, as a new charge stroke is initiated by the logic device (1770), the free- running oscillator (1766) is reset to ¹O¹. If a current zero-crossing is detected by the comparator (1762) before the logic ¹O' part of the oscillator (1766) has elapsed - an indication would be sent through the OR Gate (1767) to the Stroke Indicator (1771) (in the way described above) and that would cause the logic device (1770) to RESET the oscillator once again. However - if a current zero-crossing is not detected by the comparator (1762) before the logic ¹O' part of the oscillator (1766) has elapsed - the oscillator will emit a pulse at its output (1776), which will be fed through the OR Gate (1767) into the Stroke Indicator (1771) input of the logic-device, thus forcing an end to the charge stroke.

The Free-Running Oscillator (1766) may also be beneficial in order to ensure the start up of the circuit from an OFF state, as it ensures that no matter what the load conditions are (what current or power the load draws) - the converter will switch at a frequency equal, at least, to the Free-Running Oscillators' frequency.

A Functional Input (1774) may be connected to the Logic device (1770) which enables shut-down control. When a signal exist on this input - the Logic device (1770) may disconnect all or some of the converters' power switches, causing a load, line or both to be disconnected.

Another feature of the present invention is the adiabatic gate drive for the power switches of the invented converter. For various applications, mainly low power or high frequency switching applications, the converters' switches gate drive may be one of the important factors for the overall power losses. Many methods exist for recovering most of the gate drive energy. These methods fall under the category of 'adiabatic gate drive¹ techniques. The key principle which enables the use of adiabatic gate drive is that the converters' waveforms allow slow turn on and turn off of the power switches, usually called soft-switching.

In the disclosed invention, the current flowing through all power switches has two zero-crossing instances that coincide with the desired switching moments. Also - the wave shape of the said current is smooth near the switching instances. Therefore - soft switching does not degrade efficiency considerably, and ample time may be allocated to slow turn-on and turn-off of the power switches without compromising efficiency too much. This time is used by the adiabatic gate driver in order to slowly charge the gate capacitance, in a way that enables gate energy recovery. As long as the recovered gate energy is greater than the energy lost due to soft- switching at the drain-source channel, adiabatic switching is beneficial, and increases overall efficiency.

In principle, the energy recovered from the gates by adiabatic charging is proportional to the ratio of the allocated gate charging time and the R-C time constant of the gate capacitance and total parasitic resistances of the charging path. On the other hand, for a specific resonant cell component values and a specific switching frequency, increasing the gate charging time means increasing drain-source switching losses as larger deviations from ZCS are present. Therefore - an optimization of the gate charging time must be performed in order to find the best recovery to loss ratio. Decreasing the switching frequency and/or lowering the resonance frequency of the basic resonant cells allows more time for the soft-switching process and lower losses during this process, but effects components size and weight.

For the disclosed invention, most adiabatic gate charging schemes are applicable, including resonant gate drive through an inductor or transformer, scanning a series of voltage sources differing by a small amount, charging the gate through an inductor connecting it to a high frequency switching voltage source, etc.

When applying the scanning method, where slightly differing voltage sources are connected to the gate, increasing its voltage gradually, the disclosed invention has most of these required voltage sources readily available at, for example, the Vout(k) outputs of Fig. 7 and Fig. 8, etc., making the use of this method convenient.

Fig. 37 presents three implementations of the power switches gate drivers, in a manner that recycles the gate energy. Step-by-step charging, resonant charging and gate-feedback charging schemes are presented. Fig. 37 presents various adiabatic gate charging techniques. Other adiabatic gate charging techniques exist and may be utilized for the invented converter. Fig. 37 part 1 is the prior art, customary adiabatic gate charging approach. The MOSFET (1851) gate is connected through a scanning multiplexer (1850) to a series connection of small voltages (1852), each equals to W volt. The required gate voltage range is divided into M+l such voltage quantities, from 0 to M- d V. In order to charge the gate, one must scan the series connected voltage sources from the first (0 volt) to the last (M- d V volt). At each stop, the multiplexer waits in that state for a while, until the current flow to the gate capacitance practically stops. A Larger number of steps may cause lower energy losses. Similarly - for discharging the gate, one should scan in the same manner the multiplexer inputs from the last (M-dV volt) to the first (0 volt). Fig. 37 part 2 presents another topology for resonant gate charging. The MOSFET (1853) is connected to an inductor L (1862). There are three voltage sources that may be connected to the gate (0, V/2 and V). V/2 may be produced by a capacitor instead of an actual voltage source. In proper operation, this capacitor will be charged automatically to approximately V/2. During the stable states either switch 1 (1854) or switch 4 (1855) are connected, holding the gate voltage at V or 0 respectively. In order to charge the gate, one disconnects switch 4 (1855) and connects switch 2 (1856). A resonant charging pulse takes place, charging the gate capacitance to a voltage close to V, through the inductor L (1862).

The diode (1858) prevents the resonant current pulse from reversing and thus the gate voltage is held. Slightly later, switch 1 (1854) is turned on, shorting the gate voltage to V volt. Similarly, in order to discharge the gate, switch 1 (1854) is disconnected, and switch 3 (1857) is turned on, discharging the gate via a resonant pulse of the gate capacitance and inductor L (1862). When the gate voltage reaches close to 0, diode (1859) stops the resonant current flow, thus holding the gate voltage close to 0, until switch 4 (1855) is connected, shorting the gate to 0 volt.

The resonant characteristics of the charging and discharging helps recovering most of the energy stored in the gate. Known prior art for resonant gate charging uses transformers for interfacing with the gate. This method is better than the prior art in two aspects: if a floating gate is not needed, than this method is more economic as it saves the need for a transformer. For VLSI implementation this is a great advantage. The other aspect is that this method may hold the gate voltage for indefinite duration, while the transformer solution is very limited and can hold the gate voltage only for a short duration, before the transformer saturate.

Fig. 37 part 3 presents a feedback approach to the gate charging issue. The power MOSFET (1863) gate is connected through an inductor L (1867) and a high speed SPDT controlled switch (1866) to a voltage source V (1864). PWM control (1865) causes the gate voltage (1870) to track a reference voltage Ref (1868). Therefore - the gate driving circuit implements a high speed micro-power switch-mode converter with output filter formed by the inductor L (1867) and the MOSFET gate capacitance. This topology may achieve high efficiency of the

5 gate charging and discharging. Moreover, the PWM pulses (1869) may be calculated and recorded in a memory and fed into the SPDT switch (1866) without using feedback. This approach may be attractive for VLSI implementation. The PWM pulses must be of very high frequency, with respect to the switching frequency of the MOSFET (1863). However, switching PWM only appears at this

0 circuit at the switching time of the MOSFET (1863) and at the rest of the time the SPDT switch is held either at 0 volt or at V volt.

The methods presented in Fig. 37 may be used for controlling other power or signal switches whose gate is capacitive in nature, for example IGBTs, 5 or for other capacitive load applications.

The topology presented in Fig. 25 includes an AUX Auxiliary input, which may be used, through the means described above, in order to perform fine-tuning or regulation of the output voltage from the disclosed converter.

O

Fig. 38 presents another embodiment, option, or extension of the topology of Fig. 25, which provides both fine-tuning and coarse-tuning of the output voltage, Vo (1907). In this drawing, two networks, Network A (1200) and Network B (1201) are operated in parallel and anti-phase. Both networks are connected to the AUX

.5 input (1906) which allows for fine tuning of Vo (1907), through the means disclosed above. In order to provide also coarse gain tuning (selection), instead of a single connection to the output port (1905), each of the m last cells is equipped with an Output bus connecting switch Sol(k) (1902), for Network A (1900), or So2 (1903), for Network B (1901). Each of the bus connectingO switches are controlled by a special control signals Sol(k) (1904) or So2(k) which are derived from Φ2-1 or Φ2-2 respectively, in the following manner:

1. If the gain selected is N+l, then Sol(m) = Φ2-1 and So2(m) = Φ2-2, and for every i≠m, j=[l,2]: Soj(i) = 0 (turning OFF their respective switches). 2. If, for example, the gain selected is N, then Sol(m-l) = Φ2-1 and

So2(m-1) = Φ2-2, and for every i≠(m-l), j=[l,2]: Soj(i) = 0 (turning OFF their respective switches). 5

3. If, for example, the gain selected is N-I, then Sol(m-2) = Φ2-1 and So2(m-2)= Φ2-2, and for every i≠(m-2), J=[1, 2]: Soj(i) = 0 (turning OFF their respective switches).

And so on... 0 m may be any number between 1 and the total number of cells of Network A or B.

The coarse gain selection may be done dynamically. For instance - when the input supply

Vs is high (like in the case of a fresh battery or fuel-cell), the control system may decide that N-I stages are enough to supply the desired Vo. 5 Therefore - control rule number 3 above may be selected. When Vs drops (this can happen if the battery or fuel-cell is depleted) - the system may decide to increase the gain by selecting rule number 1 above. This is an example of how the coarse gain selection is dynamically chosen by the control.

0 This form of coarse-gain selection (control) may also be utilized with the disclosed converter's topologies that do not have an AUX input, or with the AUX input connected to Vs or even Ground, depending on the application.

Notes: In some of the drawings, part numbers are indicated each with a number in

,5 parentheses () within that part or close to it.

A part may have different numbers in different drawings; it is to be understood it is the same part which could have the same number, unless different properties are associated therewith. For example, the control may be assigned the numbers 052, 060 ..., the power stages the numbers 050, 061, the power source Vs the numbers 053, 063, 300..., etc.

O

Various embodiments of the present invention will become apparent to persons skilled in the art upon reading the present disclosure together with the drawings. Other embodiments of the invention may be implemented, without departing from the spirit and scope of the present invention.

Claims

Claims

1. ADC to DC converter comprising building blocks removably connected to each 5 other, wherein each block includes generic power-processing switching means with means for connecting their energy storage elements in series or in parallel.

2. The converter according to claim 1, wherein the energy storage elements each comprises a capacitor or a capacitor in series with an inductor.

0

3. The converter according to claim 1, further including control means for initiating a series connection for a time period of a series stroke wherein the storage elements are connected in series, or a parallel connection for a time period of a parallel stroke wherein the storage elements are connected in parallel.

5

4. The converter according to claim 1, further including a dead time interval wherein the storage elements are not connected in series or parallel.

5. The converter according to claim 4, wherein using the dead time interval tO in a sequence for performing ZVS or ZCS for all switches of the converter.

6. The converter according to claim 4, wherein using the dead time interval for allocating sufficient time for adiabatic/energy recycling gate drive.

>5 7. The converter according to claim 4, wherein using the dead time interval for allocating sufficient time for Soft-switching to take place for the power switches of the converter.

8. The converter according to claim 1, wherein the blocks are connected to each

50 other to form a chain which allows translations or transitions between series-stroke and parallel-stroke of the energy storage elements.

9. The converter according to claim 1, further including means for performing transitions from series stroke to parallel stroke and vice versa in a manner that minimizes losses during the transition.

10. The converter according to claim 9, further including means for minimizing losses during the transitions by using current waveform shaping, using for example inductors connected in series with the source or load, during the charge and discharge stroke.

11. The converter according to claim 9, wherein the means for performing the transitions include inductances in series with the storage elements.

12. The converter according to claim 1, wherein the converter has a charge stroke wherein the energy storage elements are connected to an energy source and a discharge stroke wherein the energy storage elements are connected to a load, and wherein in one of the above strokes the elements are connected in series and in the other stroke - in parallel.

13. The converter according to claim 10, wherein the charge and discharge strokes each takes about the same amount of time.

14. The converter according to claim 10, wherein the frequency of the charge and/or discharge strokes is about equal to the resonance frequency of the converters' reactive elements (capacitors and inductances).

15. The converter according to claim 10, wherein the frequency of the charge and/or discharge strokes is significantly higher than the resonance frequency of the converters' reactive elements such as capacitors and inductors.

16. The converter according to claim 1, further including means for separating high current associated with a low voltage side of the converter from the lower current associated with a high voltage side of the converter.

17. The converter according to claim 1, wherein one of the terminals of the series-connection is used as an Auxiliary connection (AUX), to enable power-efficient fine tuning of the overall conversion ratio of the whole converter.

18. The converter according to claim 1, further including means for applying a tunable voltage source to an Aux terminal to allow for continuous conversion ratio tuning.

5 19. The converter according to claim 1, further including two basic networks of cells operating in parallel and in anti-phase.

20. The converter according to claim 19, further including means for shaping the input port or output port current ripple, to reduce it to a low level.

0

21. The converter according to claim 20, wherein a common inductor at the input serves the two networks and another common inductor at the output serves the two networks, and selecting each of the inductors independently to have ω₀ much lower than or close to the stroke repetition rate.

5

22. The converter according to claim 20, wherein the controlling means use fast current-switching (handover) between the two networks.

23. The converter according to claim 1, further including means for

,0 implementing a current-handover behavior for one port (two terminals) and zero-current switching for the other port (two terminals).

24. The converter according to claim 23, wherein implementing a charge-stroke with zero-current switching and a discharge-stroke with load-current-switching (handover) '.5 or a discharge-stroke with zero-current switching and a charge-stroke with source-current- switching (handover).

25. The converter according to claim 1, further including means for implementing a topology with input-output isolation.

SO

26. The converter according to claim 1, further including means for dynamically changing the number of series-connected basic cells in order to select different gains (N+1,N,N-1,..) during a converter operation.

27. A DC to DC converter comprising building blocks removably connected to each other, wherein each block includes generic power-processing switching means with means for connecting their energy storage elements in series or in parallel, wherein the switching means comprise at least three power switches 5 and the energy storage elements each comprise a capacitor.

28. The converter according to claim 27, further including a first series inductor which is used when connecting the storage elements in parallel and a second series inductor which is used when connecting the

0 storage elements in series.

29. The converter according to claim 28, wherein the first inductor is so devised as to withstand the voltage and current found at the low-voltage side of the converter, and the second inductor is so devised as to withstand the

5 voltage and current found at the high- voltage side of the converter.

30. The converter according to claim 29, wherein the value of the first and second inductors, and of the switches resistance, are so devised as to achieve a desired shape of current waveforms at the low voltage and high voltage sides of the converter.

:0

31. The converter according to claim 27, implementing either a step up or step down mode converter, wherein in the step up mode the storage elements when in series are connected to the load and when in parallel are connected to the source, and in the step down mode the storage elements when in series are connected to the source and when in parallel are

15 connected to the load.

32. The converter according to claim 27, further including means for implementing a bi-directional converter wherein each side may be either sourcing or sinking power, instantaneously, to function as a source or load. O

33. The converter according to claim 27, further including means for connecting an input to the lower terminal of a series connection, either before (365) or after (364) the inductor Ll in Fig. 9, thus including or excluding it in the series-connection current path.

34. The converter according to claim 27, further including two networks connected in parallel and operated in anti-phase, wherein at any given time one network is feeding the load and one network is being charged from the source.

5

35. The converter according to claim 27, further including means for dynamically changing the number of cells connected in series during converter operation to enable the use of power switches rated for lower voltages.

.0 36. The converter according to claim 27, further including means for connecting the output port at the output of the Nth¹ cell, (N-l)th' cell,., etc. in order to provide high- efficiency coarse-regulation/tuning.

37. The converter according to claim 27, further including means for connecting [5 all the cells in parallel during the parallel-connection stroke.

38. The converter according to claim 37, further including means for connecting, for the series connection stroke, only a smaller group of series-connected cells, to achieve a lower conversion gain and controlling the gain in integer steps.

.0

39. ADC to DC converter comprising building blocks removably connected to each other, wherein each block includes generic power-processing switching means with means for connecting their energy storage elements in series or in parallel, further including control means for initiating a series connection 15 for a time period of a series stroke wherein the storage elements are connected in series, or a parallel connection for a time period of a parallel stroke wherein the storage elements are connected in parallel, and further including control means for performing an automatic adjustment of the stroke time based on sensing the inductor current (equivalent to inductor energy) during the 30 stroke, in order to achieve ZCS at the strokes' end.

40. The converter according to claim 39, wherein the control unit includes means for detecting the actual and specific rate at which ZCS conditions appear for strokes and tunes the strokes time intervals in order to achieve that rate.

41. The converter according to claim 39, wherein the control unit includes means for implementing an operational cycle comprising two strokes and an optional dead time after each stroke, wherein the stroke time is determined

5 automatically and the dead time may be selected.

42. The converter according to claim 39, wherein the control unit includes means for initiating a first stroke in a bi-stroke cycle according to a pre-programmed method and for ending the first stroke upon detecting a zero

LO inductor current or energy.

43. The converter according to claim 41, wherein the control unit further includes means for initiating a second stroke in a bi-stroke cycle at the end of the dead time appearing after the 1st stroke and for ending it L 5 according to zero inductor current/energy detection.

44. The converter according to claim 41, wherein the control unit further includes means for initiating a second stroke in a bi-stroke cycle during the dead time and through current handover between Network A and Network B.

.0

45. The converter according to claim 39, further including a logic unit incorporated in the control loop for generating gating signals to all the power switches of the converter, with specific delays and dead times between each gating signal, to ensure switching at low losses for some or all the power

15 switches of the converter.

46. The converter according to claim 39, further including means for synchronizing the stroke beginning time to an external Sync signal.

30 47. The converter according to claim 39, further including means for control of the stroke timings and dead time intervals using a fixed and pre-determined time intervals.

48. The converter according to claim 39, further including a logic unit with a Sync input enabling synchronization of the stroke beginning to an external signal.

49. A DC to DC converter comprising building blocks removably connected to each other, wherein each block includes generic power-processing switching means with means for connecting their energy storage elements in series or in parallel, and further including

5 current-mode control means and an Auxiliary input to the converter for fine-tuning and regulating the output voltage of the converter.

50. The DC to DC converter according to claim 49, further including means for performing a current mode control and having additional Integral and

0 Proportional control paths.

51. The DC to DC converter according to claim 49, further using a current-mode control method with means for measuring the current by sampling the converter capacitors' voltage at proper times and measuring the difference between samples.

[5

52. The DC to DC converter according to claim 51, wherein performing the of the current-mode controller by differentially sampling the converters capacitors' voltage at the series or parallel stroke.

.0 53. The DC to DC converter according to claim 52, wherein performing the sampling at a point so chosen as to achieve a measurement approximating the input or output current of the converter.

54. A DC to DC converter generally as detailed in Fig. 9 and related description. 5

55. A DC to DC converter generally as detailed in Fig. 19 and related description.

56. A DC to DC converter generally as detailed in Fig. 21 and related description. 0

57. A DC to DC converter generally as detailed in Fig. 24 and related description.

58. ADC to DC converter generally as detailed in Fig. 25 and related description.

59. A DC to DC converter generally as detailed in Fig. 27 and related description.

60. ADC to DC converter generally as detailed in Fig. 31 and related description.

61. A DC to DC converter generally as detailed in Fig. 35 and related description.

62. A DC to DC converter generally as detailed in Fig. 36 and related description.

63. A DC to DC converter generally as detailed in Fig. 38 and related description.