CN115224171A - High-luminous-efficiency light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode - Google Patents

High-luminous-efficiency light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Download PDF

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CN115224171A
CN115224171A CN202211143257.3A CN202211143257A CN115224171A CN 115224171 A CN115224171 A CN 115224171A CN 202211143257 A CN202211143257 A CN 202211143257A CN 115224171 A CN115224171 A CN 115224171A
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quantum well
polarization control
growth
emitting diode
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CN115224171B (en
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程龙
郑文杰
曾家明
刘春杨
胡加辉
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Jiangxi Zhao Chi Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

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Abstract

The invention discloses a high-luminous-efficiency light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a U-GaN layer, an N-GaN layer, an active layer, an electronic barrier layer and a P-GaN layer which are sequentially arranged on the substrate, wherein the active layer comprises a plurality of quantum well layers and quantum barrier layers which are alternately stacked; the quantum well layer comprises a first quantum well sub-layer, a first polarization regulation layer, a second quantum well sub-layer and a second polarization regulation layer which are sequentially laminated; the first quantum well sublayer is an InGaN layer, the first polarization regulation layer is an N-InGaN layer, the second quantum well sublayer is an InGaN layer, and the second polarization regulation layer is a P-InGaN layer; the proportion of the In component In the first quantum well sub-layer is smaller than the proportion of the In component In the second quantum well sub-layer. By implementing the invention, the quantum-confined Stark effect can be weakened, and the light effect of the light-emitting diode can be improved.

Description

High-luminous-efficiency light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to a high-luminous-efficiency light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
In a common GaN-based light emitting diode, inGaN/GaN is generally used as an active layer, a higher In component In an InGaN quantum well increases lattice mismatch with a GaN barrier, resulting In a huge piezoelectric field existing In the InGaN quantum well, enhancing a polarization effect of the quantum well, inclining a quantum well region energy band, and causing severe spatial separation when electrons and holes pass through the quantum well region, thereby generating a Quantum Confinement Stark Effect (QCSE), thereby reducing quantum efficiency In the light emitting diode and reducing light emitting efficiency of the light emitting diode.
Disclosure of Invention
The invention aims to provide a high-luminous-efficiency light-emitting diode epitaxial wafer and a preparation method thereof, which can weaken the quantum confinement stark effect and improve the luminous efficiency of a light-emitting diode.
The invention also provides a light emitting diode with high luminous efficiency.
In order to solve the problems, the invention discloses a high-luminous-efficiency light-emitting diode epitaxial wafer which comprises a substrate, and a buffer layer, a U-GaN layer, an N-GaN layer, an active layer, an electronic barrier layer and a P-GaN layer which are sequentially arranged on the substrate, wherein the active layer comprises a plurality of quantum well layers and quantum barrier layers which are alternately stacked; the quantum well layer comprises a first quantum well sub-layer, a first polarization regulation layer, a second quantum well sub-layer and a second polarization regulation layer which are sequentially stacked;
the first quantum well sublayer is an InGaN layer, the first polarization control layer is an N-InGaN layer, the second quantum well sublayer is an InGaN layer, and the second polarization control layer is a P-InGaN layer;
the proportion of the In component In the first quantum well sub-layer is smaller than that In the second quantum well sub-layer.
As an improvement of the above technical solution, the thickness of the first quantum well sublayer is 0.1 to 1nm, the thickness of the first polarization control layer is 0.1 to 1nm, the thickness of the second quantum well sublayer is 1 to 5nm, and the thickness of the second polarization control layer is 0.2 to 2nm.
As an improvement of the above technical solution, the proportion of the In component In the first quantum well sublayer is 0.05 to 0.15, the proportion of the In component In the first polarization control layer is 0.1 to 0.3, the proportion of the In component In the second quantum well sublayer is 0.15 to 0.3, and the proportion of the In component In the second polarization control layer is 0.1 to 0.3;
the doping element of the first polarization control layer is Si, and the doping concentration is 5 multiplied by 10 16 -5×10 17 cm -3 ；
The doping element of the second polarization control layer is Mg, and the doping concentration is 1 multiplied by 10 17 -1×10 18 cm -3 。
As an improvement of the above technical solution, the In component In the first quantum well sublayer gradually increases along the growth direction of the epitaxial wafer, the In component In the first polarization control layer gradually increases along the growth direction of the epitaxial wafer, and the In component In the second polarization control layer gradually decreases along the growth direction of the epitaxial wafer.
As an improvement of the above technical solution, the quantum well layer includes a third quantum well sublayer, a defect barrier layer, a first quantum well sublayer, a first polarization control layer, a second quantum well sublayer and a second polarization control layer, which are sequentially stacked;
the third quantum well sub-layer is a GaN layer, and the defect blocking layer is a SiN layer;
the thickness of the third quantum well sub-layer is 0.5-5nm, and the thickness of the defect barrier layer is 1-10nm.
Correspondingly, the invention also discloses a preparation method of the high-luminous-efficiency light-emitting diode epitaxial wafer, which is used for preparing the high-luminous-efficiency light-emitting diode epitaxial wafer and comprises the following steps:
providing a substrate, growing a buffer layer, a U-GaN layer, an N-GaN layer, an active layer, an electron blocking layer and a P-GaN layer on the substrate in sequence,
the active layer comprises a plurality of quantum well layers and quantum barrier layers which are alternately stacked, wherein each quantum well layer comprises a first quantum well sub-layer, a first polarization regulation and control layer, a second quantum well sub-layer and a second polarization regulation and control layer which are sequentially stacked;
the first quantum well sub-layer is an InGaN layer, the first polarization regulation and control layer is an N-InGaN layer, the second quantum well sub-layer is an InGaN layer, and the second polarization regulation and control layer is a P-InGaN layer.
As an improvement of the technical scheme, the growth temperature of the first quantum well sub-layer is 750-830 ℃, and the growth pressure is 50-500torr;
the growth temperature of the first polarization control layer is 750-830 ℃, and the growth pressure is 50-500torr;
the growth temperature of the second quantum well sub-layer is 830-900 ℃, and the growth pressure is 50-500torr;
the growth temperature of the second polarization control layer is 830-900 ℃, and the growth pressure is 50-500torr.
As an improvement of the above technical scheme, the growth temperature is gradually reduced in the growth process of the first quantum well sublayer, and the cooling rate is 20-100 ℃/min;
the growth temperature is gradually reduced in the growth process of the first polarization control layer, and the cooling rate is 20-100 ℃/min;
the growth temperature of the second polarization control layer gradually rises in the growth process, and the heating rate is 50-150 ℃/min.
As an improvement of the above technical solution, the quantum well layer includes a third quantum well sublayer, a defect barrier layer, a first quantum well sublayer, a first polarization control layer, a second quantum well sublayer and a second polarization control layer, which are sequentially stacked; the third quantum well sub-layer is a GaN layer, and the defect blocking layer is a SiN layer;
the growth temperature of the third quantum well sublayer is 810-870 ℃, and the growth pressure is 50-500torr;
the growth temperature of the defect barrier layer is 810-870 ℃, and the growth pressure is 50-500torr.
Correspondingly, the invention also discloses a light-emitting diode which comprises the high-luminous-efficiency light-emitting diode epitaxial wafer.
The implementation of the invention has the following beneficial effects:
1. in the high-light-efficiency light emitting diode epitaxial wafer, the quantum well layer of the active layer comprises a first quantum well sub-layer, a first polarization regulation layer, a second quantum well sub-layer and a second polarization regulation layer which are sequentially stacked, wherein the first quantum well sub-layer is an InGaN layer, the first polarization regulation layer is an N-InGaN layer, the second quantum well sub-layer is an InGaN layer, and the second polarization regulation layer is a P-InGaN layer. The polarization electric field of the quantum well region can be regulated and controlled through the first polarization regulation and control layer and the second polarization regulation and control layer, and the quantum confinement Stark effect is weakened. In addition, by controlling the proportion of the In component In the first quantum well sub-layer to be smaller than that In the second quantum well sub-layer, the lattice mismatch between the quantum well layer and the quantum barrier layer can be reduced, and the polarization effect of the quantum well layer is weakened. The quantum well layer and the quantum well layer are combined, and the luminous efficiency of electrons and holes in the quantum well layer is effectively improved.
2. In the quantum well layer of the high-light-efficiency light-emitting diode epitaxial wafer, the third quantum well sub-layer (GaN layer) is further arranged and can cooperate with the first quantum well sub-layer to further reduce the lattice mismatch degree and improve the crystal quality of the quantum well layer. In addition, in the quantum well layer of the present application, a defect blocking layer (SiN layer) is further disposed between the third quantum well sub-layer and the first quantum well sub-layer, which can effectively block defects extending to the quantum well layer, reduce non-radiative recombination, and improve light emitting efficiency.
Drawings
Fig. 1 is a schematic structural diagram of an epitaxial wafer of a high-luminous-efficiency light emitting diode according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a quantum well layer structure in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram of a quantum well layer structure according to an embodiment of the invention;
FIG. 4 is a flow chart of a method for fabricating a high-luminous-efficiency light emitting diode epitaxial wafer according to an embodiment of the present invention;
fig. 5 is a flow chart of a method for fabricating a quantum well layer in an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below.
Referring to fig. 1 and 2, the invention discloses a high-luminous-efficiency light emitting diode epitaxial wafer, which comprises a substrate 1, and a buffer layer 2, a U-GaN layer 3, an N-GaN layer 4, an active layer 5, an electron blocking layer 6 and a P-GaN layer 7 which are sequentially arranged on the substrate 1. The active layer 5 includes a plurality of quantum well layers 51 and quantum barrier layers 52 alternately stacked, and the number of stacking cycles is 3 to 20.
The quantum well layer 51 includes a first quantum well sub-layer 511, a first polarization control layer 512, a second quantum well sub-layer 513, and a second polarization control layer 514, which are sequentially stacked. Specifically, the first quantum well sublayer 511 is an InGaN layer, the first polarization control layer 512 is an N-InGaN layer, the second quantum well sublayer 513 is an InGaN layer, and the second polarization control layer 514 is a P-InGaN layer; the proportion of the In component In the first quantum well sub-layer 511 is smaller than that In the second quantum well sub-layer 513. Based on the above arrangement, lattice mismatch between the quantum well layer 51 and the quantum barrier layer 52 is reduced, the polarization effect of the quantum well layer is weakened, the quantum confinement stark effect is weakened, and the light emitting efficiency of electrons and holes in the quantum well layer is improved.
The In component proportion of the first quantum well sub-layer 511 is 0.05-0.15, and the In component proportion is low, so that the quantum well sub-layer can play a good transition role, and the polarization effect of the quantum well layer 51 is weakened. Preferably, in an embodiment of the present invention, the In composition In the first quantum well sub-layer 511 gradually increases along the growth direction of the epitaxial wafer, and specifically, may gradually increase from 0.05 to 0.08 to 0.1 to 0.15. Based on this arrangement, the crystal quality of the quantum well layer 51 can be further improved, and the problem of lattice mismatch due to too high In composition can be reduced. Further preferably, the In component In the first quantum well sub-layer 511 gradually increases along the growth direction of the epitaxial wafer, and the highest value of the In component is the same as the lowest value of the In component In the first polarization regulating layer 512. Based on the arrangement, the gradient structure can be further strengthened, and the lattice mismatch is reduced.
Specifically, the thickness of the first quantum well sublayer 511 is 0.1 to 1nm, and when the thickness is less than 0.1nm, it is difficult to effectively improve the crystal quality of the quantum well layer 51; when the thickness is larger than 1nm, the localization effect of the first quantum well sublayer 511 is enhanced, the carrier injection of the second quantum well sublayer 513 is influenced, and the light emitting efficiency of the quantum well is reduced. Illustratively, the thickness of the first quantum well sub-layer 511 is 0.2nm, 0.3nm, 0.4nm, 0.5nm, 0.6nm, 0.7nm, or 0.8nm, but is not limited thereto.
The doping element in the first polarization control layer 512 is Si, but not limited thereto. The doping concentration of Si in the first polarization control layer 512 is 5 × 10 16 -5×10 17 cm -3 When the doping concentration is too large or too small, it is difficult to effectively adjust the polarization electric field of the quantum well layer 51, and it is difficult to effectively weaken the quantum confinement stark effect. Illustratively, the doping concentration of Si in the first polarization control layer 512 is 6.5 × 10 16 cm -3 、8×10 16 cm -3 、9.5×10 16 cm -3 、1×10 17 cm -3 、2.5×10 17 cm -3 Or 4.5X 10 17 cm -3 But is not limited thereto.
Specifically, the In component In the first polarization control layer 512 has a proportion of 0.1-0.3, and can cooperate with the first quantum well sublayer 511 to perform a good transition effect and weaken the polarization effect of the quantum well layer 51. Preferably, in an embodiment of the present invention, the In composition In the first polarization control layer 512 gradually increases along the epitaxial growth direction, and specifically, may gradually increase from 0.1 to 0.15 to 0.3, and based on this arrangement, the polarization effect of the quantum well layer 51 may be further weakened. Further preferably, the In component In the first polarization control layer 512 is gradually increased along the growth direction of the epitaxial wafer, and the highest value of the In component is the same as the lowest value of the In component In the second quantum well sub-layer 513.
Specifically, the thickness of the first polarization control layer 512 is 0.1 to 1nm, and when the thickness is less than 0.1nm, it is difficult to effectively control the polarization electric field of the quantum well layer 51; when the thickness is greater than 1nm, electrons can migrate too fast in the quantum well layer 51, and recombination of electrons and holes in the quantum well layer 51 is reduced, thereby reducing the light emitting efficiency. Illustratively, the thickness of the first polarization control layer 512 is 0.2nm, 0.3nm, 0.4nm, 0.5nm, 0.6nm, 0.7nm, or 0.8nm, but is not limited thereto.
Wherein the In component In the second quantum well sublayer 513 has a ratio of 0.15 to 0.3, and is maintained constant. Illustratively, the In composition In the second quantum well sublayer 513 has a ratio of 0.18, 0.21, 0.24, 0.27, or 0.29, but is not limited thereto. Preferably 0.2 to 0.3. By maintaining the second quantum well sublayer 513 with a higher In composition, the In composition In the quantum well layer 51 can be maintained at a reasonable ratio, thereby maintaining reasonable external quantum efficiency and luminous efficiency.
Specifically, the thickness of the second quantum well sublayer 513 is 1 to 5nm, and when the thickness thereof is less than 1nm, it is difficult to maintain a reasonable In composition; when the thickness is more than 5nm, the quantum well layer 51 has a strong polarization effect and low light emission efficiency. Illustratively, the thickness of the second quantum well sublayer 513 is 1.4nm, 1.8nm, 2.2nm, 2.6nm, 3nm, 3.4nm, 3.8nm, 4.2nm, or 4.6nm, but is not limited thereto.
The doping element in the second polarization control layer 514 is Mg, but is not limited thereto. The doping concentration of Mg in the second polarization control layer 514 is 1 × 10 17 -1×10 18 cm -3 . When the doping concentration is too large or too small, it is difficult to effectively adjust the polarization electric field of the quantum well layer 51, and it is difficult to effectively weaken the quantum confinement stark effect. Illustratively, the doping concentration of Si in the second polarization control layer 514 is 1.5 × 10 17 cm -3 、3×10 17 cm -3 、4.5×10 17 cm -3 、6×10 17 cm -3 、7.5×10 17 cm -3 Or 9X 10 17 cm -3 But is not limited thereto.
Specifically, the In component In the second polarization control layer 514 is In a ratio of 0.1 to 0.3, preferably 0.1 to 0.25. The second polarization control layer 514 is arranged close to the quantum barrier layer 52, so that the lower In component of the second polarization control layer is kept, the lattice mismatch can be reduced, and the crystal quality is improved. Preferably, in an embodiment of the present invention, the In composition In the second polarization control layer 514 is gradually decreased along the growth direction of the epitaxial wafer, and specifically, the In composition is gradually decreased from 0.15 to 0.3 to 0.1 to 0.25. Based on this arrangement, the crystal quality of the quantum well layer 51 can be further improved. It is further preferable that the In composition In the second polarization control layer 514 is gradually decreased In the epitaxial growth direction, and the highest value of the In composition is the same as the In composition In the second quantum well sub-layer 513.
Specifically, the thickness of the second polarization control layer 514 is 0.2-2nm, and when the thickness is less than 0.2nm, it is difficult to effectively control the polarization electric field of the quantum well layer 51; when the thickness thereof is > 2nm, the migration speed of holes in the quantum well layer 51 is reduced, the recombination of holes and electrons in the quantum well layer 51 is reduced, and the light emission efficiency is lowered.
Preferably, referring to fig. 3, in another embodiment of the present invention, the quantum well layer 51 includes a third quantum well sub-layer 515, a defect blocking layer 516, a first quantum well sub-layer 511, a first polarization regulating layer 512, a second quantum well sub-layer 513, and a second polarization regulating layer 514, which are sequentially stacked. Specifically, the third quantum well sub-layer 515 is a GaN layer, and the defect blocking layer 516 is a SiN layer.
The third quantum well sub-layer 515 and the first quantum well sub-layer 511 cooperate with each other to further reduce the degree of lattice mismatch and improve the crystal quality of the quantum well layer. The thickness of the third quantum well sublayer 515 is 0.5-5nm, illustratively 0.8nm, 1nm, 1.5nm, 2nm, 3nm, 3.4nm, 4nm, or 4.4nm, but is not limited thereto.
Wherein the defect blocking layer 516 may block defects from the substrate 1 from entering into the quantum well layer 51. The thickness of the defect blocking layer 516 is 1-10nm, and is illustratively 2nm, 4nm, 6nm, 7nm, 8nm, or 9nm, but is not limited thereto.
The quantum barrier layer 52 is a GaN layer with a thickness of 5-15nm, for example, 6nm, 7nm, 8nm, 10nm, 12nm, or 14nm, but is not limited thereto.
The substrate 1 may be, but not limited to, a sapphire substrate, a silicon substrate, or a silicon carbide substrate.
Wherein, the buffer layer 2 may be an AlN layer and/or a GaN layer, but is not limited thereto; preferably, the buffer layer 2 is an AlN layer, which can control crystal defects, improve the quality of subsequently grown crystals, and relieve stress between the substrate and the epitaxial layer due to lattice mismatch and thermal mismatch. The thickness of the buffer layer 2 is 10 to 50nm, and exemplary is 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, or 45nm, but is not limited thereto.
Among them, the thickness of the U-GaN layer 3 is 1 to 5 μm, and is exemplified by 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, or 4.5 μm, but is not limited thereto.
The doping element of the N-GaN layer 4 is Si, but not limited thereto. The doping concentration of the N-GaN layer 4 is 1X 10 19 -5×10 19 cm -3 The thickness is 2-3 μm.
Wherein the electron blocking layer 6 is Al x In y Ga 1-x-y And the N layer, wherein x is 0.005-0.1, y is 0.01-0.2, the electron barrier layer 6 can effectively limit electron overflow, reduce blocking of holes, improve injection efficiency of the holes to a quantum well, reduce auger recombination of carriers and improve luminous efficiency of the light-emitting diode. Preferably, in one embodiment of the present invention, the proportion of the Al composition (i.e., x) In the electron blocking layer 6 gradually increases from the active layer 5 side, and the In composition is maintained constant. The thickness of the electron blocking layer 6 is 10-40nm.
The doping element in the P-GaN layer 7 is Mg, but not limited thereto. The doping concentration of Mg in the P-GaN layer 7 is 1X 10 19 -1×10 21 cm -3 . The thickness of the P-GaN layer 7 is 10-50nm.
Correspondingly, referring to fig. 4, the present application further discloses a method for preparing a high-luminous-efficiency light emitting diode epitaxial wafer, which is used for preparing the high-luminous-efficiency light emitting diode epitaxial wafer, and includes the following steps:
s100: providing a substrate;
specifically, the substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate, but is not limited thereto. A sapphire substrate is preferred.
S200: sequentially growing a buffer layer, a U-GaN layer, an N-GaN layer, an active layer, an electron blocking layer and a P-GaN layer on a substrate;
specifically, S200 includes:
s210: growing a buffer layer on a substrate;
specifically, MOCVD growth of GaN as a buffer layer or PVD growth of an AlN layer as a buffer layer may be used, but is not limited thereto. Preferably, the AlN layer is grown using PVD.
Preferably, in one embodiment of the present invention, after the AlN layer growth is complete,the substrate is loaded into MOCVD at H 2 Pretreating for 1-10min under atmosphere at 1000-1200 deg.C; and then carrying out nitridation treatment to improve the crystal quality of the AlN layer.
S220: growing a U-GaN layer on the buffer layer;
specifically, a U-GaN layer is grown in MOCVD, the growth temperature is 1050-1200 ℃, and the growth pressure is 100-600torr.
S230: growing an N-GaN layer on the U-GaN layer;
specifically, an N-GaN layer is grown in MOCVD at 1050-1200 ℃ and under 100-600torr.
S240: growing an active layer on the N-GaN layer;
specifically, a quantum well layer and a quantum barrier layer are periodically grown in MOCVD to form an active layer. Wherein the growth temperature of the quantum barrier layer is 800-950 ℃, and the growth pressure is 100-500torr, but the growth method is not limited to the above.
Specifically, referring to fig. 5, in one embodiment of the present invention, growing a quantum well layer comprises:
s1: growing a third quantum well sublayer on the N-GaN layer/the quantum barrier layer;
specifically, a GaN layer is grown in MOCVD as a third quantum well sublayer. The growth temperature is 810-870 ℃, and the growth pressure is 50-500torr.
S2: growing a defect barrier layer on the third quantum well sublayer;
specifically, a SiN layer is grown in MOCVD as a defect barrier. The growth temperature is 810-870 ℃, and the growth pressure is 50-500torr.
S3: growing a first quantum well sub-layer on the defect barrier layer;
specifically, an AlGaN layer is grown in MOCVD as a first quantum well sublayer. The growth temperature is 750-830 deg.c and the growth pressure is 50-500torr. Based on the growth temperature and the growth pressure, the incorporation efficiency of the In component is improved, the mobility of atoms is improved by the lower growth pressure of the In component and the growth pressure, and step flow growth is facilitated.
Preferably, in an embodiment of the present invention, the growth temperature is gradually decreased during the growth of the first quantum well sub-layer, and the temperature decrease rate is controlled to be 20-100 ℃/min. Based on such control, one is favorable for forming a gradually changed In component, and reducing the lattice mismatch between the quantum well layer and the quantum barrier layer; and In atoms can form more uniform doping, so that the crystal quality of the quantum well layer is improved.
S4: growing a first polarization control layer on the first quantum well sublayer;
specifically, an N-AlGaN layer is grown in MOCVD as a first polarization control layer. The growth temperature is 750-830 deg.c and the growth pressure is 50-500torr. Based on the growth temperature and the growth pressure, the incorporation efficiency of the In component is improved, the mobility of atoms is improved by the lower growth pressure of the In component and the growth pressure, and the step flow type growth is facilitated.
Preferably, in an embodiment of the present invention, the growth temperature is gradually decreased during the growth of the first polarization control layer, and the temperature decrease rate is controlled to be 20-100 ℃/min. Based on the control, one is beneficial to forming a gradually changed In component and reducing the lattice mismatch between the quantum well layer and the quantum barrier layer; and In atoms can form more uniform doping, so that the crystal quality of the quantum well layer is improved.
S5: growing a second quantum well sublayer on the first polarization control layer;
specifically, an AlGaN layer is grown in MOCVD as the second quantum well sublayer. The growth temperature is 830-900 ℃, the growth pressure is 50-500torr, and the growth temperature and the growth pressure are kept constant in the growth process.
S6: growing a second polarization control layer on the second quantum well sublayer;
specifically, a P-AlGaN layer is grown in MOCVD to be used as a second polarization control layer. The growth temperature is 830-900 deg.C, and the growth pressure is 50-500torr. The lower growth pressure improves the mobility of atoms and is beneficial to step flow growth.
Preferably, in an embodiment of the present invention, the growth temperature gradually increases during the growth of the second polarization control layer, and the temperature increase rate is 50-150 ℃/min. Based on the control, one is beneficial to forming a gradually changed In component and reducing the lattice mismatch between the quantum well layer and the quantum barrier layer; and In addition, in atoms can form more uniform doping, and the crystal quality of the quantum well layer is improved.
S250: growing an electron blocking layer on the active layer;
specifically, al is grown in MOCVD x In y Ga 1-x-y And the N layer is used as an electron blocking layer. The growth temperature is 900-1000 deg.C, and the growth pressure is 100-300torr.
S260: growing a P-GaN layer on the electron blocking layer;
specifically, a P-GaN layer is grown in MOCVD at the growth temperature of 900-1050 ℃ and the growth pressure of 100-600torr.
The invention is further illustrated by the following specific examples:
example 1
The embodiment provides an epitaxial wafer of a light emitting diode, and referring to fig. 1 and fig. 2, the epitaxial wafer comprises a substrate 1, and a buffer layer 2, a U-GaN layer 3, an N-GaN layer 4, an active layer 5, an electron blocking layer 6 and a P-GaN layer 7 which are sequentially arranged on the substrate 1.
Wherein, the substrate 1 is a sapphire substrate, the buffer layer 2 is an AlN layer, and the thickness of the AlN layer is 15nm; the thickness of the U-GaN layer 3 was 2.5 μm. The doping concentration of Si in the N-GaN layer 4 was 2.5X 10 19 cm -3 The thickness was 2.8. Mu.m.
The active layer 5 includes quantum well layers 51 and quantum barrier layers (GaN layers, each having a thickness of 5 nm) stacked alternately, and the number of stacking cycles is 10. Each quantum well layer 51 includes a first quantum well sub-layer 511, a first polarization regulating layer 512, a second quantum well sub-layer 513, and a second polarization regulating layer 514, which are sequentially stacked.
Specifically, the first quantum well sublayer 511 is an InGaN layer having an In composition ratio of 0.08 (maintained constant) and a thickness of 0.5nm. The first polarization control layer 512 is an N-InGaN layer having an In component ratio of 0.15 (constant), a doping element of Si and a doping concentration of 1.5 × 10 17 cm -3 The thickness is 0.5nm. The second quantum well sublayer 513 was an InGaN layer with an In composition ratio of 0.22 (maintained constant) and a thickness of 3.2nm. The second polarization control layer 514 is a P-InGaN layer with an In fraction of 0.12 (constant), doped elementThe element is Mg, and the doping concentration is 5 multiplied by 10 17 cm -3 The thickness is 1nm.
Wherein the electron blocking layer 6 is Al x In y Ga 1-x-y The N layer (x is gradually changed from 0.01 to 0.05, y is 0.01) is 15nm thick. The doping element of the P-GaN layer 7 is Mg, and the doping concentration is 2 multiplied by 10 20 cm -3 The thickness is 15nm.
The preparation method of the light emitting diode epitaxial wafer in the embodiment includes the following steps:
(1) Providing a substrate;
(2) Growing a buffer layer on a substrate;
specifically, an AlN layer grows by adopting PVD; then loaded into MOCVD in H 2 Treating at 1050 deg.C for 5min under atmosphere, and nitriding.
(3) Growing a U-GaN layer on the buffer layer;
specifically, MOCVD is adopted to grow the U-GaN layer, the growth temperature is 1100 ℃, and the growth pressure is 150torr.
(4) Growing an N-GaN layer on the U-GaN layer;
specifically, an N-GaN layer is grown by MOCVD at 1120 ℃ under a growth pressure of 100torr.
(5) Growing an active layer on the N-GaN layer;
specifically, a quantum well layer and a quantum barrier layer are periodically grown in MOCVD to obtain an active layer;
wherein the growth temperature of the quantum barrier layer is 840 ℃, and the growth pressure is 400torr.
The preparation method of each quantum well layer comprises the following steps:
growing a first quantum well sublayer;
specifically, an InGaN layer is grown by MOCVD as the first quantum well sub-layer. The growth temperature was 800 deg.C (maintained constant) and the growth pressure was 200torr.
(II) growing a first polarization control layer on the first quantum well sublayer;
specifically, an N-InGaN layer is grown by MOCVD and serves as a first polarization control layer. The growth temperature was 800 deg.C (maintained constant) and the growth pressure was 200torr.
(III) growing a second quantum well sublayer on the first polarization control layer;
specifically, an InGaN layer is grown by MOCVD as the second quantum well sub-layer. The growth temperature was 790 deg.C (maintained constant) and the growth pressure was 200torr.
(IV) growing a second polarization control layer on the second quantum well sublayer;
specifically, a P-InGaN layer is grown by MOCVD and used as a second polarization control layer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(6) Growing an electron blocking layer on the active layer;
specifically, MOCVD is used to grow Al x In y Ga 1-x-y And the N layer is used as an electron blocking layer. The growth temperature was 960 ℃ and the growth pressure was 200torr.
(7) Growing a P-GaN layer on the electron blocking layer;
specifically, MOCVD is adopted to grow the P-GaN layer, the growth temperature is 985 ℃, and the growth pressure is 200torr.
Example 2
The embodiment provides an epitaxial wafer of a light emitting diode, and referring to fig. 1 and fig. 3, the epitaxial wafer of the light emitting diode comprises a substrate 1, and a buffer layer 2, a U-GaN layer 3, an N-GaN layer 4, an active layer 5, an electron blocking layer 6 and a P-GaN layer 7 which are sequentially arranged on the substrate 1.
Wherein, the substrate 1 is a sapphire substrate, the buffer layer 2 is an AlN layer, and the thickness of the AlN layer is 15nm; the thickness of the U-GaN layer 3 was 2.5 μm. The doping concentration of Si in the N-GaN layer 4 was 2.5X 10 19 cm -3 The thickness was 2.8. Mu.m.
The active layer 5 includes quantum well layers 51 and quantum barrier layers (GaN layers, each having a thickness of 5 nm) stacked alternately, and the number of stacking cycles is 10. Each quantum well layer 51 includes a third quantum well sublayer 515, a defect blocking layer 516, a first quantum well sublayer 511, a first polarization regulating layer 512, a second quantum well sublayer 513, and a second polarization regulating layer 514, which are sequentially stacked.
Specifically, the first quantum well sublayer 511 is an InGaN layer having an In composition ratio of 0.08 (maintained constant) and a thickness of 0.5nm. The first polarization control layer 512 is NInGaN layer with an In fraction of 0.15 (kept constant), a doping element of Si and a doping concentration of 1.5X 10 17 cm -3 The thickness is 0.5nm. The second quantum well sublayer 513 was an InGaN layer with an In composition ratio of 0.22 (maintained constant) and a thickness of 3.2nm. The second polarization control layer 514 is a P-InGaN layer with an In composition ratio of 0.12 (constant), a doping element Mg and a doping concentration of 5 × 10 17 cm -3 The thickness is 1nm; the third quantum well sublayer 515 is a GaN layer with a thickness of 2nm; the defect blocking layer 516 is a SiN layer with a thickness of 5nm.
Wherein the electron blocking layer 6 is Al x In y Ga 1-x-y N layer (x is gradually changed from 0.01 to 0.05, y is 0.01) with the thickness of 15nm. The doping element of the P-GaN layer 7 is Mg, and the doping concentration is 2 multiplied by 10 20 cm -3 The thickness is 15nm.
The preparation method of the light emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
(2) Growing a buffer layer on a substrate;
specifically, an AlN layer grows by adopting PVD; then loaded into MOCVD in H 2 Treating at 1050 deg.C for 5min under atmosphere, and nitriding.
(3) Growing a U-GaN layer on the buffer layer;
specifically, MOCVD is adopted to grow the U-GaN layer, the growth temperature is 1100 ℃, and the growth pressure is 150torr.
(4) Growing an N-GaN layer on the U-GaN layer;
specifically, an N-GaN layer is grown by MOCVD at 1120 ℃ under a growth pressure of 100torr.
(5) Growing an active layer on the N-GaN layer;
specifically, a quantum well layer and a quantum barrier layer are periodically grown in MOCVD to obtain an active layer;
wherein the growth temperature of the quantum barrier layer is 840 ℃, and the growth pressure is 400torr.
The preparation method of each quantum well layer comprises the following steps:
growing a third quantum well sub-layer;
specifically, a GaN layer is grown by MOCVD to serve as a first quantum well sublayer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(II) growing a defect barrier layer on the third quantum well sublayer
Specifically, an MOCVD is used to grow a SiN layer as a defect blocking layer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(iii) growing a first quantum well sub-layer on the defect barrier layer;
specifically, an InGaN layer is grown by MOCVD as the first quantum well sub-layer. The growth temperature was 800 deg.C (maintained constant) and the growth pressure was 200torr.
(IV) growing a first polarization control layer on the first quantum well sublayer;
specifically, an N-InGaN layer is grown by MOCVD and serves as a first polarization control layer. The growth temperature was 800 deg.C (maintained constant) and the growth pressure was 200torr.
(v) growing a second quantum well sub-layer on the first polarization modulation layer;
specifically, an InGaN layer is grown by MOCVD as the second quantum well sub-layer. The growth temperature was 790 deg.C (maintained constant) and the growth pressure was 200torr.
(vi) growing a second polarization control layer on the second quantum well sublayer;
specifically, a P-InGaN layer is grown by MOCVD and used as a second polarization control layer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(6) Growing an electron blocking layer on the active layer;
specifically, MOCVD is used to grow Al x In y Ga 1-x-y And the N layer is used as an electron blocking layer. The growth temperature was 960 ℃ and the growth pressure was 200torr.
(7) Growing a P-GaN layer on the electron blocking layer;
specifically, MOCVD is adopted to grow the P-GaN layer, the growth temperature is 985 ℃, and the growth pressure is 200torr.
Example 3
The embodiment provides an epitaxial wafer of a light emitting diode, and referring to fig. 1 and fig. 3, the epitaxial wafer includes a substrate 1, and a buffer layer 2, a U-GaN layer 3, an N-GaN layer 4, an active layer 5, an electron blocking layer 6, and a P-GaN layer 7 which are sequentially arranged on the substrate 1.
Wherein, the substrate 1 is a sapphire substrate, the buffer layer 2 is an AlN layer, and the thickness of the AlN layer is 15nm; the thickness of the U-GaN layer 3 was 2.5 μm. The doping concentration of Si in the N-GaN layer 4 was 2.5X 10 19 cm -3 The thickness was 2.8. Mu.m.
The active layer 5 includes quantum well layers 51 and quantum barrier layers (GaN layers, each having a thickness of 5 nm) stacked alternately, and the number of stacking cycles is 10. Each quantum well layer 51 includes a third quantum well sublayer 515, a defect blocking layer 516, a first quantum well sublayer 511, a first polarization control layer 512, a second quantum well sublayer 513, and a second polarization control layer 514, which are sequentially stacked.
Specifically, the first quantum well sublayer 511 is an InGaN layer having an In composition ratio of 0.08 (maintained constant) and a thickness of 0.5nm. The first polarization control layer 512 is an N-InGaN layer with an In composition ratio of 0.15 (constant), a doping element of Si and a doping concentration of 4 × 10 16 cm -3 The thickness was 0.5nm. The second quantum well sublayer 513 was an InGaN layer with an In composition ratio of 0.22 (maintained constant) and a thickness of 3.2nm. The second polarization control layer 514 is a P-InGaN layer having an In composition ratio of 0.12 (constant), a doping element Mg and a doping concentration of 2 × 10 18 cm -3 The thickness is 1nm. The third quantum well sublayer 515 is a GaN layer with a thickness of 2nm; the defect blocking layer 516 is a SiN layer with a thickness of 5nm.
Wherein the electron blocking layer 6 is Al x In y Ga 1-x-y The N layer (x is gradually changed from 0.01 to 0.05, y is 0.01) is 15nm thick. The doping element of the P-GaN layer 7 is Mg, and the doping concentration is 2 multiplied by 10 20 cm -3 The thickness is 15nm.
The preparation method of the light emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
(2) Growing a buffer layer on a substrate;
specifically, an AlN layer grows by adopting PVD; then loaded into MOCVD in H 2 Treating at 1050 deg.C for 5min under atmosphere, and nitriding.
(3) Growing a U-GaN layer on the buffer layer;
specifically, MOCVD is adopted to grow the U-GaN layer, the growth temperature is 1100 ℃, and the growth pressure is 150torr.
(4) Growing an N-GaN layer on the U-GaN layer;
specifically, MOCVD is adopted to grow the N-GaN layer, the growth temperature is 1120 ℃, and the growth pressure is 100torr.
(5) Growing an active layer on the N-GaN layer;
specifically, a quantum well layer and a quantum barrier layer are periodically grown in MOCVD to obtain an active layer;
wherein the growth temperature of the quantum barrier layer is 840 ℃, and the growth pressure is 400torr.
The preparation method of each quantum well layer comprises the following steps:
growing a third quantum well sub-layer;
specifically, a GaN layer is grown by MOCVD to serve as a first quantum well sublayer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(II) growing a defect barrier layer on the third quantum well sublayer
Specifically, an MOCVD is used to grow a SiN layer as a defect blocking layer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(iii) growing a first quantum well sub-layer on the defect barrier layer;
specifically, an InGaN layer is grown by MOCVD as the first quantum well sub-layer. The growth temperature was 800 deg.C (maintained constant) and the growth pressure was 200torr.
(IV) growing a first polarization control layer on the first quantum well sublayer;
specifically, an N-InGaN layer is grown by MOCVD and serves as a first polarization control layer. The growth temperature was 800 deg.C (maintained constant) and the growth pressure was 200torr.
(v) growing a second quantum well sub-layer on the first polarization modulation layer;
specifically, an InGaN layer is grown by MOCVD as the second quantum well sub-layer. The growth temperature was 790 deg.C (maintained constant) and the growth pressure was 200torr.
(vi) growing a second polarization control layer on the second quantum well sublayer;
specifically, a P-InGaN layer is grown by MOCVD and used as a second polarization control layer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(6) Growing an electron blocking layer on the active layer;
specifically, MOCVD is used to grow Al x In y Ga 1-x-y And the N layer is used as an electron blocking layer. The growth temperature was 960 ℃ and the growth pressure was 200torr.
(7) Growing a P-GaN layer on the electron blocking layer;
specifically, MOCVD is adopted to grow the P-GaN layer, the growth temperature is 985 ℃, and the growth pressure is 200torr.
Example 4
The embodiment provides an epitaxial wafer of a light emitting diode, and referring to fig. 1 and fig. 3, the epitaxial wafer of the light emitting diode comprises a substrate 1, and a buffer layer 2, a U-GaN layer 3, an N-GaN layer 4, an active layer 5, an electron blocking layer 6 and a P-GaN layer 7 which are sequentially arranged on the substrate 1.
Wherein, the substrate 1 is a sapphire substrate, the buffer layer 2 is an AlN layer, and the thickness of the AlN layer is 15nm; the thickness of the U-GaN layer 3 was 2.5 μm. The doping concentration of Si in the N-GaN layer 4 was 2.5X 10 19 cm -3 The thickness was 2.8. Mu.m.
The active layer 5 includes quantum well layers 51 and quantum barrier layers (GaN layers, each having a thickness of 5 nm) stacked alternately, and the number of stacking cycles is 10. Each quantum well layer 51 includes a third quantum well sublayer 515, a defect blocking layer 516, a first quantum well sublayer 511, a first polarization regulating layer 512, a second quantum well sublayer 513, and a second polarization regulating layer 514, which are sequentially stacked.
Specifically, the first quantum well sublayer 511 is an InGaN layer having an In composition ratio of 0.08 (maintained constant) and a thickness of 0.5nm. The first polarization control layer 512 is an N-InGaN layer with an In composition ratio of 0.15 (constant), a doping element of Si and a doping concentration of 6 × 10 17 cm -3 The thickness is 0.5nm. The second quantum well sublayer 513 is InGaAnd an N layer having an In composition ratio of 0.22 (maintained constant) and a thickness of 3.2nm. The second polarization control layer 514 is a P-InGaN layer with an In composition ratio of 0.12 (constant), a doping element Mg and a doping concentration of 8.5 × 10 16 cm -3 cm -3 The thickness is 1nm. The third quantum well sublayer 515 is a GaN layer with a thickness of 2nm; the defect blocking layer 516 is a SiN layer with a thickness of 5nm.
Wherein the electron blocking layer 6 is Al x In y Ga 1-x-y The N layer (x is gradually changed from 0.01 to 0.05, y is 0.01) is 15nm thick. The doping element of the P-GaN layer 7 is Mg, and the doping concentration is 2 multiplied by 10 20 cm -3 And the thickness is 15nm.
The preparation method of the light emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
(2) Growing a buffer layer on a substrate;
specifically, an AlN layer grows by adopting PVD; then loaded into MOCVD in H 2 Treating at 1050 deg.C for 5min under atmosphere, and nitriding.
(3) Growing a U-GaN layer on the buffer layer;
specifically, MOCVD is adopted to grow the U-GaN layer, the growth temperature is 1100 ℃, and the growth pressure is 150torr.
(4) Growing an N-GaN layer on the U-GaN layer;
specifically, MOCVD is adopted to grow the N-GaN layer, the growth temperature is 1120 ℃, and the growth pressure is 100torr.
(5) Growing an active layer on the N-GaN layer;
specifically, a quantum well layer and a quantum barrier layer are periodically grown in MOCVD to obtain an active layer;
wherein the growth temperature of the quantum barrier layer is 840 ℃, and the growth pressure is 400torr.
The preparation method of each quantum well layer comprises the following steps:
growing a third quantum well sub-layer;
specifically, a MOCVD is used to grow a GaN layer as the first quantum well sublayer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(II) growing a defect barrier layer on the third quantum well sublayer
Specifically, MOCVD is used to grow SiN layer as defect barrier. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(iii) growing a first quantum well sub-layer on the defect barrier layer;
specifically, an InGaN layer is grown by MOCVD as the first quantum well sub-layer. The growth temperature was 800 deg.C (maintained constant) and the growth pressure was 200torr.
(IV) growing a first polarization control layer on the first quantum well sublayer;
specifically, an N-InGaN layer is grown by MOCVD and used as a first polarization control layer. The growth temperature was 800 deg.C (maintained constant) and the growth pressure was 200torr.
(v) growing a second quantum well sub-layer on the first polarization modulation layer;
specifically, an InGaN layer is grown by MOCVD as the second quantum well sub-layer. The growth temperature was 790 deg.C (maintained constant) and the growth pressure was 200torr.
(vi) growing a second polarization control layer on the second quantum well sublayer;
specifically, an MOCVD is adopted to grow a P-InGaN layer as a second polarization control layer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(6) Growing an electron blocking layer on the active layer;
specifically, MOCVD is adopted to grow Al x In y Ga 1-x-y And the N layer is used as an electron blocking layer. The growth temperature was 960 ℃ and the growth pressure was 200torr.
(7) Growing a P-GaN layer on the electron blocking layer;
specifically, MOCVD is adopted to grow the P-GaN layer, the growth temperature is 985 ℃, and the growth pressure is 200torr.
Example 5
The embodiment provides an epitaxial wafer of a light emitting diode, and referring to fig. 1 and fig. 3, the epitaxial wafer of the light emitting diode comprises a substrate 1, and a buffer layer 2, a U-GaN layer 3, an N-GaN layer 4, an active layer 5, an electron blocking layer 6 and a P-GaN layer 7 which are sequentially arranged on the substrate 1.
Wherein, the substrate 1 is a sapphire substrate, the buffer layer 2 is an AlN layer, and the thickness of the AlN layer is 15nm; the thickness of the U-GaN layer 3 was 2.5 μm. The doping concentration of Si in the N-GaN layer 4 was 2.5X 10 19 cm -3 The thickness thereof was 2.8. Mu.m.
The active layer 5 includes quantum well layers 51 and quantum barrier layers (GaN layers, each having a thickness of 5 nm) alternately stacked, and the number of stacking cycles is 10. Each quantum well layer 51 includes a third quantum well sublayer 515, a defect blocking layer 516, a first quantum well sublayer 511, a first polarization control layer 512, a second quantum well sublayer 513, and a second polarization control layer 514, which are sequentially stacked.
Specifically, the first quantum well sub-layer 511 is an InGaN layer having an In composition ratio linearly increasing from 0.05 to 0.1, and a thickness of 0.5nm. The first polarization control layer 512 is an N-InGaN layer with an In content linearly increasing from 0.1 to 0.22, the doping element is Si and the doping concentration is 1.5 × 10 17 cm -3 The thickness was 0.5nm. The second quantum well sublayer 513 was an InGaN layer with an In composition fraction of 0.22 (maintained constant) and a thickness of 3.2nm. The second polarization control layer 514 is a P-InGaN layer with an In component linearly decreasing from 0.22 to 0.1, a doping element Mg and a doping concentration of 5 × 10 17 cm -3 The thickness is 1nm. The third quantum well sublayer 515 is a GaN layer with a thickness of 2nm; the defect blocking layer 516 is a SiN layer with a thickness of 5nm.
Wherein the electron blocking layer 6 is Al x In y Ga 1-x-y The N layer (x is gradually changed from 0.01 to 0.05, y is 0.01) is 15nm thick. The doping element of the P-GaN layer 7 is Mg, and the doping concentration is 2 multiplied by 10 20 cm -3 The thickness is 15nm.
The preparation method of the light emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
(2) Growing a buffer layer on a substrate;
specifically, an AlN layer grows by adopting PVD; then loaded into MOCVD in H 2 Treating at 1050 deg.C for 5min under atmosphere, and nitriding.
(3) Growing a U-GaN layer on the buffer layer;
specifically, MOCVD is adopted to grow the U-GaN layer, the growth temperature is 1100 ℃, and the growth pressure is 150torr.
(4) Growing an N-GaN layer on the U-GaN layer;
specifically, MOCVD is adopted to grow the N-GaN layer, the growth temperature is 1120 ℃, and the growth pressure is 100torr.
(5) Growing an active layer on the N-GaN layer;
specifically, a quantum well layer and a quantum barrier layer are periodically grown in MOCVD to obtain an active layer;
wherein the growth temperature of the quantum barrier layer is 840 ℃, and the growth pressure is 400torr.
The preparation method of each quantum well layer comprises the following steps:
growing a third quantum well sub-layer;
specifically, a GaN layer is grown by MOCVD to serve as a first quantum well sublayer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(II) growing a defect barrier layer on the third quantum well sublayer
Specifically, an MOCVD is used to grow a SiN layer as a defect blocking layer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(iii) growing a first quantum well sub-layer on the defect barrier layer;
specifically, an InGaN layer is grown by MOCVD as the first quantum well sub-layer. The growth temperature was 800 deg.C (maintained constant) and the growth pressure was 200torr.
(IV) growing a first polarization control layer on the first quantum well sublayer;
specifically, an N-InGaN layer is grown by MOCVD and used as a first polarization control layer. The growth temperature was 800 deg.C (maintained constant) and the growth pressure was 200torr.
(v) growing a second quantum well sub-layer on the first polarization modulation layer;
specifically, an InGaN layer is grown by MOCVD as the second quantum well sub-layer. The growth temperature was 790 deg.C (maintained constant) and the growth pressure was 200torr.
(vi) growing a second polarization control layer on the second quantum well sublayer;
specifically, a P-InGaN layer is grown by MOCVD and used as a second polarization control layer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(6) Growing an electron blocking layer on the active layer;
specifically, MOCVD is adopted to grow Al x In y Ga 1-x-y And the N layer is used as an electron blocking layer. The growth temperature was 960 ℃ and the growth pressure was 200torr.
(7) Growing a P-GaN layer on the electron blocking layer;
specifically, MOCVD is adopted to grow the P-GaN layer, the growth temperature is 985 ℃, and the growth pressure is 200torr.
Example 6
The embodiment provides an epitaxial wafer of a light emitting diode, and referring to fig. 1 and fig. 3, the epitaxial wafer of the light emitting diode comprises a substrate 1, and a buffer layer 2, a U-GaN layer 3, an N-GaN layer 4, an active layer 5, an electron blocking layer 6 and a P-GaN layer 7 which are sequentially arranged on the substrate 1.
Wherein, the substrate 1 is a sapphire substrate, the buffer layer 2 is an AlN layer, and the thickness of the AlN layer is 15nm; the thickness of the U-GaN layer 3 was 2.5 μm. The doping concentration of Si in the N-GaN layer 4 was 2.5X 10 19 cm -3 The thickness was 2.8. Mu.m.
The active layer 5 includes quantum well layers 51 and quantum barrier layers (GaN layers, each having a thickness of 5 nm) alternately stacked, and the number of stacking cycles is 10. Each quantum well layer 51 includes a third quantum well sublayer 515, a defect blocking layer 516, a first quantum well sublayer 511, a first polarization control layer 512, a second quantum well sublayer 513, and a second polarization control layer 514, which are sequentially stacked.
Specifically, the first quantum well sublayer 511 is an InGaN layer having an In composition linearly increasing from 0.05 to 0.1 and a thickness of 0.5nm. The first polarization control layer 512 is an N-InGaN layer with an In content linearly increasing from 0.1 to 0.22, the doping element is Si and the doping concentration is 1.5 × 10 17 cm -3 The thickness was 0.5nm. The second quantum well sublayer 513 was an InGaN layer with an In composition fraction of 0.22 (maintained constant) and a thickness of 3.2nm. The second polarization control layer 514 is a P-InGaN layer with an In composition linearly decreasing from 0.22 to 0.1 and a doping element ofMg with a doping concentration of 5X 10 17 cm -3 The thickness is 1nm. The third quantum well sublayer 515 is a GaN layer with a thickness of 2nm; the defect blocking layer 516 is a SiN layer with a thickness of 5nm.
Wherein the electron blocking layer 6 is Al x In y Ga 1-x-y The N layer (x is gradually changed from 0.01 to 0.05, y is 0.01) is 15nm thick. The doping element of the P-GaN layer 7 is Mg, and the doping concentration is 2 multiplied by 10 20 cm -3 And the thickness is 15nm.
The preparation method of the light emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
(2) Growing a buffer layer on a substrate;
specifically, an AlN layer grows by adopting PVD; then loaded into MOCVD in H 2 Treating at 1050 deg.C for 5min under atmosphere, and nitriding.
(3) Growing a U-GaN layer on the buffer layer;
specifically, MOCVD is adopted to grow the U-GaN layer, the growth temperature is 1100 ℃, and the growth pressure is 150torr.
(4) Growing an N-GaN layer on the U-GaN layer;
specifically, an N-GaN layer is grown by MOCVD at 1120 ℃ under a growth pressure of 100torr.
(5) Growing an active layer on the N-GaN layer;
specifically, a quantum well layer and a quantum barrier layer are periodically grown in MOCVD to obtain an active layer;
wherein the growth temperature of the quantum barrier layer is 840 ℃, and the growth pressure is 400torr.
The preparation method of each quantum well layer comprises the following steps:
growing a third quantum well sub-layer;
specifically, a GaN layer is grown by MOCVD to serve as a first quantum well sublayer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(II) growing a defect barrier on the third quantum well sublayer
Specifically, an MOCVD is used to grow a SiN layer as a defect blocking layer. The growth temperature was 850 deg.C (maintained constant) and the growth pressure was 200torr.
(iii) growing a first quantum well sub-layer on the defect barrier layer;
specifically, an InGaN layer is grown by MOCVD as the first quantum well sub-layer. The growth temperature is gradually reduced from 830 ℃ to 790 ℃, the temperature reduction rate is 50 ℃/min, and the growth pressure is 200torr.
(IV) growing a first polarization control layer on the first quantum well sublayer;
specifically, an N-InGaN layer is grown by MOCVD and serves as a first polarization control layer. The growth temperature is gradually reduced from 830 ℃ to 790 ℃, the temperature reduction rate is 50 ℃/min, and the growth pressure is 200torr.
(v) growing a second quantum well sub-layer on the first polarization modulation layer;
specifically, an InGaN layer is grown by MOCVD as the second quantum well sub-layer. The growth temperature was 790 deg.C (maintained constant) and the growth pressure was 200torr.
(vi) growing a second polarization control layer on the second quantum well sublayer;
specifically, a P-InGaN layer is grown by MOCVD and used as a second polarization control layer. The growth temperature is gradually increased from 790 ℃ to 870 ℃, the heating rate is 100 ℃/min, and the growth pressure is 200torr.
(6) Growing an electron blocking layer on the active layer;
specifically, MOCVD is adopted to grow Al x In y Ga 1-x-y And the N layer is used as an electron blocking layer. The growth temperature was 960 ℃ and the growth pressure was 200torr.
(7) Growing a P-GaN layer on the electron blocking layer;
specifically, MOCVD is adopted to grow the P-GaN layer, the growth temperature is 985 ℃, and the growth pressure is 200torr.
Comparative example 1
This comparative example provides an epitaxial structure which is different from example 1 In that the quantum well layer is an InGaN layer, the In composition ratio is 0.25, the growth temperature is 790 ℃, and the growth pressure is 200torr.
Comparative example 2
This comparative example provides an epitaxial structure which is different from example 1 in that the first polarization regulating layer and the second polarization regulating layer are not provided in the quantum well layer, and accordingly, the preparation steps of the above two layers are not provided in the preparation method, and the rest is the same as example 1.
Comparative example 3
This comparative example provides an epitaxial structure, which is different from example 1 in that only the first polarization regulating layer is provided in the quantum well layer, and the second polarization regulating layer is not provided. Accordingly, in the preparation method, the preparation step of the second polarization control layer is not provided, and the rest is the same as that of example 1.
Comparative example 4
This comparative example provides an epitaxial structure, which is different from example 1 in that only the second polarization control layer is provided in the quantum well layer, and the first polarization control layer is not provided. Accordingly, in the manufacturing method, the manufacturing step of the first polarization control layer is not provided, and the rest is the same as that of example 1.
Comparative example 5
This comparative example provides an epitaxial structure which is different from example 1 In that the In composition ratio In the first quantum well sub-layer In the quantum well layer is 0.22, the In composition ratio In the second quantum well sub-layer is 0.08, and the rest is the same as example 1.
The light emitting diode epitaxial wafers obtained in the examples 1 to 6 and the comparative examples 1 to 5 were subjected to a brightness test, and the specific results were as follows:
Figure 416282DEST_PATH_IMAGE001
as can be seen from the table, when the conventional quantum well layer (comparative example 1) was changed to the quantum well layer structure of the present invention, the light emission efficiency was increased from 185.4mW to 190.5mW, indicating that the quantum well layer of the present invention can effectively increase the light emission efficiency. In addition, as can be seen from comparison between example 1 and comparative examples 2 to 4, when the quantum well layer structure in the present application is changed, it is difficult to effectively achieve the result of improving the light emission efficiency. As can be seen from comparison of example 1 with comparative example 5, when the distribution of the In component ratio In the quantum well layer In the present application was changed, the effect of improving the light emission efficiency was weak.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.

Claims (10)

1. A high-luminous-efficiency light emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a U-GaN layer, an N-GaN layer, an active layer, an electron barrier layer and a P-GaN layer which are sequentially arranged on the substrate, wherein the active layer comprises a plurality of quantum well layers and quantum barrier layers which are alternately stacked; the quantum well layer comprises a first quantum well sub-layer, a first polarization regulation layer, a second quantum well sub-layer and a second polarization regulation layer which are sequentially stacked;
the first quantum well sub-layer is an InGaN layer, the first polarization control layer is an N-InGaN layer, the second quantum well sub-layer is an InGaN layer, and the second polarization control layer is a P-InGaN layer;
the proportion of the In component In the first quantum well sub-layer is smaller than that In the second quantum well sub-layer.
2. The high-luminous-efficiency light-emitting diode epitaxial wafer as claimed in claim 1, wherein the thickness of the first quantum well sub-layer is 0.1-1nm, the thickness of the first polarization control layer is 0.1-1nm, the thickness of the second quantum well sub-layer is 1-5nm, and the thickness of the second polarization control layer is 0.2-2nm.
3. The high-luminous-efficiency light emitting diode epitaxial wafer as claimed In claim 1, wherein the In component In the first quantum well sub-layer has a ratio of 0.05 to 0.15, the In component In the first polarization control layer has a ratio of 0.1 to 0.3, the In component In the second quantum well sub-layer has a ratio of 0.15 to 0.3, and the In component In the second polarization control layer has a ratio of 0.1 to 0.3;
the doping element of the first polarization control layer is Si, and the doping concentration is 5 multiplied by 10 16 -5×10 17 cm -3 ；
The doping element of the second polarization control layer is Mg, and the doping concentration is 1 multiplied by 10 17 -1×10 18 cm -3 。
4. The high-luminous-efficiency light-emitting diode epitaxial wafer as claimed In claim 3, wherein the In component In the first quantum well sub-layer gradually increases along the growth direction of the epitaxial wafer, the In component In the first polarization control layer gradually increases along the growth direction of the epitaxial wafer, and the In component In the second polarization control layer gradually decreases along the growth direction of the epitaxial wafer.
5. The high-luminous-efficiency light-emitting diode epitaxial wafer as claimed in claim 1, wherein the quantum well layer comprises a third quantum well sub-layer, a defect barrier layer, a first quantum well sub-layer, a first polarization control layer, a second quantum well sub-layer and a second polarization control layer which are sequentially stacked;
the third quantum well sub-layer is a GaN layer, and the defect blocking layer is a SiN layer;
the thickness of the third quantum well sub-layer is 0.5-5nm, and the thickness of the defect barrier layer is 1-10nm.
6. A method for preparing a high luminous efficiency light emitting diode epitaxial wafer, which is used for preparing the high luminous efficiency light emitting diode epitaxial wafer as claimed in any one of claims 1 to 5, and comprises the following steps:
providing a substrate, and sequentially growing a buffer layer, a U-GaN layer, an N-GaN layer, an active layer, an electron blocking layer and a P-GaN layer on the substrate;
the active layer comprises a plurality of quantum well layers and quantum barrier layers which are alternately laminated, wherein each quantum well layer comprises a first quantum well sub-layer, a first polarization regulation and control layer, a second quantum well sub-layer and a second polarization regulation and control layer which are sequentially laminated;
the first quantum well sub-layer is an InGaN layer, the first polarization control layer is an N-InGaN layer, the second quantum well sub-layer is an InGaN layer, and the second polarization control layer is a P-InGaN layer.
7. The method according to claim 6, wherein the first quantum well sub-layer is grown at a temperature of 750-830 ℃ and a growth pressure of 50-500torr;
the growth temperature of the first polarization control layer is 750-830 ℃, and the growth pressure is 50-500torr;
the growth temperature of the second quantum well sub-layer is 830-900 ℃, and the growth pressure is 50-500torr;
the growth temperature of the second polarization control layer is 830-900 ℃, and the growth pressure is 50-500torr.
8. The method for preparing the high-luminous-efficiency light-emitting diode epitaxial wafer as claimed in claim 6 or 7, wherein the growth temperature is gradually reduced in the growth process of the first quantum well sub-layer, and the cooling rate is 20-100 ℃/min;
the growth temperature is gradually reduced in the growth process of the first polarization control layer, and the cooling rate is 20-100 ℃/min;
the growth temperature of the second polarization control layer gradually rises in the growth process, and the heating rate is 50-150 ℃/min.
9. The method for preparing the high-luminous-efficiency light-emitting diode epitaxial wafer as claimed in claim 6, wherein the quantum well layer comprises a third quantum well sub-layer, a defect barrier layer, a first quantum well sub-layer, a first polarization control layer, a second quantum well sub-layer and a second polarization control layer which are sequentially stacked; the third quantum well sub-layer is a GaN layer, and the defect barrier layer is a SiN layer;
the growth temperature of the third quantum well sublayer is 810-870 ℃, and the growth pressure is 50-500torr;
the growth temperature of the defect barrier layer is 810-870 ℃, and the growth pressure is 50-500torr.
10. A light emitting diode comprising the high luminous efficiency light emitting diode epitaxial wafer as claimed in any one of claims 1 to 5.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115377259A (en) * 2022-10-26 2022-11-22 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode
CN115799416A (en) * 2023-02-15 2023-03-14 江西兆驰半导体有限公司 Deep ultraviolet light emitting diode epitaxial wafer and preparation method thereof
CN115842078A (en) * 2023-02-10 2023-03-24 江西兆驰半导体有限公司 Deep ultraviolet LED epitaxial wafer, preparation method thereof and LED
CN115881865A (en) * 2023-03-03 2023-03-31 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode
CN117393667A (en) * 2023-12-13 2024-01-12 江西兆驰半导体有限公司 LED epitaxial wafer, preparation method thereof and LED

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100067504A (en) * 2008-12-11 2010-06-21 삼성엘이디 주식회사 Nitride semiconductor light emitting device using multilayer struture quantum barrier
WO2011090581A1 (en) * 2010-01-25 2011-07-28 Invenlux Corporation Strain balanced light emitting devices
CN103500779A (en) * 2013-09-03 2014-01-08 华灿光电股份有限公司 GaN-based light-emitting diode epitaxial wafer and manufacturing method thereof
WO2016011924A1 (en) * 2014-07-24 2016-01-28 映瑞光电科技(上海)有限公司 EPITAXIAL STRUCTURE FOR IMPROVING EFFICIENCY DROP OF GaN-BASED LED
CN106159047A (en) * 2016-06-03 2016-11-23 华南理工大学 There is the light emitting diode epitaxial structure at PN doping quantum base and preparation method thereof
CN109545924A (en) * 2018-09-26 2019-03-29 华灿光电(苏州）有限公司 A kind of LED epitaxial slice and its manufacturing method
CN109904288A (en) * 2019-01-18 2019-06-18 华灿光电（浙江）有限公司 Gallium nitride based LED epitaxial slice and its manufacturing method
CN111769180A (en) * 2020-07-10 2020-10-13 湘能华磊光电股份有限公司 LED epitaxial growth method suitable for small-spacing display screen
CN111769181A (en) * 2020-07-10 2020-10-13 湘能华磊光电股份有限公司 LED epitaxial growth method suitable for small-spacing display screen
CN112048710A (en) * 2020-09-07 2020-12-08 湘能华磊光电股份有限公司 LED epitaxial growth method for reducing blue shift quantity of LED light-emitting wavelength
CN114597293A (en) * 2022-05-06 2022-06-07 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer and preparation method thereof
CN114695610A (en) * 2022-05-31 2022-07-01 江西兆驰半导体有限公司 GaN-based LED epitaxial wafer, epitaxial growth method and LED chip
CN114725257A (en) * 2022-04-08 2022-07-08 江西兆驰半导体有限公司 GaN-based light emitting diode epitaxial wafer, preparation method thereof and light emitting diode
CN114883462A (en) * 2022-07-12 2022-08-09 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer and preparation method thereof

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100067504A (en) * 2008-12-11 2010-06-21 삼성엘이디 주식회사 Nitride semiconductor light emitting device using multilayer struture quantum barrier
WO2011090581A1 (en) * 2010-01-25 2011-07-28 Invenlux Corporation Strain balanced light emitting devices
CN103500779A (en) * 2013-09-03 2014-01-08 华灿光电股份有限公司 GaN-based light-emitting diode epitaxial wafer and manufacturing method thereof
WO2016011924A1 (en) * 2014-07-24 2016-01-28 映瑞光电科技(上海)有限公司 EPITAXIAL STRUCTURE FOR IMPROVING EFFICIENCY DROP OF GaN-BASED LED
CN106159047A (en) * 2016-06-03 2016-11-23 华南理工大学 There is the light emitting diode epitaxial structure at PN doping quantum base and preparation method thereof
CN109545924A (en) * 2018-09-26 2019-03-29 华灿光电(苏州）有限公司 A kind of LED epitaxial slice and its manufacturing method
CN109904288A (en) * 2019-01-18 2019-06-18 华灿光电（浙江）有限公司 Gallium nitride based LED epitaxial slice and its manufacturing method
CN111769180A (en) * 2020-07-10 2020-10-13 湘能华磊光电股份有限公司 LED epitaxial growth method suitable for small-spacing display screen
CN111769181A (en) * 2020-07-10 2020-10-13 湘能华磊光电股份有限公司 LED epitaxial growth method suitable for small-spacing display screen
CN112048710A (en) * 2020-09-07 2020-12-08 湘能华磊光电股份有限公司 LED epitaxial growth method for reducing blue shift quantity of LED light-emitting wavelength
CN114725257A (en) * 2022-04-08 2022-07-08 江西兆驰半导体有限公司 GaN-based light emitting diode epitaxial wafer, preparation method thereof and light emitting diode
CN114597293A (en) * 2022-05-06 2022-06-07 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer and preparation method thereof
CN114695610A (en) * 2022-05-31 2022-07-01 江西兆驰半导体有限公司 GaN-based LED epitaxial wafer, epitaxial growth method and LED chip
CN114883462A (en) * 2022-07-12 2022-08-09 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer and preparation method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115377259A (en) * 2022-10-26 2022-11-22 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode
CN115842078A (en) * 2023-02-10 2023-03-24 江西兆驰半导体有限公司 Deep ultraviolet LED epitaxial wafer, preparation method thereof and LED
CN115799416A (en) * 2023-02-15 2023-03-14 江西兆驰半导体有限公司 Deep ultraviolet light emitting diode epitaxial wafer and preparation method thereof
CN115799416B (en) * 2023-02-15 2023-04-14 江西兆驰半导体有限公司 Deep ultraviolet light-emitting diode epitaxial wafer and preparation method thereof
CN115881865A (en) * 2023-03-03 2023-03-31 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode
CN117393667A (en) * 2023-12-13 2024-01-12 江西兆驰半导体有限公司 LED epitaxial wafer, preparation method thereof and LED
CN117393667B (en) * 2023-12-13 2024-03-12 江西兆驰半导体有限公司 LED epitaxial wafer, preparation method thereof and LED

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