CN115224124A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN115224124A
CN115224124A CN202110423761.8A CN202110423761A CN115224124A CN 115224124 A CN115224124 A CN 115224124A CN 202110423761 A CN202110423761 A CN 202110423761A CN 115224124 A CN115224124 A CN 115224124A
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layer
semiconductor
isolation region
semiconductor device
channel
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陈纪孝
李凯霖
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202110423761.8A priority Critical patent/CN115224124A/zh
Priority to US17/335,026 priority patent/US11955541B2/en
Publication of CN115224124A publication Critical patent/CN115224124A/zh
Priority to US18/596,643 priority patent/US20240213361A1/en
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Abstract

本发明公开一种半导体元件及其制作方法，其中该半导体元件包括一基底，一缓冲层设置在该基底上，一通道层设置在该缓冲层上，一势垒层设置在该通道层上，一钝化层设置在该势垒层上，以及一元件隔离区，其贯穿该钝化层、该势垒层，以及至少部分该通道层，并且包围该半导体元件的一第一元件区。该元件隔离区具有沿着一深度方向变化的缺陷浓度，且在该通道层和该势垒层之间的一结附近具有最高的缺陷浓度。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件及其制作方法，特别是涉及一种包括元件隔离区的高电子迁移率晶体管及其制作方法。
背景技术
高电子迁移率晶体管(high electron mobility transistor,HEMT)为一种新兴的场效晶体管，其主要包括由多层不同半导体材料堆叠所构成的一异质结构(heterostructure)，通过半导体材料的选择可在异质结(heterojunction)附近区域形成一二维电子气层(two dimensional electron gas,2DEG)作为电流的通道区，具有高切换速度及响应频率，特别适合应用在功率转换器、低噪声放大器、射频(RF)或毫米波(MMW)等技术领域中。
为了达到简化制作工艺以及降低高电子迁移率晶体管的漏电流以提升击穿电压和输出功率从而获得改善的效能的目的，如何设计高电子迁移率晶体管之间的隔离结构仍为本领域积极研究的课题。
发明内容
本发明目的在于提供一种半导体元件及其制作方法，例如是一种高电子迁移率晶体管及其制作方法，利用离子注入来破坏外延叠层的晶格结构，从而在外延叠层中形成具有高缺陷浓度的区域，可束缚/捕捉(trap)自由电子，从而抑制或阻断电流路径，提供电性隔离的效果，可用作元件隔离区。另外，利用离子注入来形成元件隔离区，可简化制作工艺。
根据发明一实施例提供的一种半导体元件，包括一基底，一缓冲层设置在该基底上，一通道层设置在该缓冲层上，一势垒层设置在该通道层上，一钝化层设置在该势垒层上，以及一元件隔离区，其贯穿该钝化层以及该势垒层以及至少部分该通道层，并且包围该半导体元件的一第一元件区，其中该元件隔离区具有沿着一深度方向变化的缺陷浓度，且在该通道层和该势垒层之间的一结(接面)附近具有最高的缺陷浓度。
根据本发明另一实施例提供的一种半导体元件的制作方法，包括以下步骤。首先，提供一基底。接着，形成一缓冲层于该基底上，形成一通道层于该缓冲层上，形成一势垒层于该通道层上，再形成一钝化层于该势垒层上。然后，进行一离子注入制作工艺，以形成贯穿该钝化层、该势垒层，以及至少部分该通道层的一元件隔离区，其中该元件隔离区包围该半导体元件的一第一元件区，该元件隔离区具有沿着一深度方向变化的缺陷浓度，且在该通道层和该势垒层之间的一结附近具有最高的缺陷浓度。
附图说明
图1至图7为本发明一实施例的半导体元件的制作方法步骤示意图，其中各图的上部为半导体元件的平面图，下部为半导体元件的剖视图；
图8为本发明一实施例的半导体元件的示意图，其中上部为半导体元件的平面图，下部为半导体元件的剖视图；
图9为本发明一实施例的半导体元件的示意图，其中上部为半导体元件的平面图，下部为半导体元件的剖视图；
图10为本发明一实施例的元件隔离区142的缺陷浓度沿着深度方向(例如第三方向D3)的浓度曲线图。
主要元件符号说明
100 外延叠层
101 基底
102 成核层
104 过渡层
106 缓冲层
108 通道层
109 结
110 势垒层
112 半导体栅极层
130 钝化层
132 钝化层
140 离子注入制作工艺
142 元件隔离区
200 浓度曲线
112a 第一半导体栅极层
112b 第二半导体栅极层
152a 第一漏极接触
152b 第二漏极接触
154a 第一源极接触
154b 第二源极接触
162a 第一漏极电极
162b 第二漏极电极
164a 第一源极电极
164b 第二源极电极
166a 第一栅极电极
166b 第二栅极电极
2DEG 二维电子气层
D1 第一方向
D2 第二方向
D3 第三方向
Ra 第一元件区
Rb 第二元件区
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。需知悉的是，以下所举实施例可以在不脱离本揭露的精神下，将数个不同实施例中的特征进行替换、重组、混合以完成其他实施例。
为了使读者能容易了解及附图的简洁，本揭露中的多张附图只绘出显示装置的一部分，且附图中的特定元件并非依照实际比例绘图。此外，图中各元件的数量及尺寸仅作为示意，并非用来限制本揭露的范围。附图中，相同或相似的元件可以用相同的标号表示。文中所描述对于图形中相对元件的上下关系，在本领域的人都应能理解其是指物件的相对位置而言，因此都可以翻转而呈现相同的构件，此都应同属本说明书所揭露的范围。
在本说明书中，当元件或膜层被称为「在另一元件或膜层上」或「连接到另一元件或膜层」时，它可以直接在另一个元件或膜层上，或直接连接到另一个元件或膜层，或者两者之间可存在有其他元件或膜层。相对的，当元件被称为「直接在另一个元件或膜层上」，或「直接连接到另一个元件或膜层」时，两者之间不存在有插入的元件或膜层。
在本说明书中，「晶片」、「基底」或「基板」意指任何包含一暴露面，可依据本发明实施例所示在其上沉积材料，制作集成电路结构的结构物，例如布线层。需了解的是「基底」包含半导体晶片，但并不限于此。「基底」在制作工艺中也意指包含制作于其上的材料层的半导体结构物。
本发明的高电子迁移率晶体管可以是耗尽型(depletion mode)/常开型(normally-on)或增强型(enhancement mode)/常闭型(normally-off)的高电子迁移率晶体管，可应用在功率转换器、低噪声放大器、射频(RF)或毫米波(MMW)等技术领域中。
本发明实施例描述的高电子迁移率晶体管的栅极、源极和漏极的结构及形状仅为举例，以便于绘图及说明为目的，并不用于限制本发明。下文以包括金属-半导体栅极结构(metal-semiconductor gate structure)的高电子迁移率晶体管为例进行说明，应理解在其他实施例中，高电子迁移率晶体管可包括金属栅极结构(metal gate structure)。
图1至图7所绘示为根据本发明一实施例的半导体元件的制作方法步骤示意图。各图的上部为半导体元件在第一方向D1和第二方向D2定义的平面上的顶视平面图，各图的下部为沿着第一方向D1和第三方向D3切过半导体元件的剖视图。
如图1所示，本发明的高电子迁移率晶体管的制作方法步骤包括提供一基底101，接着依序在基底101上形成一外延叠层100。根据本发明一实施例，外延叠层100由下(靠近基底101的部分)而上(远离基底101的部分)可依序包括一成核层102、一过渡层104、一缓冲层106、一通道层108，以及一势垒层110。然后，再于势垒层110上形成一半导体栅极层112。
基底101可包括硅基底、碳化硅(SiC)基底、蓝宝石(sapphire)基底、氮化镓基底、氮化铝基底或其他适合的材料所形成的基底。成核层102、过渡层104、缓冲层106、通道层108以及势垒层110可分别包括三五族(III-V)半导体化合物材料，例如分别可包括氮化镓(GaN)、氮化铝镓(AlGaN)、渐变氮化铝镓(graded AlGaN)、氮化铝铟(AlInN)、氮化铟镓(InGaN)、氮化铝镓铟(AlGaInN)、含掺杂氮化镓(doped GaN)、氮化铝(AlN)，或上述的组合，但不限于此。根据本发明一实施例，成核层102可包括氮化铝(AlN)，过渡层104可包括氮化铝镓(AlGaN)或氮化镓(GaN)，缓冲层106可包括碳掺杂氮化镓(GaN:C)，通道层108可包括氮化镓(GaN)，势垒层110可包括氮化铝镓(AlGaN)，但不限于此。
通过选用合适的通道层108和势垒层110材料，使两者的结109附近的通道层108能带弯曲而形成一位能阱(potential well)，加上通道层108自发极化(spontaneouspolarization)与压电极化(piezoelectric polarization)特性，因而产生高浓度的电子汇聚于位能阱中，而于通道层108表面形成二维电子气层2DEG，作为高电子迁移率晶体管导通(on-state)时的一平面电流通道。
半导体栅极层112的材料可包含III-V族半导体化合物，并且可根据高电子迁移率晶体管的应用类型选择半导体栅极层112具有n导电型(negative conductive type)或p导电型(positive conductive type)，利用其内建电压(built-in voltage)来拉升位能阱的能带，而空乏(deplete)了大致上位于半导体栅极层112正下方的二维电子气层2DEG，以实现高电子迁移率晶体管的常闭(normally-off)操作。根据本发明一实施例，半导体栅极层112的材料可包含镁(Mg)、铁(Fe)或其他合适掺杂的p型氮化镓(p-GaN)，但不限于此。
根据本发明一实施例，可利用异质外延成长(heteroepitaxy growth)技术在基底101上依序形成外延叠层100及半导体栅极层112。适用的异质外延成长技术例如分子束外延(molecule beam epitaxy,MBE)、金属有机化学气相沉积(metal-organic chemicalvapor deposition,MOCVD)、氢化物气相沉积(hydride vapor phase deposition,HVPE)，但不限于此。
根据本发明一实施例，缓冲层106、通道层108及势垒层110可以分别具有单层结构，或者具有由多层半导体薄层构成的超晶格(superlattice)结构。通过各半导体薄层的材料选择及厚度调整，可调变能带结构、极化场强度及/或载流子分布，进而调整二维电子气层2DEG的电子分布及迁移率，以获得期望的效能。
请参考图2，接着可对半导体栅极层112进行一图案化制作工艺，获得第一半导体栅极层112a和第二半导体栅极层112b。
请参考图3，接着形成钝化层130全面性地覆盖势垒层110、第一半导体栅极层112a和第二半导体栅极层112b。钝化层130可包括单层或多层的介电材料，例如氮化铝(AlN)、氧化铝(Al2O3)、氮化硼(BN)、氮化硅(Si3N4)、氧化硅(SiO2)、氧化锆(ZrO2)、氧化铪(HfO2)、氧化镧(La2O3)、氧化镏(Lu2O3)、氧化镧镏(LaLuO3)、高介电常数(high-k)介电材料或其他适合的介电材料。可利用例如原子层沉积(ALD)、等离子体辅助原子层沉积(PEALD)、化学气相沉积(CVD)、等离子体辅助化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)等技术形成钝化层130，但不限于此。钝化层130可作为绝缘层及保护层，避免其下方的材料层于后续制作工艺中受到损害。
请参考图4，接着可利用形成在钝化层130上的一图案化掩模(图未示)为注入掩模进行一离子注入制作工艺140，将例如但不限于氩、氟、氮、硼、铟、及锗等其中至少一种离子注入至钝化层130、势垒层110以及通道层110的部分区域中以破坏晶格结构，由此形成贯穿钝化层130、势垒层110，以及通道层108的至少部分厚度，并且包围住半导体元件的第一元件区Ra和第二元件区Rb的元件隔离区142。根据本发明一实施例，当元件隔离区142的晶格结构被高度破坏，则元件隔离区142可包括非晶化(amorphous)结构。
元件隔离区142的晶格缺陷可束缚/捕捉(trap)自由电子，降低自由电子浓度。如图4所示，当缺陷浓度(damage concentration)高于束缚/捕捉二维电子气层2DEG的自由电子浓度时，二维电子气层2DEG在元件隔离区142会被断开，实现第一元件区Ra和第二元件区Rb之间的电性隔离。在一些实施例中，还可通过选择注入离子的种类以在元件隔离区142中形成带电核(charged center)来散射电子从而降低电子迁移率，进一步提升元件隔离区142电性隔离的效果。
为了确保隔离效果，元件隔离区142较佳是贯穿通道层108整体厚度并接触缓冲层106，底部可大致上切齐通道层108与缓冲层106之间的结，如图4所示，或者可再往下延伸至缓冲层106中(参考图9)。由此，当缓冲层106选用高阻值材料(例如GaN:C)，缓冲层106可与元件隔离区142共同构成完全围绕住元件区底部的隔离结构。
需特别说明的是，图4示出的第一半导体栅极层112a和第二半导体栅极层112b穿越第一元件区Ra和第二元件区Rb而包括略凸出于第一元件区Ra和第二元件区Rb的边缘而与元件隔离区142部分重叠的端部的设计仅为举例。在其他实施例中，可设计使第一半导体栅极层112a和第二半导体栅极层112b的端部切齐第一元件区Ra或第二元件区Rb而不重叠元件隔离区142，或者完全位于第一元件区Ra和第二元件区Rb范围内而不重叠元件隔离区142。
本发明特征之一在于，通过调整离子注入制作工艺140的制作工艺参数，例如调整注入角度、剂量及能量，使元件隔离区具有沿着深度方向变化的缺陷浓度。根据本发明一实施例，注入的离子例如是氩离子，注入角度可介于0度至10度之间，注入剂量可介于1E12atoms/cm2至1E15 atoms/cm2之间，注入能量可介于50KeV至150KeV之间，但不限于此。
根据本发明一实施例，离子注入制作工艺140可包括多步骤注入，以获得期望的缺陷浓度分布。举例来说，可先以较高能量(例如介于100KeV至150KeV之间)将氩离子离子注入至结109和通道层108之间的部分，然后再以较低能量(例如介于50KeV至90KeV之间)将氩离子离子注入至结109附近的部分。
图10所绘示为根据本发明一实施例的元件隔离区142的缺陷浓度沿着深度方向(例如第三方向D3)的浓度曲线200。为了便于理解，图10也标示出钝化层130、势垒层110、通道层108和二维电子气层2DEG的深度范围。如图10所示，元件隔离区142在通道层108和势垒层110之间的结109附近(即二维电子气层2DEG附近)具有一最高的缺陷浓度Cmax。缺陷浓度Cmax需大于或等于二维电子气层2DEG的自由电子浓度。根据本发明一实施例，当二维电子气层2DEG的自由电子浓度大约是9E19 count/cm3时，缺陷浓度Cmax可大约是2E20 count/cm3。
请参考图5，接着于第一半导体栅极层112a两侧形成第一漏极接触152a和第一源极接触154a，在第二半导体栅极层112b两侧形成第二漏极接触152b和第二源极接触154b。可利用任何适合的半导体制作工艺来形成第一漏极接触152a、第一源极接触154a、第二漏极接触152b，和第二源极接触154b，例如包括先形成穿过钝化层130、势垒层110并延伸至通道层108上部内的多个开口，然后以电子束蒸镀(electron beam evaporation)或溅镀(sputtering)的方法沉积一导电层填满该些开口，并利用掀离制作工艺(lift-offprocess)或光刻暨蚀刻制作工艺来移除多余的导电层。第一漏极接触152a、第一源极接触154a、第二漏极接触152b，和第二源极接触154b分别可包括金属材料，例如金(Au)、钨(W)、钴(Co)、镍(Ni)、钛(Ti)、钼(Mo)、铜(Cu)、铝(Al)、钽(Ta)、钯(Pd)、铂(Pt)、上述金属的化合物、复合层或合金，但不限于此。
需特别说明的是，图5示出的第一漏极接触152a、第一源极接触154a、第二漏极接触152b，和第二源极接触154b穿越第一元件区Ra和第二元件区Rb而包括略凸出于第一元件区Ra和第二元件区Rb的边缘而与元件隔离区142部分重叠的端部的设计仅为举例。在其他实施例中，可设计使第一漏极接触152a、第一源极接触154a、第二漏极接触152b，和第二源极接触154b的端部切齐第一元件区Ra或第二元件区Rb而不重叠元件隔离区142，或者完全位于第一元件区Ra和第二元件区Rb范围内而不重叠元件隔离区142。
请参考图6，接着形成钝化层132全面性地覆盖钝化层130、第一漏极接触152a、第一源极接触154a、第二漏极接触152b，和第二源极接触154b。钝化层132可包括单层或多层的介电材料，且钝化层132与钝化层130可包括相同或不同的介电材料。
请参考图7，接着形成穿过第一元件区Ra上的钝化层132并分别接触第一半导体栅极层112a、第一漏极接触152a和第一源极接触154a的第一栅极电极166a、第一漏极电极162a和第一源极电极164a，以及穿过第二元件区Rb上的钝化层132并分别接触第二半导体栅极层112b、第二漏极接触152b和第二源极接触154b的第二栅极电极166b、第二漏极电极162b和第二源极电极164b。第一栅极电极166a、第一漏极电极162a、第一源极电极164a、第二栅极电极166b、第二漏极电极162b，和第二源极电极164b分别可包括金属材料，例如金(Au)、钨(W)、钴(Co)、镍(Ni)、钛(Ti)、钼(Mo)、铜(Cu)、铝(Al)、钽(Ta)、钯(Pd)、铂(Pt)、上述金属的化合物、复合层或合金，但不限于此。应理解本发明的第一栅极电极166a、第一漏极电极162a、第一源极电极164a、第二栅极电极166b、第二漏极电极162b、第二源极电极164b的布局图案并不限于图7所示，在其他实施例中可根据设计需求调整。
需特别说明的是，前述第一漏极接触152a、第一源极接触154a、第二漏极接触152b、第二源极接触154b、第一栅极电极166a、第一漏极电极162a、第一源极电极164a、第二栅极电极166b、第二漏极电极162b，和第二源极电极164b的制作顺序仅为举例，本发明其他实施例中可采用不同于前述的制作顺序。例如，在一些实施例中，可于在形成元件隔离区142后，接着以相同步骤同时制作贯穿钝化层130的第一栅极电极166a、第二栅极电极166b和位于第一半导体栅极层112a和第二半导体栅极层112b两侧的第一漏极接触152a、第一源极接触154a、第二漏极接触152b，和第二源极接触154b。在这情况下，可省略钝化层132以及第一漏极电极162a、第一源极电极164a、第二漏极电极162b，和第二源极电极164b。其他本文未提到的制作顺序也可应用于本发明，只要可获得与二维电子气层接触的漏极接触、源极接触，以及与半导体栅极层接触的栅极电极，且均可与后续的内连线电路电连接即可。
请继续参考图7和图10。本发明提供的半导体元件，包括基底101，缓冲层106设置在基底101上、通道层108设置该缓冲层106上、势垒层110设置在通道层108上，以及钝化层130设置在势垒层110上。元件隔离区142贯穿钝化层130、势垒层110以及至少部分通道层108，并且分别包围住半导体元件的第一元件区Ra和第二元件区Rb。重要的是，如图10所示，元件隔离区142具有沿着深度方向(第三方向D3)变化的缺陷浓度，且在通道层108和势垒层110之间的结109附近具有一最高的缺陷浓度Cmax。
下文将针对本发明的不同实施例进行说明。为简化说明，以下说明主要描述各实施例不同之处，而不再对相同之处作重复赘述。各实施例中相同的元件是以相同的标号进行标示，以利于各实施例间互相对照。
图8所绘示为根据本发明一实施例的半导体元件的示意图，其中图8的上部为半导体元件在第一方向D1和第二方向D2定义的平面上的顶视平面图，图8的下部为沿着第一方向D1和第三方向D3切过半导体元件的剖视图。本实施例中，可通过调整离子注入制作工艺(例如图4的离子注入制作工艺140)的能量，使注入的离子最深仅达通道层108内部而不会贯穿通道层108。因此，形成的元件隔离区142会仅贯穿通道层108的部分厚度，且与缓冲层106之间由通道层108区隔开，不直接接触。本实施例可适用于通道层108的底部部分的自由电子(free electron)的浓度小于1E12 count/cm3的情况。
图9所绘示为根据本发明一实施例的半导体元件的示意图，其中图9的上部为半导体元件在第一方向D1和第二方向D2定义的平面上的顶视平面图，图9的下部为沿着第一方向D1和第三方向D3切过半导体元件的剖视图。相较于图7的实施例，在图9的实施例中，元件隔离区142可更往下延伸至部分缓冲层106中。
综合以上，本发明提供的半导体元件及其制作方法，利用离子注入来破坏外延叠层的晶格结构，从而在外延叠层中形成具有高缺陷浓度的区域，可束缚/捕捉(trap)自由电子，从而抑制或阻断电流路径，提供电性隔离的效果，可用作元件隔离区。另外，利用离子注入来形成元件隔离区，可简化制作工艺。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (19)

1.一种半导体元件，其特征在于，包括:
基底；
缓冲层，设置在该基底上；
通道层，设置在该缓冲层上；
势垒层，设置在该通道层上；
钝化层，设置在该势垒层上；以及
元件隔离区，贯穿该钝化层、该势垒层以及至少部分该通道层，并且包围该半导体元件的第一元件区，其中该元件隔离区具有沿着深度方向变化的缺陷浓度，且在该通道层和该势垒层之间的结附近具有最高的缺陷浓度。
2.如权利要求1所述的半导体元件，其中该元件隔离区贯穿该通道层的部分厚度，且不接触该缓冲层。
3.如权利要求1所述的半导体元件，其中该元件隔离区贯穿该通道层以及部分该缓冲层。
4.如权利要求1所述的半导体元件，其中该缓冲层包括碳掺杂氮化镓(GaN:C)，该通道层包括氮化镓(GaN)，该势垒层包括氮化铝镓(AlGaN)。
5.如权利要求1所述的半导体元件，另包括过渡层位于该基底与该缓冲层之间，该过渡层包括氮化铝镓(AlGaN)或氮化镓(GaN)。
6.如权利要求5所述的半导体元件，另包括成核层位于该过渡层与该基底之间，其中该成核层包括氮化铝。
7.如权利要求1所述的半导体元件，其中该钝化层包括氮化硅。
8.如权利要求1所述的半导体元件，另包括:
第一半导体栅极层，设置在该势垒层上；以及第一源极接触和第一漏极接触分别设置在该第一半导体栅极层两侧，其中在俯视图中，该第一半导体栅极层穿越该第一元件区。
9.如权利要求8所述的半导体元件，其中该半导体元件另包括第二元件区邻近该第一元件区并且被该元件隔离区包围。
10.如权利要求9所述的半导体元件，另包括:
第二半导体栅极层，设置在该势垒层上；以及
第二源极接触和第二漏极接触，分别设置在该第二半导体栅极层两侧，其中在该俯视图中，该第二半导体栅极层穿越该第二元件区，该第一漏极接触与该第二源极接触相邻设置在该元件隔离区的两侧。
11.如权利要求1所述的半导体元件，其中该元件隔离区包括氩、氟、氮、硼、铟、及锗等其中至少一种离子。
12.一种半导体元件的制作方法，包括:
提供基底；
形成缓冲层于该基底上；
形成通道层于该缓冲层上；
形成势垒层于该通道层上；
形成钝化层于该势垒层上；以及
进行离子注入制作工艺以形成贯穿该钝化层、该势垒层，以及至少部分该通道层的元件隔离区，其中该元件隔离区包围该半导体元件的第一元件区，该元件隔离区具有沿着一深度方向变化的缺陷浓度，且在该通道层和该势垒层之间的结附近具有最高的缺陷浓度。
13.如权利要求12所述的半导体元件的制作方法，其中该离子注入制作工艺包括将氩、氟、氮、硼、铟、及锗等其中至少一种离子注入至该钝化层、该势垒层以及至少部分该通道层中。
14.如权利要求12所述的半导体元件的制作方法，其中该离子注入制作工艺的注入角度介于0度至10度之间。
15.如权利要求12所述的半导体元件的制作方法，其中该离子注入制作工艺的注入剂量介于1E12 atoms/cm2至1E15 atoms/cm2之间。
16.如权利要求12所述的半导体元件的制作方法，另包括:
形成成核层于该基底上；
形成过渡层于该成核层上；以及
形成该缓冲层于该过渡层上。
17.如权利要求12所述的半导体元件的制作方法，其中该元件隔离区贯穿该通道层的部分厚度，且不接触该缓冲层。
18.如权利要求12所述的半导体元件的制作方法，其中该元件隔离区贯穿该通道层以及至少部分该缓冲层。
19.如权利要求12所述的半导体元件的制作方法，另包括:
形成第一半导体栅极层于该势垒层上；以及
形成第一源极接触和第一漏极接触于该第一半导体栅极层两侧并且贯穿该钝化层、该势垒层以及部分该通道层。
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