CN115223875A - 包括InGaAs沟道的FET装置及制造该FET装置的方法 - Google Patents

包括InGaAs沟道的FET装置及制造该FET装置的方法 Download PDF

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CN115223875A
CN115223875A CN202210867089.6A CN202210867089A CN115223875A CN 115223875 A CN115223875 A CN 115223875A CN 202210867089 A CN202210867089 A CN 202210867089A CN 115223875 A CN115223875 A CN 115223875A
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fet
channel
rvt
slvt
lvt
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博尔纳·J·奥布拉多维奇
帝泰什·拉克西特
马克·S·罗德尔
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供了包括InGaAs沟道的FET装置及制造该FET装置的方法。一种制造包括RVT装置、LVT装置和SLVT装置的FET装置的方法包括：确定用于所述RVT装置的InxGa1‑xAs中的x值，其中，x在0.0和1.0之间；确定用于所述LVT装置的InyGa1‑yAs中的y值，其中，y在0.0和1.0之间；确定用于所述SLVT装置的InzGa1‑zAs中的z值，其中，z在0.0和1.0之间；以及形成用于所述RVT装置的包括InxGa1‑xAs的第一沟道、用于所述LVT装置的包括InyGa1‑yAs的第二沟道以及用于所述SLVT装置的包括InzGa1‑zAs的第三沟道。

Description

包括InGaAs沟道的FET装置及制造该FET装置的方法
本申请是2017年3月21日提交到国家知识产权局的发明名称为“包括InGaAs沟道的FET装置及制造该FET装置的方法”的第201710168788.7号发明专利申请的分案申请。
本申请要求于2016年3月21日在美国专利商标局提交的第62/311,025号美国临时专利申请和于2016年11月8日在美国专利商标局提交的第15/346,535号美国非临时专利申请的优先权和权益，这些申请的全部内容通过引用包含于此。
技术领域
以下描述总体上涉及包括由砷化铟镓(InGaAs)形成的沟道的场效应晶体管(FET)。
背景技术
根据阈值电压(Vt)，FET装置可分类为常规阈值电压(RVT)装置、低阈值电压(LVT)装置或超低阈值电压(SLVT)装置。例如，为了分别达到0.1nA/μm、1nA/μm和10nA/μm的泄漏水平，RVT装置、LVT装置和SLVT装置的Vt值可分别是大约200mV、270mV和340mV。FET还可根据各种架构来分类，诸如鳍式场效应晶体管(finFET)、水平纳米片(hNS)FET、垂直FET、垂直纳米片(vNS)FET等。
基于由InGaAs形成的沟道(即，InGaAs沟道)的FET提供了高迁移率、高注入速度和低栅极电容的可能性。
通常，InGaAs沟道中的In分数和Ga分数总计为1。相关技术的InGaAs沟道通常使用53％的In分数。然而，In0.53Ga0.47As装置也倾向于具有小的带隙(大约75meV，明显低于对于Si的1.1eV)。这种小带隙的结果是大量的带带隧穿(BTBT)泄漏电流。由于BTBT泄漏电流对装置的目标阈值电压(Vt)敏感，所以RVT装置实际上会具有比LVT装置和SLVT装置更大的泄漏电流，从而使得难以满足其更严格的截止电流Ioff目标。
鉴于对用于移动SOC的RVT装置的泄漏电流约束(有效宽度(Weff)的晶体管为大约0.1nA/μm)，并且还因为BTBT泄漏电流对电源电压VDD和栅极长度Lg成指数地敏感，所以BTBT泄漏电流对VDD施加严格的上限(通常约0.7V)以及对Lg施加下限(通常约12.5nm)。这使得In0.53Ga0.47As不适用于标准片上系统(SOC)应用，例如，不适用于SOC的中央处理单元(CPU)核，这是因为在当前技术节点处的设计通常要求最大工作电压在0.9V-1.4V范围内，而即使在大约5nm技术节点处的设计通常也将要求最大工作电压在至少0.85V-0.9V范围内(对于最大振荡频率(fmax)的200mV过驱动，正常电压(Vnom)为0.65V-0.7V)。值得注意的是，对于SOC的工作电压范围，FET必须实现小于特定值的泄漏电流以使得总芯片泄漏功率小于或等于整个芯片功率的期望分数值。过驱动条件下的泄漏电流不能明显高于(不超过2X-3X)标称工作条件下的泄漏电流。
发明内容
根据本发明构思的一个或更多个实施例的一方面涉及一种增强包括InGaAs沟道的FET的性能的方法，其中，改进(例如，优化)In分数以满足BTBT泄漏电流标准和最大VDD。
根据本发明构思的一个或更多个实施例的一方面涉及具有InGaAs沟道的FET，其中，改进In分数以满足BTBT泄漏电流标准和最大VDD。
其它方面将在下面的描述中部分地阐述，并且，部分地通过描述将是清楚的，或者可通过所提出的实施例的实践来了解。
根据本发明构思的实施例，一种制造具有设定的BTBT泄漏电流和最大VDD的FET装置的方法包括：根据BTBT泄漏电流和最大VDD确定InxGa1-xAs中的x值；利用InxGa1-xAs形成沟道，其中，x不为0.53。
最大VDD可为0.85V，x可为40％或更小。
所述FET装置可为SLVT装置，x可为60％或更大。
所述FET装置可为RVT装置，x可为40％或更小。
根据本公开的实施例，一种制造用于RVT装置的具有设定的BTBT泄漏电流和最大VDD的FET装置的方法包括：根据BTBT泄漏电流和最大VDD确定InxGa1-xAs中的x的值；利用InxGa1-xAs形成第一沟道；确定用于LVT装置和/或SLVT装置的BTBT泄漏电流；根据用于LVT装置和/或SLVT装置的BTBT泄漏电流确定InyGa1-yAs中的y的值；利用InyGa1-yAs形成第二沟道，其中，y大于x。
在一个实施例中，y≥x+0.1。
根据本公开的另一个实施例，一种制造包括RVT装置、LVT装置和SLVT装置的FET装置的方法包括：确定用于RVT装置的InxGa1-xAs中的x值；确定用于LVT装置的InyGa1-yAs中的y值；确定用于SLVT装置的InzGa1-zAs中的z值；形成用于RVT装置的包括InxGa1-xAs的沟道、用于LVT装置的包括InyGa1-yAs的沟道和用于SLVT装置的包括InzGa1-zAs的沟道。
在一个实施例中，x<y≤z。
所述方法还可包括对于SLVT装置、LVT装置和RVT装置中的每个利用基本上相同的功函数材料形成栅电极。
根据本公开的实施例，一种FET装置包括栅电极和InxGa1-xAs沟道，其中，x不为0.53，BTBT泄漏电流为0.1nA/μm或更低，并且FET装置被构造为利用为0.75V或更大的最大VDD工作。
在一个实施例中，x为约0.3-0.4，并且FET装置被构造为利用0.8V或更大的最大VDD工作。
在一个实施例中，x为约0.2-0.3，并且FET装置被构造为利用0.8V或更大的最大VDD工作。
所述FET装置还可包括处于栅电极和沟道之间的缓冲层，缓冲层可包括InGaP和/或InAlAs。
所述FET装置还可包括第二FET，第二FET包括含有InyGa1-yAs的第二沟道，其中，y大于x，第二FET具有1nA/μm或更低的BTBT泄漏电流。
所述FET装置还可包括第三FET，第三FET包括含有InzGa1-zAs的第三沟道，其中，z大于或等于y，第三FET具有10nA/μm或更低的BTBT泄漏电流。
在一个实施例中，x<y<z。
在一个实施例中，0.2≤x<y≤z≤0.8。
根据实施例，一种FET装置包括SLVT装置、LVT装置和RVT装置，SLVT装置、LVT装置和RVT装置中的每个包括栅电极和InGaAs沟道，其中，用于SLVT装置、LVT装置和RVT装置中的每个的栅电极包括基本上相同的功函数材料和相同的厚度，用于RVT装置的InGaAs沟道由InxGa1-xAs表示，用于LVT装置的InGaAs沟道由InyGa1-yAs表示，用于SLVT装置的InGaAs沟道由InzGa1-zAs表示，其中，x与y和z不相同。
在一个实施例中，z＝y+0.1＝x+0.2。
所述FET装置还可包括处于栅电极和沟道之间的缓冲层，其中，用于SLVT装置和LVT装置的缓冲层包括InP，用于RVT装置的缓冲层包括InGaP和/或InAlAs。
所述FET装置可以是水平纳米片FET，并且相邻纳米片之间的竖直间隔为大约15nm或更小。
水平纳米片的宽度可为大约40nm或更小，并且水平纳米片的厚度可为大约10nm或更小。
所述FET装置可为fin FET、hNS FET、垂直FET或vNS FET。
附图说明
通过参照以下结合附图考虑时的详细描述，将更好地理解本发明构思的这些和其它特征和优势。理解的是，所选择的结构和特征在某些附图中未示出，以提供对其余结构和特征的更好的观察。
图1是hNS FET装置的剖视图的示意图。
图2是vNS FET装置的示意图。
图3是示出沟道厚度和栅极长度对BTBT泄漏电流的影响的曲线图。
图4是示出In分数对带隙的影响的曲线图。
图5是示出在各种栅极长度In含量对BTBT泄漏电流的影响的曲线图。
图6是示出In含量对相对迁移率的影响的曲线图。
图7是示出In含量对相对注入速度的影响的曲线图。
图8是示出在各种栅极长度InGaAs沟道中的In含量对Ieff的影响的曲线图。
图9是示出在各种栅极长度InGaAs沟道中的In含量对总寄生泄漏电流的影响的曲线图。
图10是根据本公开的实施例制造的FET装置的示意图。
图11是根据本公开的实施例制造的FET装置的示意图。
图12是根据本公开的实施例制造的FET装置的示意图。
图13是hNS多Vt装置的示意图。
图14示出了各种材料的导带。
图15是根据本发明公开的实施例制造的FET装置的示意图。
图16示出了给定Vt类型(flavor)所要求的组成。
图17是示出InGaAs沟道中的纳米片间隔对各种栅极长度下的栅极电容的影响的曲线图。
图18是示出InGaAs沟道中的纳米片间隔对栅极寄生电容的影响的曲线图。
图19是示出InGaAs沟道中的片厚度对BTBT泄漏电流的影响的曲线图。
图20是示出InGaAs沟道中的片厚度对Ieff的影响的曲线图。
具体实施方式
为了便于描述，可在这里使用诸如“在……之下”、“在……下方”、“下”、“在……上方”、和“上”等空间相对术语，来描述如附图中示出的一个元件或特征与另一(其它)元件或特征的关系。将理解的是，除了包含附图中描绘的方位之外，空间相对术语还意图包含装置在使用或操作中的不同方位。将参考作为本发明的理想示意图的平面图和/或剖面图来描述在此描述的实施例。因此，可根据制造技术和/或公差来修改示例视图。因此，本发明的实施例不限于视图中示出的实施例，而是包括基于制造工艺形成的构造的修改。因此，图中示出的区域具有示意性性质，图中示出的区域的形状是元件的区域的特定形状的示例并且不限制本发明的方面。
这里使用的术语仅是为了描述具体示例实施例的目的，而并非意图限制本发明。如这里所使用的，除非上下文另外明确指出，否则单数形式“一个(种)”和“所述(该)”也意图包括复数形式。还将理解的是，术语“包含”和/或“包括”用在本说明书中时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或更多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。
诸如“……中的至少一个(种)”或“选自于……中的至少一个(种)”的表述在一列元件(要素)之后时，修饰整列元件(要素)，而不是修饰该列的个别元件(要素)。另外，在描述本发明构思的实施例时“可以”的使用是指“本发明构思的一个或更多个实施例”。另外，术语“示例性”意图指示例或图示。将理解的是，当元件或层被称作“在”另一元件或层“上”，“连接到”、“结合到”或“邻近于”另一元件或层时，该元件或层可以直接在所述另一元件或层上，直接连接到、直接结合到或直接邻近于所述另一元件或层，或者可以存在一个或更多个中间元件或中间层。相反，当元件或层被称作“直接在”另一元件或层“上”，“直接连接到”、“直接结合到”或“直接邻近于”另一元件或层时，不存在中间元件或中间层。
如这里所使用的，术语“基本上”、“大约”和相似的术语被用作近似术语而不用作程度术语，并且意图解释能被本领域的普通技术人员意识到的在测量值或计算值中的固有偏差。另外，在此叙述的任何数值范围意图包括该叙述的范围内包含的相同数值精度的所有子范围。例如，范围“1.0至10.0”意图包括在叙述的最小值1.0和叙述的最大值10.0之间的所有子范围(并且包括叙述的最小值1.0和叙述的最大值10.0)，即，具有等于或大于1.0的最小值和等于或小于10.0的最大值，诸如，例如2.4至7.6。在此叙述的任何最大数值极限意图包括包含在此的所有较低数值极限，在本说明书中叙述的任何最小数值极限旨在包括包含在此的所有较高数值极限。因此，申请人保留修改本说明书(包括权利要求书)的权利，以明确地叙述在此明确地叙述的范围内包括的任何子范围。
FET根据其架构可分类为fin FET、hNS FET、垂直FET、vNS FET等。作为示例，图1是水平纳米片(hNS)FET的剖视图的示意图，图2是vNS FET的示意图。
参照图1，FET装置包括竖直地相互堆叠的多个沟道110，多个栅极堆叠件120围绕每个沟道110。每个栅极堆叠件120包括以环栅结构围绕沟道110的栅电极122、在栅电极122与沟道110之间的高K电介质124以及在栅电极122与源漏电极140之间的内部间隔件130。FET装置还包括基底150和一对接触焊盘160。
参照图2，FET装置包括体(bulk)源电极340、体漏电极350和它们之间的沟道310。FET装置还包括围绕沟道区的缓冲层360、在体源电极340和体漏电极350与栅电极322之间的间隔件330以及在栅电极322和沟道310之间的高K电介质324。
这里，沟道110和310可由InGaAs形成。高K电介质124和324可由诸如Al2O3和/或Hf2O3的合适的材料形成。间隔件130和330可由诸如金属氧化物或氮化物的K较低的电介质形成。在一个实施例中，间隔件130和330可由SiO2形成。缓冲层360可由磷化铟(InP)形成。源漏电极140、340和350可由任何合适的材料形成。在一个实施例中，源漏电极140、340和350由与沟道110和310基本相同的材料(诸如，InGaAs)形成，但具有比沟道110和310高的In分数。或者，源漏电极140、340和350可用合适的掺杂剂高度掺杂以提供低的接触电阻。栅电极122和322可由诸如TiN的合适的金属材料形成。基底可由用于工艺的OI版本(version)的SiO2或者诸如InAlAs的宽带隙半导体形成。
虽然在图1中示出了三个水平栅极并且在图2中示出了一个垂直栅极，但是本发明构思的实施例不限于此。
根据本公开的实施例，制造具有设定的BTBT泄漏电流和最大VDD的FET装置的方法包括根据BTBT泄漏电流和最大VDD确定InxGa1-xAs(x在0.0和1.0之间)中的x的值并且利用InxGa1-xAs形成沟道。
包括InGaAs沟道的FET装置的BTBT泄漏电流受到例如VDD、InGaAs中的In含量等多种因素的影响。当确定装置的VDD和BTBT泄漏电流时，可改进InxGa1-xAs中的x值，以使装置在最大VDD时具有期望的BTBT泄漏电流。这里，优化包括确定满足在最大VDD时的BTBT泄漏电流要求的In含量的范围以及从也提供令人满意的注入速度的范围中选择In含量。
对于RVT装置的BTBT泄漏电流值可为大约0.1nA/μm，对于LVT装置的BTBT泄漏电流值可为大约1nA/μm，对于SLVT装置的BTBT泄漏电流值可为大约10nA/μm。也就是说，BTBT标准对于RVT装置是最低的，对于SLVT装置是最高的。
在利用In0.53Ga0.47As的相关技术的FET装置中，由于RVT装置的BTBT泄漏电流对于Weff在约0.1nA/μm，并且因为BTBT泄漏电流对VDD成指数地敏感，所以这种相关技术装置的VDD限制为约0.7V或更低。然而，为了标准SOC应用的利用，当前技术节点处的设计通常需要最大工作电压在0.9V-1.4V范围内。甚至在尖端5nm技术节点处的设计通常也将需要最大工作电压至少在0.85V-0.9V范围内(对于fmax的200mV过驱动，Vnom为0.65V-0.7V)。这样，具有In0.53Ga0.47As沟道的FET装置不适合于标准SOC应用。
BTBT泄漏电流也受栅极长度和沟道厚度的影响。图3是示出沟道厚度和栅极长度对BTBT泄漏电流的影响的曲线图。在图3中，Ioff表示热离子电流，IBTBT是BTBT泄漏电流，tchannel表示沟道厚度。对于RVT装置，如图3中的虚线示出的部分所表明的，Ioff和IBTBT都应限制在0.1nA/μm以下。如图3所示，BTBT泄漏电流对栅极长度(Lg)具有很强的依赖性。
事实上，在VDD为0.75V时，具有In0.53Ga0.47As沟道的FET装置的最小栅极长度约为12.5nm。另一方面，由于沟道厚度对BTBT泄漏电流的影响，使得在VDD为0.75V时，最大沟道厚度小于5nm。对最小栅极长度和最大沟道厚度的这种限制对制造工艺提出了很大的挑战。此外，这种装置不可能支持+200mV的VDD过驱动。因此，利用In0.53Ga0.47As的相关技术的FET装置不适用于诸如移动SOC应用的标准SOC应用，并且不适合替代已经用于这种应用的硅(Si)装置。
当根据本发明构思的实施例制造FET装置时，由于基于对BTBT泄漏电流和最大VDD的要求而改进了InGaAs沟道中的In含量，所以其可以满足低BTBT泄漏电流和高VDD的要求并因此适合于标准SOC应用。
In含量影响FET装置中的多个性能因素。例如，包括较大的铟(In)分数将导致较小的带隙和较高的迁移率/注入速度。另一方面，包括较小的In分数可导致增大的带隙和相应地(呈指数地)较小的BTBT泄漏电流。也就是说，在迁移率和BTBT泄漏电流之间存在作为In分数的函数的权衡。
带隙设定隧穿势垒，并且带隙对In分数高度敏感。也就是说，减小In分数将相应地使隧穿势垒增大并使BTBT泄漏电流减小。图4是示出在各种栅极长度下In分数对带隙的影响的曲线图。如图4所示，当如相关技术的InGaAs装置中In含量为0.53时，带隙为约0.8eV。然而，当In含量为约0.3时，带隙接近于Si的在约1.1eV处的带隙。图5是示出在各种栅极长度In含量对BTBT泄漏电流的影响的曲线图。如图5所示，在In含量为40％时，在RVT装置中可以支持高达0.85V的VDD。
降低In的含量还会导致较低的迁移率和注入速度。图6是示出在各种栅极长度In含量对相对迁移率的影响的曲线图。如图6所示，当In含量升高时，相对迁移率增大。图7是示出在沟道厚度tch为5nm且VDD为0.8V时的In含量对相对注入速度的影响的曲线图。如图7所示，当In含量升高时，相对注入速度增大。然而，如图7所示，当In含量从53％降低到35％时，相对注入速度减小小于10％，这仍然是Si的情形的大约3倍。
这里，如图7所示，当In含量低于30％时，在In含量进一步降低时相对注入速度的损失相对更大。这种现象主要是由于从γ谷到L谷的电子溢出。根据本公开的实施例，可以使用拉伸应变诱导缓冲层来抑制从γ谷到L谷的电子溢出。例如，拉伸应变诱导缓冲层可包括InGaP和/或InAlAs，并且可位于沟道上。因此，In含量可为约20％至约30％，并且仍然具有可接受的相对注入速度。
图8是示出在各种栅极长度InGaAs沟道中的In含量对有效驱动电流Ieff的影响的曲线图。参照图8，值得注意的是，即使在In含量为40％时，InGaAs沟道仍然具有与RVT装置和SLVT装置中的每个的应变Si(S-Si)的Ieff相当的Ieff。此外，In含量越高，RVT装置和SLVT装置二者的Ieff越大。
图9是示出在各种栅极长度和0.85V的VDD下InGaAs沟道中的In含量对总寄生泄漏电流(具有寄生双极效应的BTBT泄漏电流)的影响的曲线图。参照图9，值得注意的是，为了要用在RVT区域中，在25nm或更大的栅极长度处需要40％或更低的In含量。例如，可以利用40％的In含量和30nm的栅极长度来制造RVT装置。这里，对于RVT装置，在低VDD时选择In含量以在支持VDD过驱动的同时获得最佳的功率、性能和区域。
如图9所示，In含量为50％的装置在15nm至35nm的栅极长度内似乎提供不了令人满意的总寄生泄漏电流，并且In含量越大，泄漏电流变得更大。清楚的是，具有53％的In含量的相关技术的InGaAs沟道将不能具有期望的泄漏性能。
另一方面，如果用在SLVT区域中，在约20nm的栅极长度时的In含量为60％是令人满意的。因此，对于SLVT装置，可利用60％或更大的In含量。也就是说，相对于RVT装置，在SLVT装置中可使用更大的In含量，因为SLVT装置不容易产生BTBT泄漏电流。从图8可以看出，这种SLVT装置具有显著高于应变Si(S-Si)装置的Ieff的Ieff。
另外，从图9可以观察到，对于所有的Vt类型，即RVT、LVT和SLVT，可以使用具有约40％的In和约30nm栅极长度的InGaAs沟道。也就是说，可以利用单个In分数在迁移率、泄漏电流和最大VDD方面具有最佳权衡。
更详细地，当如在RVT装置中BTBT泄漏电流较低(例如，0.1nA/μm)时，为了支持0.85V或更大的VDD，In的量可以低于0.5，例如0.4或更少。当如在SLVT装置中BTBT泄漏电流较高(例如，10nA/μm)时，In的量可以高于0.53，例如0.6或更大。
图10是根据本公开的实施例制造的FET装置的示意图。参照图10，FET装置包括栅电极722和InxGa1-xAs(x在0.0与1.0之间)沟道710，其中，x不为0.53，BTBT泄漏电流为0.1nA/μm或更低，FET装置被构造为以0.75V或更大的最大VDD工作。FET装置还包括基底750、源漏电极740、高K电介质724和间隔件730。
在一个实施例中，x可以是大约0.3-0.4，并且FET装置被构造为以0.8V或更大的最大VDD工作。
在一个实施例中，x可以是大约0.2-0.3，并且FET装置被构造为以0.8V或更大的最大VDD工作。
图11是根据本公开的实施例制造的FET装置的示意图。参照图11，FET装置还可包括处于栅电极722和沟道710之间的缓冲层880，缓冲层880可包括InGaP和/或InAlAs。
根据本公开的实施例的制造FET装置的工艺可以是任何合适的工艺，诸如在CA1196111A1、US 20060024874和US 20080296622中公开的工艺，所有这些申请的全部内容通过引用包含于此。
根据本公开的实施例，制造具有用于RVT装置的设定的第一BTBT泄漏电流和最大VDD的FET装置的方法包括：根据第一BTBT泄漏电流和最大VDD确定InxGa1-xAs中的x的值(x在0.0和1.0之间)，利用InxGa1-xAs形成第一沟道；确定LVT装置和/或SLVT装置的第二BTBT泄漏电流；根据LVT装置和/或SLVT装置的第二BTBT泄漏电流确定InyGa1-yAs中的y的值(y在0.0和1.0之间)，并且利用InyGa1-yAs形成第二沟道，其中y大于x。例如，y可以是x与0.1之和或更大。这里，具有相对较低In含量以满足BTBT泄漏电流和最大VDD要求的RVT装置与具有相对较高In含量的LVT装置和/或SLVT装置的组合比只有单个RVT装置提供更好的DC性能。
图12是根据本实施例制造的FET装置的示意图。参照图12，FET装置包括由InxGa1- xAs形成的第一沟道511和由InyGa1-yAs形成的第二沟道512。FET装置还包括围绕第一沟道511和第二沟道512的栅电极522、源漏电极540、高K电介质524、间隔件530和基底550。这里，选择InxGa1-xAs的第一沟道511中的In含量以满足BTBT泄漏电流和最大VDD，而InyGa1-yAs的第二沟道512中的In含量大于第一沟道511的In含量，从而提供更好的DC性能。例如，x可为0.4并且y可为0.6；或者，x可为0.3并且y可为0.6。
参照图15，FET装置还可以包括第三FET，第三FET包括含有InzGa1-zAs(z在0.0和1.0之间)的第三沟道，其中，z大于或等于y，并且第三FET具有10nA/μm或更低的BTBT泄漏电流。
在一个实施例中，x<y<z。
在一个实施例中，0.2≤x<y≤z≤0.8。
根据本公开的另一实施例，制造包括RVT装置、LVT装置和SLVT装置的FET装置的方法包括：确定用于RVT装置的InxGa1-xAs(x在0.0和1.0之间)中的x值；确定用于LVT装置的InyGa1-yAs(y在0.0和1.0之间)中的y值；确定用于SLVT装置的InzGa1-zAs(z在0.0和1.0之间)中的z值，并且形成用于RVT装置的包括InxGa1-xAs的第一沟道、用于LVT装置的包括InyGa1- yAs的第二沟道和用于SLVT装置的包括InzGa1-zAs的第三沟道。在一个实施例中，x<y≤z。这里，与仅单个RVT装置相比，具有相对较低In含量以满足BTBT泄漏电流和最大VDD要求的RVT装置与具有相对较高In含量的LVT装置和/或SLVT装置的组合提供更好的DC性能。
该方法还可包括对于SLVT装置、LVT装置和RVT装置中每个利用基本上相同的功函数材料形成栅电极。也就是说，单个功函数材料和厚度可被用于形成SLVT装置、LVT装置和RVT装置中的每个的栅电极。
制造具有多个不同Vt值(即，Vt调制)的装置的相关技术方法包括选择用于形成栅电极的金属材料，然后改变栅电极的厚度以实现期望的功函数(WF)，并因此获得期望的Vt值。然而，对于一些Vt值，会需要栅极厚度要相对高，例如，一些栅电极会具有约50nm的厚度。由于栅电极的增大的厚度，导致相邻沟道之间的间隔也相应地增大。
然而，根据本公开的实施例制造的装置可对于贯穿所有Vt值的栅电极保持基本相同的期望厚度。图13是hNS多Vt装置的示意图。参照图13，多Vt装置包括四个沟道811、812、813和814。如在插图中更详细地示出的，每个沟道具有厚度Tsheet并且被栅电极822包围。内部间隔件830在栅电极822和其相邻的源电极或漏电极之间。对于每个Vt装置，栅电极的厚度(VSP)是相同的。栅电极822的长度由Lg表示。通过调节In含量，每个沟道的导带(CB)能量被进行调制，因此能够根据In含量调整Vt。也就是说，沟道811-814中的每个都包括InGaAs，但是具有不同的In含量以提供四种不同的Vt类型。
图14示出了各种材料的导带。参照图14，通过调节InGaAs中的In含量，可将导带调节为针对期望的阈值电压Vt具有适合的功函数。
例如，可以首先根据BTBT标准确定SLVT装置中的In含量。相对于SLVT区域，对于LVT区域的In含量可以确定为使Vt增大大约70mV。然后，相对于LVT区域，RVT区域的In含量可以确定为使Vt增大大约70mV。
图15是根据本实施例制造的FET装置的示意图。参照图15，FET装置包括由InxGa1- xAs(x在0.0和1.0之间)形成的第一沟道611、由InyGa1-yAs(y在0.0和1.0之间)形成的第二沟道612以及由InzGa1-zAs(z在0.0和1.0之间)形成的第三沟道613。FET装置还包括围绕第一沟道611和第二沟道612的栅电极622、源漏电极640、高K电介质624、间隔件630和基底650。这里，选择InxGa1-xAs的第一沟道611中的In含量以满足BTBT泄漏电流和最大VDD，而第二沟道612和第三沟道613中的In含量大于第一沟道611的In含量，以提供更好的DC性能。例如，x可以是0.4并且y和z可以是0.6；或者，x可以是0.3并且y和z可以是0.6。
图16示出了给定Vt类型所要求的组成。参照图16，对于给定的片厚度和给定的栅极长度，SLVT装置可具有比RVT装置高的In含量。
在一个实施例中，用于LVT区域的In的分数可大于RVT区域中的In的分数，并且用于SLVT区域的In的分数可以大于LVT区域中的In的分数。例如，用于LVT区域的In的分数可以是RVT区域中的In的分数加0.1，并且用于SLVT区域的In的分数可以是RVT区域中的In的分数加0.2。
图19是示出InGaAs沟道中的片厚度对BTBT泄漏电流的影响的曲线图。图20是示出InGaAs沟道中的片厚度对Ieff的影响的曲线图。如图19和图20所示，不同的In含量可以用于RVT装置(例如，In含量为0.42)和SLVT装置(例如，In含量为0.5)。对于每种装置，可对于每种Vt类型分别改进(例如，优化)沟道厚度。因此，可以实现更薄的片或鳍(fin)间隔。
较薄的金属栅极能够实现比现有技术的多功函数金属更紧密的纳米片间隔(例如，竖直地或水平地)。此外，如图17所示，较小的纳米片间隔也使寄生电容减小。图17是示出了InGaAs沟道中的纳米片间隔对各种栅极长度下的栅极电容的影响的曲线图。图18是示出了InGaAs沟道中的纳米片间隔对栅极寄生电容的影响的曲线图。如图17和图18所示，在较小的间隔处，寄生电容Cpara(Cg关于Lg的曲线与Cg轴的截距)较小，并且栅极电容也较小。例如，当间隔从15nm减小到6nm时，可以实现栅极电容减小约25％。在一个实施例中，间隔可以约为15nm。在另一个实施例中，间隔可以约为6nm-9nm。根据实施例，在单个芯片上的Vt的范围内，In含量从约20％变化到约80％。
根据实施例，FET装置包括SLVT装置、LVT装置和RVT装置，SLVT装置、LVT装置和RVT装置中的每个包括栅电极和InGaAs沟道，其中，SLVT装置、LVT装置和RVT装置中的每个的栅电极包括基本相同的功函数材料和相同的厚度，用于RVT装置的InGaAs沟道由InxGa1-xAs(x在0.0和1.0之间)表示，用于LVT装置的InGaAs沟道由InyGa1-yAs(y在0.0和1.0之间)表示，用于SLVT装置的InGaAs沟道由InzGa1-zAs(z在0.0和1.0之间)表示，其中，x与y和z不相同。
在一个实施例中，z＝y+0.1＝x+0.2。
FET装置还可包括在栅电极和沟道之间的缓冲层，其中，用于SLVT装置和LVT装置的缓冲层包括InP，用于RVT装置的缓冲层包括InGaP和/或InAlAs。
FET装置可以是水平纳米片FET，并且相邻纳米片之间的竖直间隔为约15nm或更小。
水平纳米片的宽度可为约40nm或更小，并且水平纳米片的厚度可为约10nm或更小。
FET装置可为fin FET、hNS FET、垂直FET或vNS FET。
在一个实施例中，FET是nFET。
鉴于前述内容，本发明构思的实施例提供了一种增强包括InGaAs沟道的FET装置的性能的方法，其中，改进(例如，优化)In分数以满足BTBT泄漏电流标准和最大VDD。
鉴于前述内容，本发明构思的实施例提供了具有InGaAs沟道的FET装置，其中，改进In分数以满足BTBT泄漏电流标准和最大VDD。
尽管已经参考附图描述了本发明构思的一个或更多个实施例，但是本领域普通技术人员将理解，在不脱离由权利要求书及其等同物所限定的本发明构思的精神和范围的情况下，可在其中做出形式和细节上的各种改变。

Claims (17)

1.一种制造包括RVT装置、LVT装置和SLVT装置的FET装置的方法，所述方法包括：
确定用于所述RVT装置的InxGa1-xAs中的x值，其中，x在0.0和1.0之间；
确定用于所述LVT装置的InyGa1-yAs中的y值，其中，y在0.0和1.0之间；
确定用于所述SLVT装置的InzGa1-zAs中的z值，其中，z在0.0和1.0之间；以及
形成用于所述RVT装置的包括InxGa1-xAs的第一沟道、用于所述LVT装置的包括InyGa1- yAs的第二沟道以及用于所述SLVT装置的包括InzGa1-zAs的第三沟道。
2.根据权利要求1所述的方法，其中，x<y≤z。
3.根据权利要求2所述的方法，所述方法还包括对于SLVT装置、LVT装置和RVT装置中的每个形成包括基本上相同的功函数材料的栅电极。
4.一种FET装置，所述FET装置包括栅电极、InxGa1-xAs沟道以及处于栅电极和InxGa1-xAs沟道之间的缓冲层，其中，x在0.0和1.0之间，
其中，x不为0.53，
BTBT泄漏电流为0.1nA/μm或更低，
所述FET装置被构造为以至少0.7V的最大VDD工作。
5.根据权利要求4所述的FET装置，其中，x为0.3-0.4，所述FET装置被构造为以至少0.8V的最大VDD工作。
6.根据权利要求4所述的FET装置，其中，x为0.2-0.3，所述FET装置被构造为以至少0.8V的最大VDD工作。
7.根据权利要求4所述的FET装置，其中，所述缓冲层包括InGaP和/或InAlAs。
8.根据权利要求4所述的FET装置，所述FET装置还包括第二FET，所述第二FET包括第二沟道，所述第二沟道包括InyGa1-yAs，y在0.0和1.0之间，其中，y大于x，所述第二FET具有1nA/μm或更低的BTBT泄漏电流。
9.根据权利要求8所述的FET装置，所述FET装置还包括第三FET，所述第三FET包括第三沟道，所述第三沟道包括InzGa1-zAs，z在0.0和1.0之间，其中，z大于或等于y，所述第三FET具有10nA/μm或更低的BTBT泄漏电流。
10.根据权利要求9所述的FET装置，其中，x<y<z。
11.根据权利要求9所述的FET装置，其中，0.2≤x<y<z≤0.8。
12.一种FET装置，所述FET装置包括SLVT装置、LVT装置和RVT装置，SLVT装置、LVT装置和RVT装置中的每个包括栅电极和InGaAs沟道，其中，用于SLVT装置、LVT装置和RVT装置中的每个的栅电极包括基本相同的功函数材料和相同的厚度，用于RVT装置的InGaAs沟道由InxGa1-xAs表示，x在0.0和1.0之间，用于LVT装置的InGaAs沟道由InyGa1-yAs表示，y在0.0和1.0之间，用于SLVT装置的InGaAs沟道由InzGa1-zAs表示，z在0.0和1.0之间，其中，x与y和z不相同。
13.根据权利要求12所述的FET装置，其中，z＝y+0.1＝x+0.2。
14.根据权利要求12所述的FET装置，SLVT装置、LVT装置和RVT装置中的每个还包括处于栅电极和InGaAs沟道之间的缓冲层，其中，SLVT装置和LVT装置的缓冲层包括InP，用于RVT装置的缓冲层包括InGaP和/或InAlAs。
15.根据权利要求12所述的FET装置，其中，所述FET装置为水平纳米片FET，并且相邻水平纳米片之间的竖直间隔为15nm或更小。
16.根据权利要求15所述的FET装置，其中，水平纳米片的宽度为40nm或更小，并且水平纳米片的厚度为10nm或更小。
17.根据权利要求12所述的FET装置，其中，所述FET装置为fin FET、hNS FET、垂直FET和vNS FET中的至少一种。
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