CN115206972A - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
- Publication number
- CN115206972A CN115206972A CN202110402435.9A CN202110402435A CN115206972A CN 115206972 A CN115206972 A CN 115206972A CN 202110402435 A CN202110402435 A CN 202110402435A CN 115206972 A CN115206972 A CN 115206972A
- Authority
- CN
- China
- Prior art keywords
- substrate
- electrode layer
- conductive
- top surface
- orthographic projection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 153
- 239000003990 capacitor Substances 0.000 claims abstract description 59
- 239000000463 material Substances 0.000 claims description 19
- 238000003466 welding Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 12
- 239000004020 conductor Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
An embodiment of the present application provides a semiconductor structure, including: a substrate, and a first electrode layer disposed in the substrate; the capacitor structures are positioned on the substrate, and each capacitor structure is electrically connected with the first electrode layer; the conducting ring is positioned in the substrate and is insulated from the first electrode layer, and the orthographic projection of the conducting ring on the bottom surface of the substrate surrounds the orthographic projection of the first electrode layer on the bottom surface of the substrate; the second electrode layer covers the top and the side walls of all the capacitor structures, and the boundary line of the orthographic projection of the second electrode layer on the bottom surface of the substrate is positioned in the orthographic projection of the conductive ring on the bottom surface of the substrate; the conductive structure is positioned in the substrate, is electrically connected with the first electrode layer and is used for leading out an electric signal of the first electrode layer; the embodiment of the application aims at improving the electric leakage risk after the parallel unit capacitor forms the array capacitor.
Description
Technical Field
The present disclosure relates to semiconductor device structures, and more particularly to a semiconductor structure.
Background
High density and high performance Dynamic Random Access Memory (DRAM) requires sufficient cell capacitance. As DRAM dimensions decrease and density increases, the capacitor critical dimensions become smaller. In order to meet the capacitance requirement, those skilled in the art generally form an array capacitor by connecting a plurality of unit capacitors in parallel, thereby increasing the capacity of the storage capacitor.
However, the applicant has found that the risk of leakage of the array capacitor is greatly increased due to the shrinking of the device size, thereby greatly increasing the risk of leakage of the semiconductor device.
Disclosure of Invention
The embodiment of the application provides a semiconductor structure, and aims to improve the leakage risk after an array capacitor is formed by parallel unit capacitors.
To solve the above technical problem, an embodiment of the present application provides a semiconductor structure, including: a substrate, and a first electrode layer disposed in the substrate; the capacitor structures are positioned on the substrate, and each capacitor structure is electrically connected with the first electrode layer; the conducting ring is positioned in the substrate and is insulated from the first electrode layer, and the orthographic projection of the conducting ring on the bottom surface of the substrate surrounds the orthographic projection of the first electrode layer on the bottom surface of the substrate; the second electrode layer covers the tops and the side walls of all the capacitor structures, and the boundary line of the orthographic projection of the second electrode layer on the bottom surface of the substrate is positioned in the orthographic projection of the conductive ring on the bottom surface of the substrate; and the conductive structure is positioned in the substrate, is electrically connected with the first electrode layer and is used for leading out an electric signal of the first electrode layer.
Compared with the prior art, the first electrode layer is used as a lower electrode plate of the array capacitor, the second electrode layer is used as an upper electrode plate of the array capacitor, the extra conducting ring is arranged in the substrate, and the boundary line of the orthographic projection of the second electrode layer on the bottom surface of the substrate is positioned in the orthographic projection of the conducting ring on the bottom surface of the substrate, so that the leakage current of the second electrode layer generated by the etching problem can be transmitted into the conducting ring, the conducting ring is insulated from the first electrode layer, and the risk of electric leakage of the second electrode layer to the first electrode layer caused by the etching problem is avoided.
In addition, the top surface height of the conductive ring coincides with the top surface height of the first electrode layer in a direction perpendicular to the top surface of the substrate. The top surface of the conductive ring and the top surface of the first electrode layer are located at the same height, so that the conductive ring and the first electrode layer can be formed in one step, and the forming process of the semiconductor structure is simplified.
In addition, the bottom surface of the conductive ring is higher than the top surface of the first electrode layer in a direction perpendicular to the top surface of the substrate. The bottom surface height of the conducting ring is higher than the top surface height of the first electrode layer, so that the distance between the conducting ring and the second electrode layer is reduced, the leakage current of the second electrode layer is further ensured to be transmitted into the conducting ring, and the risk of electric leakage from the second electrode layer to the first electrode layer is avoided.
In addition, the orthographic projection of the conductive ring on the bottom surface of the substrate is not coincident with the orthographic projection of the first electrode layer on the bottom surface of the substrate.
In addition, the orthographic projection of the conductive ring on the bottom surface of the substrate is overlapped or adjacent to the orthographic projection part of the first electrode layer on the bottom surface of the substrate.
In addition, in the direction perpendicular to the top surface of the substrate, the thickness of the first electrode layer and the thickness of the conductive ring are the same, and the material of the first electrode layer and the material of the conductive ring are the same.
In addition, a boundary line of an orthographic projection of the second electrode layer on the bottom surface of the substrate is located at a center position, which is a center line of an orthographic projection width of the conductive ring on the bottom surface of the substrate. By locating the boundary line of the orthographic projection of the second electrode layer on the bottom surface of the substrate at the central position, it is further ensured that the leakage current of the second electrode layer will be transmitted into the conductive ring.
In addition, the conductive ring is a closed ring on a plane parallel to the plane of the substrate surface.
In addition, the substrate exposes a top surface of the first electrode layer, the capacitor structures are disposed on the first electrode layer, and a bottom surface of each capacitor structure is in contact with the top surface of the first electrode layer.
In addition, the capacitor structure penetrates through part of the substrate and is in contact with the first electrode layer.
In addition, the conductive structure includes: the conductive electrode plate is electrically connected with the first electrode layer, and the orthographic projection part of the conductive electrode plate on the bottom surface of the substrate is positioned outside the orthographic projection of the conductive ring on the bottom surface of the substrate; in the direction perpendicular to the top surface of the substrate, the conductive plate is located at a height lower than that of the conductive ring, and the height of the conductive plate is the same as that of the first electrode layer.
In addition, the conductive structure includes: the conductive electrode plate is arranged in the substrate in parallel with the first electrode layer, the height of the conductive electrode plate is lower than that of the first electrode layer in the direction vertical to the top surface of the substrate, and the orthographic projection part of the conductive electrode plate on the bottom surface of the substrate is positioned outside the orthographic projection of the conductive ring on the bottom surface of the substrate; and the first contact plug is used for electrically connecting the conductive electrode plate and the first electrode layer.
In addition, the conductive structure further includes: the conductive pads are arranged in the substrate in parallel with the conductive pole plates, the height of the conductive pole plates is lower than that of the conductive pads in the direction perpendicular to the top surface of the substrate, and the orthographic projections of the conductive pads on the bottom surface of the substrate are positioned outside the orthographic projections of the conductive rings on the bottom surface of the substrate; and the second contact pin is used for electrically connecting the conductive polar plate and the conductive welding plate.
In addition, the height of the top surface of the conductive pad is not lower than the height of the top surface of the first electrode layer in a direction perpendicular to the top surface of the substrate.
In addition, in the direction perpendicular to the top surface of the substrate, the height of the top surface of the conductive pad is consistent with the height of the top surface of the first electrode layer, the thickness of the conductive pad is the same as the thickness of the first electrode layer, and the material of the conductive pad is the same as the material of the first electrode layer.
In addition, in the direction perpendicular to the top surface of the substrate, the height of the top surface of the conductive pad is consistent with that of the top surface of the conductive ring, the thickness of the conductive pad is the same as that of the conductive ring, and the material of the conductive pad is the same as that of the conductive ring.
Drawings
Fig. 1 and fig. 2 are schematic cross-sectional views of a semiconductor structure in the prior art provided in the present application;
fig. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure;
fig. 4 is a schematic cross-sectional view of another semiconductor structure according to an embodiment of the present disclosure;
FIG. 5 is a schematic projection diagram of a first electrode layer and a conductive ring provided in the present embodiment based on FIGS. 3 and 4;
fig. 6 is a schematic cross-sectional view of another semiconductor structure according to an embodiment of the present disclosure;
FIGS. 7 and 8 are schematic projection views of a first electrode layer and a conductive ring provided in the present embodiment based on FIG. 6;
fig. 9 is a projection view of the second electrode layer and the conductive ring according to an embodiment of the disclosure.
Detailed Description
High density and high performance Dynamic Random Access Memory (DRAM) requires sufficient cell capacitance; as DRAM dimensions decrease and density increases, the capacitor critical dimensions become smaller and smaller. In order to meet the capacitance requirement, those skilled in the art generally form an array capacitor by connecting a plurality of unit capacitors in parallel, thereby increasing the capacity of the storage capacitor.
Referring to fig. 1, an upper electrode 12, a plurality of capacitor structures 20, and a lower electrode 11 located in a substrate 10 together form an array capacitor, where the upper electrode 12 is formed by depositing a conductive material and then performing a patterning process; at this time, the contact edge between the upper electrode 12 and the substrate 10, for example, at points a and B in fig. 1, may cause an over-etching problem, so as to reduce the dielectric layer distance between the upper electrode 12 and the lower electrode 11, increase the risk of short circuit between the upper electrode 12 and the lower electrode 11, and increase the capacitance of the array capacitor compared with the cell capacitor, thereby greatly increasing the risk of leakage of the semiconductor device.
Based on this, the related art adds the etching barrier layer 14 (refer to fig. 2) between the lower electrode 11 and the upper electrode 12, thereby increasing the thickness of the dielectric layer between the lower electrode 11 and the upper electrode 12, and blocking the path of the leakage current, that is, before the upper electrode 12 is formed, the first dielectric layer 13, the etching barrier layer 14, and the second dielectric layer 15 are deposited on the substrate 10, thereby increasing the dielectric layer gap between the upper electrode 12 and the lower electrode 11, and blocking the path of the leakage current, thereby avoiding the leakage risk caused by the etching problem.
To solve the above problem, an embodiment of the present application provides a semiconductor structure, including: a substrate, and a first electrode layer disposed in the substrate; the capacitor structures are positioned on the substrate, and each capacitor structure is electrically connected with the first electrode layer; the conducting ring is positioned in the substrate and is insulated from the first electrode layer, and the orthographic projection of the conducting ring on the bottom surface of the substrate surrounds the orthographic projection of the first electrode layer on the bottom surface of the substrate; the second electrode layer covers the top and the side walls of all the capacitor structures, and the boundary line of the orthographic projection of the second electrode layer on the bottom surface of the substrate is positioned in the orthographic projection of the conductive ring on the bottom surface of the substrate; and the conductive structure is positioned in the substrate, is electrically connected with the first electrode layer and is used for leading out an electric signal of the first electrode layer.
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be combined with each other and cited as reference to each other without contradiction.
Fig. 3 is a schematic cross-sectional structure diagram of a semiconductor structure provided in this embodiment, fig. 4 is a schematic cross-sectional structure diagram of another semiconductor structure provided in this embodiment, fig. 5 is a schematic projection diagram of a first electrode layer and a conductive ring provided in fig. 3 and 4 in this embodiment, fig. 6 is a schematic cross-sectional structure diagram of another semiconductor structure provided in this embodiment, fig. 7 and 8 are schematic projection diagrams of a first electrode layer and a conductive ring provided in fig. 6 in this embodiment, and fig. 9 is a schematic projection diagram of a second electrode layer and a conductive ring provided in this embodiment; the semiconductor structure provided in this embodiment is further described in detail below with reference to the drawings.
Referring to fig. 3 and 4, a semiconductor structure, comprising:
a substrate 101, and a first electrode layer 102 disposed in the substrate 101.
And a plurality of capacitor structures 201, wherein the capacitor structures 201 are located on the substrate 101, and each capacitor structure 201 is electrically connected with the first electrode layer 102.
And a second electrode layer 401 covering the top and sidewalls of all the capacitor structures 201.
Specifically, the plurality of capacitor structures 201 form an array capacitor, and the plurality of capacitor structures 201 in the array capacitor are connected in parallel with each other, so that the capacitance of the storage capacitor is increased.
In the present embodiment, the second electrode layer 401 is electrically connected to the capacitor structure 201 by directly covering the capacitor structure 201; the capacitor structures 201 are directly disposed on the first electrode layer 102, so as to be electrically connected to the first electrode layer 102, wherein the capacitor structures 201 are electrically connected to the first electrode layer 102 in the following manner:
referring to fig. 3, the capacitor structure 201 penetrates a portion of the substrate 101 and contacts the first electrode layer 102.
Referring to fig. 4, the substrate 101 exposes the top surface of the first electrode layer 102, the capacitor structures 201 are disposed on the first electrode layer 102, and the bottom surface of each capacitor structure 201 is in contact with the top surface of the first electrode layer 102.
In this embodiment, the first electrode layer 102 and the second electrode layer 401 are made of tungsten, which has low resistance and good stability, so as to ensure the electrical performance and stability of the formed storage capacitor. In other embodiments, the first electrode layer and the second electrode layer may be formed using any conductive material, including a metal conductive material, a non-metal conductive material, a semiconductor conductive material, and the like, for example, a conductive material such as polysilicon. Accordingly, in the present embodiment, the substrate 101 is made of silicon nitride, and in other embodiments, the substrate may be made of other semiconductor insulating materials, such as silicon oxide, silicon oxynitride, and the like.
In addition, the semiconductor structure further includes: and a conductive ring 103 located in the substrate 101 and insulated from the first electrode layer 102, wherein an orthographic projection of the conductive ring 103 on the bottom surface of the substrate 101 surrounds an orthographic projection of the first electrode layer 102 on the bottom surface of the substrate 101, and a boundary line of an orthographic projection of the second electrode layer 401 on the bottom surface of the substrate 101 is located in the orthographic projection of the conductive ring 103 on the bottom surface of the substrate 101.
It should be noted that, in the process of forming the second electrode layer 401, a deposition process is usually used to form a front second electrode film (not shown), and then the second electrode layer 401 as shown in fig. 3, fig. 4, or fig. 6 is formed by etching through an imaging process, at this time, an over-etching condition may be caused to the substrate 101 located at the edge of the second electrode layer 401, and the over-etching to the substrate 101 may cause a short-circuit point to be generated between the first electrode layer 102 and the second electrode layer 401, so that a leakage current in the second electrode layer 401 leaks into the first electrode layer 102 in the substrate 101.
In the embodiment, by positioning the boundary line of the orthographic projection of the second electrode layer 401 on the bottom of the substrate 101 in the orthographic projection of the conductive ring 103 on the bottom surface of the substrate 101, it is ensured that the projection of the edge of the second electrode layer 401 on the bottom surface of the substrate 101 is positioned in the projection of the conductive ring 103 on the bottom surface of the substrate 101, that is, in the direction perpendicular to the top surface of the substrate 101, the edge of the second electrode layer 401 is positioned above the conductive ring 103, and at this time, if a short circuit point is generated on the substrate 101 due to over-etching, the short circuit point is also positioned above the conductive ring 103; at this time, the leakage current of the second electrode layer 103 is introduced into the conductive ring 103; the conductive ring 103 is insulated from the first electrode layer 102, so that leakage current of the second electrode layer 401 is prevented from flowing into the first electrode layer 401, and the electrical performance of the formed array capacitor is prevented from being affected.
Further, the borderline of the orthographic projection of the second electrode layer 401 on the bottom surface of the substrate 101 is located at the center position, which is the center line of the orthographic projection width of the conductive ring 103 on the bottom surface of the substrate 101. By arranging the projected borderline of the second electrode layer 401 at the position of the center position of the conductive ring, it is further ensured that leakage current in the second electrode layer 401 will be conducted into the conductive ring 103.
In the present embodiment, the conductive ring 103 is a closed ring in a plane parallel to the plane of the surface of the substrate 101. By arranging the closed conductive ring 103, leakage current at any position of the second electrode layer 401 can be ensured to be led into the conductive ring 103, so that leakage current at any position of the second electrode layer 401 is prevented from being led into the first electrode layer 102, and the electrical performance of the formed array capacitor is further ensured.
It should be noted that, in other embodiments, the conductive ring may be an open ring disposed around the first electrode layer, so as to avoid leakage current between the first electrode layer and the second electrode layer to some extent, and effectively improve the electrical performance of the formed array capacitor.
In one example, referring to fig. 3 and 4, the top surface height of the conductive loop 103 coincides with the top surface height of the first electrode layer 102 in a direction perpendicular to the top surface of the substrate 101.
Since the conductive ring 103 and the top surface of the first electrode layer 102 have the same height, and in order to ensure the insulating arrangement between the first electrode layer 102 and the conductive ring 103, the orthographic projection of the conductive ring 103 on the bottom surface of the substrate 101 does not coincide with the orthographic projection of the first electrode layer 102 on the bottom surface of the substrate 101 (refer to fig. 5).
In addition, in a specific example, in a direction perpendicular to the top surface of the substrate 101, the thickness of the first electrode layer 102 and the thickness of the conductive ring 103 are the same, and the material of the first electrode layer 102 and the material of the conductive ring 103 are the same.
Since the height of the top surface between the conductive ring 103 and the first electrode layer 102 is the same, and the thickness between the conductive ring 103 and the first electrode layer 102 is the same, at this time, the height of the bottom surface between the conductive ring 103 and the first electrode layer 102 is also the same, and the conductive ring 103 and the first electrode layer 102 can be formed in the same process step, thereby simplifying the formation steps of the semiconductor structure.
In another example, referring to fig. 6, the bottom surface height of the conductive ring 103 is higher than the top surface height of the first electrode layer 102 in a direction perpendicular to the top surface of the substrate 101.
Since the height of the bottom surface of the conductive ring 103 is higher than the height of the top surface of the first electrode layer 102, i.e. in the direction perpendicular to the top surface of the substrate 101, the conductive ring 103 is located above the first electrode layer 102, the distance between the conductive ring 103 and the second electrode layer 401 is further reduced, and the effect of using the conductive ring 103 to introduce the leakage current into the second electrode layer 401 is ensured.
Since the conductive ring 103 and the first electrode layer 102 are disposed at different heights, in order to ensure the insulating arrangement between the first electrode layer 102 and the conductive ring 103, an orthographic projection of the conductive ring 103 on the bottom surface of the substrate 101 does not coincide with an orthographic projection of the first electrode layer 102 on the bottom surface of the substrate 101 (refer to fig. 5), or an orthographic projection of the conductive ring 103 on the bottom surface of the substrate 101 coincides with or is adjacent to an orthographic projection of the first electrode layer 102 on the bottom surface of the substrate 101, that is, an orthographic projection edge coincides with (refer to fig. 7) and the orthographic projection coincides (refer to fig. 8, a dashed frame in fig. 8 is an edge of the first electrode layer 102 projected on the bottom surface of the substrate). In an example, since the conductive ring 103 is not located at the same height as the first electrode layer 102, the conductive ring 103 and the first electrode layer 102 may be made of different materials, the conductive ring 103 is made of a conductive material, and the conductive ring 103 and the first electrode layer 102 are formed in different steps.
It should be noted that, in this example, the thicknesses of the conductive ring 103 and the first electrode layer 102 may be the same or different, and the application does not specifically limit the thickness of the conductive ring 103 in this example, and the thickness of the conductive ring 103 may be specifically set according to a specific application scenario.
Referring to fig. 9, in the present embodiment, a boundary line of an orthographic projection of the second electrode layer 401 on the bottom surface of the substrate 101 is located in an orthographic projection of the conductive ring 103 on the bottom surface of the substrate 101, wherein a dashed frame in fig. 9 is an edge of the conductive ring 103 projected on the bottom surface of the substrate.
When the height of the top surface of the conductive ring 103 is consistent with the height of the top surface of the first electrode layer 102 in the direction perpendicular to the top surface of the substrate 101, the conductive ring 103 is disposed around the first electrode layer 102, and then the electrical signal derivation of the first electrode layer 102 needs to additionally use a conductive structure.
Specifically, the conductive structure is located in the substrate 101, electrically connected to the first electrode layer 102 and used for deriving an electrical signal of the first electrode layer 102.
In a specific example, referring to fig. 3, 4 and 6, the conductive structure includes:
the conductive plate 301 is disposed in the substrate 101 in parallel with the first electrode layer 102, the conductive plate 301 is located at a height lower than that of the first electrode layer 102 in a direction perpendicular to the top surface of the substrate 101, and an orthographic projection portion of the conductive plate 301 is located outside an orthographic projection of the conductive ring 103.
A first contact plug 302 for electrically connecting the conductive electrode plate 301 and the first electrode layer.
Specifically, in this embodiment, the conductive plate 301 is made of polysilicon, and the first contact plug 302 is made of titanium nitride; in other embodiments, the conductive plate 301 and the first contact pin 302 may be formed using any conductive material.
In this example, the first electrode layer 102 and the conductive plate 301 are electrically connected through the first contact pin 302, so that the electrical signal in the first electrode layer 102 is led out to the conductive plate 301, and the orthographic projection of the conductive plate 301 is located outside the orthographic projection of the conductive ring 103, that is, the conductive plate 301 protrudes outside the conductive ring 103, and the leading out of the electrical signal of the conductive plate 301 can be realized through the protruding part.
Further, the conductive structure further includes:
and the conductive pad 304 is arranged in the substrate 101 in parallel with the conductive plate 301, the conductive plate 301 is located at a lower height than the conductive pad 304 in a direction perpendicular to the top surface of the substrate 101, and an orthographic projection of the conductive pad 304 is located outside the orthographic projection of the conductive ring 103.
And a second contact pin 303 for electrically connecting the conductive plate 301 and the conductive pad 304.
Specifically, in this embodiment, the conductive pad 304 is made of tungsten, and the second contact plug 303 is made of titanium nitride; in other embodiments, the conductive pad 304 and the second contact pin 302 may be formed using any conductive material.
In this example, the conductive electrode plate 301 and the conductive pad 304 are electrically connected through the second contact pin 303 to conduct an electrical signal in the first electrode plate 102 to the conductive pad 304, and the conductive pad 304 is disposed outside the conductive ring 103 to achieve electrical connection of the first electrode plate 102 through the conductive pad 304 to conduct an electrical signal of the first electrode plate 102.
In one example, referring to fig. 3, 4 and 6, the height of the top surface of the conductive pad 304 is not lower than the height of the top surface of the first electrode layer 102 in a direction perpendicular to the top surface of the substrate 101.
Referring to fig. 3 and 4, the height of the top surface of the conductive pad 304 coincides with the height of the top surface of the first electrode layer 102 in a direction perpendicular to the top surface of the substrate 101.
Specifically, in one example, referring to fig. 4, the thickness of the conductive pad 304 is the same as the thickness of the first electrode layer 102, and the material of the conductive pad 304 is the same as the material of the first electrode layer 102; since the height of the top surface between the conductive pad 304 and the first electrode layer 102 is the same, and the thickness between the conductive pad 304 and the first electrode layer 102 is the same, at this time, the height of the bottom surface between the conductive pad 304 and the first electrode layer 102 is also the same, so that the conductive pad 304 and the first electrode layer 102 can be formed in the same process step, thereby simplifying the formation steps of the semiconductor structure.
Referring to fig. 6, the height of the top surface of the conductive pad 304 is higher than the height of the top surface of the first electrode layer 102 in a direction perpendicular to the top surface of the substrate 101.
In addition, in other embodiments, the height of the top surface of the conductive pad may also be lower than the height of the top surface of the first electrode layer in the direction perpendicular to the top surface of the substrate.
In another example, referring to fig. 3 and 4, the height of the top surface of the conductive pad 304 is not lower than the height of the top surface of the conductive ring 103 in a direction perpendicular to the top surface of the substrate 101.
Referring to fig. 3 and 4, the top surface height of the conductive pad 304 coincides with the top surface height of the conductive ring 103 in a direction perpendicular to the top surface of the substrate 101; specifically, in one example, referring to fig. 4, the thickness of the conductive pad 304 is the same as the thickness of the conductive loop 103, and the material of the conductive pad 304 is the same as the material of the conductive loop 103; since the height of the top surface between the conductive pad 304 and the conductive ring 103 is the same, and the thickness between the conductive pad 304 and the conductive ring 103 is the same, at this time, the height of the bottom surface between the conductive pad 304 and the conductive ring 103 is also the same, so that the conductive pad 304 and the conductive ring 103 can be formed in the same process step, thereby simplifying the formation steps of the semiconductor structure.
Further, in a direction perpendicular to the top surface of the substrate 101, the top surfaces of the conductive pad 304, the first electrode layer 102, and the conductive ring 103 are uniform in height, and the thicknesses and materials of the conductive pad 304, the first electrode layer 102, and the conductive ring 103 are the same.
Since the heights of the top surfaces among the conductive pad 304, the first electrode layer 102 and the conductive ring 103 are the same and the thicknesses are the same, the heights of the bottom surfaces among the conductive pad 304, the first electrode layer 102 and the conductive ring 103 are also the same, and the conductive pad 304, the first electrode layer 102 and the conductive ring 103 can be formed in the same process step, thereby further simplifying the formation steps of the semiconductor structure.
In addition, referring to fig. 6, in other embodiments, the height of the top surface of the conductive pad 304 may also be lower than the height of the top surface of the conductive ring 103 in a direction perpendicular to the top surface of the substrate 101.
The above examples are applicable to any conductive ring 103 structure and have stable performance, and in another specific example, if the conductive ring 103 and the first electrode layer 102 are not located at the same height (refer to fig. 6), the conductive structure can be led out in the horizontal direction of the first electrode layer 102, that is, the first electrode layer 102 is extended, so as to lead out the electrical signal of the first electrode layer 102. Specifically, the conductive structure includes: and the conductive plate is electrically connected with the first electrode layer 102, an orthographic projection part of the conductive plate on the bottom surface of the substrate is positioned outside an orthographic projection of the conductive ring 103 on the bottom surface of the substrate 101, in a direction perpendicular to the top surface of the substrate 101, the conductive plate is positioned at a height lower than that of the conductive ring 103, and the height of the conductive plate is the same as that of the first electrode layer 102.
If the conductive ring 103 is an open-loop structure, the electrical signal of the first electrode layer 102 can be derived by leading out the conductive structure in the horizontal direction of the first electrode layer 102 and passing the conductive structure through the opening of the conductive ring 103.
Compared with the prior art, the first electrode layer is used as a lower electrode plate of the array capacitor, the second electrode layer is used as an upper electrode plate of the array capacitor, the extra conducting ring is arranged in the substrate, and the boundary line of the orthographic projection of the second electrode layer on the bottom surface of the substrate is located in the orthographic projection of the conducting ring on the bottom surface of the substrate, so that the leakage current of the second electrode layer generated by the etching problem can be transmitted into the conducting ring, and the conducting ring is insulated from the first electrode layer, so that the risk of leakage of the second electrode layer to the first electrode layer caused by the etching problem is avoided.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice.
Claims (16)
1. A semiconductor structure, comprising:
a substrate, and a first electrode layer disposed in the substrate;
a plurality of capacitor structures located on the substrate, each capacitor structure electrically connected to the first electrode layer;
the conductive ring is positioned in the substrate and is insulated from the first electrode layer, and the orthographic projection of the conductive ring on the bottom surface of the substrate surrounds the orthographic projection of the first electrode layer on the bottom surface of the substrate;
the second electrode layer covers the top and the side walls of all the capacitor structures, and the boundary line of the orthographic projection of the second electrode layer on the bottom surface of the substrate is positioned in the orthographic projection of the conductive ring on the bottom surface of the substrate;
and the conductive structure is positioned in the substrate, is electrically connected with the first electrode layer and is used for deriving an electric signal of the first electrode layer.
2. The semiconductor structure of claim 1, wherein a top surface height of the conductive ring coincides with a top surface height of the first electrode layer in a direction perpendicular to the top surface of the substrate.
3. The semiconductor structure of claim 1, wherein a height of a bottom surface of the conductive ring is higher than a height of a top surface of the first electrode layer in a direction perpendicular to the top surface of the substrate.
4. The semiconductor structure of claim 2 or 3, wherein an orthographic projection of the conductive ring on the bottom surface of the substrate is not coincident with an orthographic projection of the first electrode layer on the bottom surface of the substrate.
5. The semiconductor structure of claim 3, wherein an orthographic projection of the conductive ring on the bottom surface of the substrate coincides with or is adjacent to an orthographic projection of the first electrode layer on the bottom surface of the substrate.
6. The semiconductor structure of claim 2, wherein a thickness of the first electrode layer and a thickness of the conductive ring are the same, and a material of the first electrode layer and a material of the conductive ring are the same, in a direction perpendicular to the top surface of the substrate.
7. The semiconductor structure of claim 1, wherein a boundary line of an orthographic projection of the second electrode layer on the bottom surface of the substrate is located at a center position, the center position being a center line of an orthographic projection width of the conductive ring on the bottom surface of the substrate.
8. The semiconductor structure of claim 1, wherein the conductive ring is a closed ring in a plane parallel to a plane of the substrate surface.
9. The semiconductor structure of claim 1, wherein the substrate exposes a top surface of the first electrode layer, wherein the capacitor structures are disposed on the first electrode layer, and wherein a bottom surface of each of the capacitor structures is in contact with the top surface of the first electrode layer.
10. The semiconductor structure of claim 1, wherein the capacitor structure extends through a portion of the substrate and contacts the first electrode layer.
11. The semiconductor structure of claim 3, wherein the conductive structure comprises:
the conductive electrode plate is electrically connected with the first electrode layer, and the orthographic projection part of the conductive electrode plate on the bottom surface of the substrate is positioned outside the orthographic projection of the conductive ring on the bottom surface of the substrate;
in a direction perpendicular to the top surface of the substrate, the conductive plate is located at a height lower than that of the conductive ring, and the height of the conductive plate is the same as that of the first electrode layer.
12. The semiconductor structure of claim 1, wherein the conductive structure comprises:
the conductive electrode plate is arranged in the substrate in parallel with the first electrode layer, the height of the conductive electrode plate is lower than that of the first electrode layer in the direction perpendicular to the top surface of the substrate, and the orthographic projection part of the conductive electrode plate on the bottom surface of the substrate is positioned outside the orthographic projection of the conductive ring on the bottom surface of the substrate;
and the first contact pin is used for electrically connecting the conductive electrode plate and the first electrode layer.
13. The semiconductor structure of claim 12, wherein the conductive structure further comprises:
the conductive pads are arranged in the substrate in parallel with the conductive plates, the height of the conductive plates is lower than that of the conductive pads in the direction perpendicular to the top surface of the substrate, and the orthographic projections of the conductive pads on the bottom surface of the substrate are positioned outside the orthographic projections of the conductive rings on the bottom surface of the substrate;
and the second contact pin is used for electrically connecting the conductive polar plate and the conductive welding disc.
14. The semiconductor structure of claim 13, wherein a top surface height of the conductive pad is not less than a top surface height of the first electrode layer in a direction perpendicular to the top surface of the substrate.
15. The semiconductor structure of claim 14, wherein a height of a top surface of the conductive pad coincides with a height of a top surface of the first electrode layer in a direction perpendicular to the top surface of the substrate, a thickness of the conductive pad is the same as a thickness of the first electrode layer, and a material of the conductive pad is the same as a material of the first electrode layer.
16. The semiconductor structure of claim 14 or 15, wherein a height of a top surface of the conductive pad coincides with a height of a top surface of the conductive loop in a direction perpendicular to the top surface of the substrate, a thickness of the conductive pad is the same as a thickness of the conductive loop, and a material of the conductive pad is the same as a material of the conductive loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110402435.9A CN115206972B (en) | 2021-04-14 | 2021-04-14 | Semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110402435.9A CN115206972B (en) | 2021-04-14 | 2021-04-14 | Semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115206972A true CN115206972A (en) | 2022-10-18 |
| CN115206972B CN115206972B (en) | 2024-06-21 |
Family
ID=83574163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110402435.9A Active CN115206972B (en) | 2021-04-14 | 2021-04-14 | Semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115206972B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115867127A (en) * | 2023-03-03 | 2023-03-28 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01235268A (en) * | 1988-03-15 | 1989-09-20 | Toshiba Corp | Semiconductor memory device and manufacture thereof |
| US20020195631A1 (en) * | 2001-06-26 | 2002-12-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| US20110198679A1 (en) * | 2010-02-15 | 2011-08-18 | Elpida Memory, Inc. | Semiconductor device with vertical transistor |
| US20200052064A1 (en) * | 2018-08-09 | 2020-02-13 | Shenzhen Weitongbo Technology Co., Ltd. | Capacitor and method for fabricating the same |
| US10622451B1 (en) * | 2018-12-07 | 2020-04-14 | National Cheng Kung University | Flash memory with multiple control gates and flash memory array device made thereof |
| CN111211092A (en) * | 2018-11-22 | 2020-05-29 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN111682027A (en) * | 2020-05-29 | 2020-09-18 | 上海中航光电子有限公司 | Array substrate, display module and display device |
-
2021
- 2021-04-14 CN CN202110402435.9A patent/CN115206972B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01235268A (en) * | 1988-03-15 | 1989-09-20 | Toshiba Corp | Semiconductor memory device and manufacture thereof |
| US20020195631A1 (en) * | 2001-06-26 | 2002-12-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| US20110198679A1 (en) * | 2010-02-15 | 2011-08-18 | Elpida Memory, Inc. | Semiconductor device with vertical transistor |
| US20200052064A1 (en) * | 2018-08-09 | 2020-02-13 | Shenzhen Weitongbo Technology Co., Ltd. | Capacitor and method for fabricating the same |
| CN111033780A (en) * | 2018-08-09 | 2020-04-17 | 深圳市为通博科技有限责任公司 | Capacitor and manufacturing method thereof |
| CN111211092A (en) * | 2018-11-22 | 2020-05-29 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| US10622451B1 (en) * | 2018-12-07 | 2020-04-14 | National Cheng Kung University | Flash memory with multiple control gates and flash memory array device made thereof |
| CN111682027A (en) * | 2020-05-29 | 2020-09-18 | 上海中航光电子有限公司 | Array substrate, display module and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115867127A (en) * | 2023-03-03 | 2023-03-28 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115206972B (en) | 2024-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102669885B1 (en) | Semiconductor Device | |
| CN115206972A (en) | Semiconductor structure | |
| US20220059435A1 (en) | Semiconductor structure and method of manufacturing thereof | |
| CN114121962A (en) | Dynamic random access memory device and forming method thereof | |
| CN217955857U (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN114446955A (en) | Semiconductor structure and manufacturing method thereof | |
| CN113838852B (en) | Semiconductor memory device and method of forming the same | |
| KR20000008446A (en) | High integrated semiconductor device and methode thereof | |
| CN218039204U (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN215933602U (en) | Semiconductor device with a plurality of semiconductor chips | |
| US12009324B2 (en) | Semiconductor structure and method for forming semiconductor structure | |
| CN215183961U (en) | Semiconductor package | |
| CN216435901U (en) | Semiconductor memory device with a plurality of memory cells | |
| CN218920890U (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| US20220271030A1 (en) | Integrated circuit comprising a three-dimensional capacitor | |
| US11825644B2 (en) | Semiconductor memory device | |
| CN215933603U (en) | Semiconductor memory device with a plurality of memory cells | |
| CN216818341U (en) | Semiconductor memory device with a plurality of memory cells | |
| CN113764419B (en) | Semiconductor device and method for forming the same | |
| US20230403843A1 (en) | Semiconductor device and method of fabricating the same | |
| EP4319528A1 (en) | Semiconductor structure as well as manufacturing method therefor, storage chip, and electronic device | |
| WO2024092868A1 (en) | Semiconductor structure and manufacturing method therefor | |
| WO2024060477A1 (en) | Semiconductor structure and method for forming same | |
| CN117352491A (en) | Semiconductor structure and manufacturing method thereof | |
| CN117373996A (en) | Semiconductor structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |