CN115188821A - A kind of gallium nitride HEMT device and preparation method thereof - Google Patents

Abstract

The invention relates to a gallium nitride HEMT device and a preparation method thereof. The source electrode and the drain electrode are both located on the channel layer, and the channel layer is provided with an insertion layer, a barrier layer and a P-GaN layer stacked in sequence from bottom to top, and the insertion layer is located between the source electrode and the drain electrode. The insulating dielectric layer is located on the barrier layer and the P-GaN layer, and the second insulating dielectric layer is located on the first insulating dielectric layer. The source electrode and the drain electrode respectively form ohmic contact with the barrier layer. The source and drain electrodes are interfacially treated using a low temperature supercritical fluid process before and after metal deposition. The invention adopts the low temperature process of supercritical fluid for interface treatment, which is used to improve the quality of the interface layer of the gallium nitride HEMT and make up for the defects of the interface layer. At the same time, the low-temperature annealing technology is used to improve the stability of the ohmic contact and the voltage withstand capability of the drain electrode, which provides an effective method for the preparation of high-performance gallium nitride HEMT devices.

Description

A kind of gallium nitride HEMT device and preparation method thereof

technical field

The invention belongs to the technical field of power semiconductor devices, and in particular relates to a gallium nitride HEMT device and a preparation method thereof.

Background technique

Gallium nitride semiconductor materials have high band gap, high breakdown field strength, high electron mobility, high withstand voltage, and heat resistance. HEMT devices made with it are very suitable for applications due to their excellent switching characteristics and withstand voltage capabilities. In the field of high-power power electronics and microwave radio frequency.

For power devices, improving the interface layer defects and improving the stability of the ohmic contact are the key nodes in the process flow of gallium nitride devices. The size of the ohmic contact resistance has a direct impact on the performance of various devices. The contact resistance will lead to the degradation of the output power, gain, and power-added efficiency of the device; the additional loss will also increase the channel temperature of the device and affect the stability of the device.

After the commonly used metal deposition process for source and drain electrodes, high-temperature annealing is often required to eliminate the interface layer damage caused by thermal radiation. However, high-temperature annealing also leads to the decomposition and re-oxidation of electrode materials, which reduces the dielectric strength of the dielectric layer. Reliability and withstand voltage capability of source and drain electrodes.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a gallium nitride HEMT device and a preparation method thereof.

The technical problem to be solved by the present invention is realized by the following technical solutions:

The present invention provides a gallium nitride HEMT device including a substrate, a nucleation layer, a graded buffer layer and a channel layer which are sequentially stacked from bottom to top.

The source electrode and the drain electrode are both located on the channel layer and located on both sides of the device respectively.

An insertion layer, a barrier layer and a P-GaN layer are sequentially stacked on the channel layer from bottom to top, and the insertion layer is located between the source electrode and the drain electrode.

The first insulating dielectric layer is located on the barrier layer and the P-GaN layer, and the second insulating dielectric layer is located on the first insulating dielectric layer.

A T-shaped groove is provided in the first insulating dielectric layer and the second insulating dielectric layer, a gate electrode is located in the T-shaped groove, and the bottom of the gate electrode is in contact with the P-GaN layer, A Schottky contact is formed, and the upper surface of the gate electrode is located above the first insulating dielectric layer.

The source electrode and the drain electrode respectively form ohmic contact with the barrier layer.

Wherein, the source electrode and the drain electrode are both deposited metal by electron beam evaporation process, and the ohmic contact positions on both sides of the source electrode and the drain electrode are interfaced with a low temperature supercritical fluid process before and after depositing the metal. .

In one embodiment of the present invention, the substrate is a silicon substrate, a sapphire substrate or a gallium nitride substrate.

In one embodiment of the present invention, the nucleation layer includes a first nucleation layer and a second nucleation layer.

Wherein, the first nucleation layer is located on the substrate, and the second nucleation layer is located on the first nucleation layer. Both the first nucleation layer and the second nucleation layer use AlN material.

In one embodiment of the present invention, the graded buffer layer includes three layers of AlGaN buffer layers arranged in layers.

Wherein, in the three-layer AlGaN buffer layer, the Al composition from bottom to top is 23%, 52% and 73% in sequence. The thickness of the three-layer AlGaN buffer layer from bottom to top is 200 nm, 300 nm and 700 nm in sequence.

In an embodiment of the present invention, the channel layer is a GaN channel layer, and the insertion layer is an AlN insertion layer. The barrier layer is an AlGaN barrier layer, and its Al composition is 20%.

In an embodiment of the present invention, the P-GaN layer is implanted with Mg+ ions into a GaN material to form a P-type GaN structure.

Wherein, the amount of doping concentration of Mg+ ions in the P-GaN layer is extremely large than 10 ⁹ cm ^-3 .

In an embodiment of the present invention, the first insulating dielectric layer is a HfO ₂ dielectric layer, and the second insulating dielectric layer is a SiO ₂ dielectric layer.

The present invention also provides a preparation method of a gallium nitride HEMT device, the method is applicable to the gallium nitride HEMT device described in any one of the above embodiments, including:

S1: preparing an epitaxial wafer on a substrate, including sequentially stacking a nucleation layer, a graded buffer layer, a channel layer, an insertion layer, a barrier layer and a P-GaN layer.

S2: Etch the P-GaN layer, and prepare a first insulating dielectric layer on the barrier layer and the P-GaN layer.

S3: Etch the first insulating dielectric layer to form a T-shaped groove, the gate groove is located on the P-GaN layer, and deposit metal in the T-shaped groove to form a gate electrode.

S4: preparing a second insulating medium layer on the first insulating medium layer.

S5: Etch the second insulating medium layer, the first insulating medium layer, the barrier layer and the insertion layer to form source-drain electrode contact regions.

S6: Use a low-temperature supercritical fluid to process the contact area of the source and drain electrodes before depositing the metal, and deposit the metal in the processed area to form the source electrode and the drain electrode.

S7: Perform secondary treatment on the source electrode and the drain electrode by using supercritical fluid technology, and finally perform rapid thermal annealing at 800°C.

In an embodiment of the present invention, the supercritical fluid is a carbon dioxide supercritical fluid or a nitrous oxide supercritical fluid.

Compared with the prior art, the beneficial effects of the present invention are:

The gallium nitride HEMT device and the manufacturing method thereof of the present invention use a low-temperature process of supercritical fluid for interface treatment. Supercritical fluid is a special phase of matter with high permeability of gas and high solubility of liquid. It is used to improve the quality of the interface layer of gallium nitride HEMT and make up for the defects of the interface layer. At the same time, the low-temperature annealing technology is used to improve the stability of the ohmic contact and the voltage withstand capability of the drain electrode, which provides an effective method for the preparation of high-performance gallium nitride HEMT devices.

The above description is only an overview of the technical solutions of the present invention, in order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand , the following specific preferred embodiments, and in conjunction with the accompanying drawings, are described in detail as follows.

Description of drawings

1 is a schematic structural diagram of an epitaxial wafer for preparing a gallium nitride HEMT device provided by an embodiment of the present invention;

2 is a schematic structural diagram of a gallium nitride HEMT device provided by an embodiment of the present invention;

3(a)-FIG. 3(f) are a flow chart of the preparation of an epitaxial wafer for preparing a gallium nitride HEMT device according to an embodiment of the present invention;

4(a)-FIG. 4(f) are flowcharts of the preparation of the gallium nitride HEMT device provided by the embodiment of the present invention.

Detailed ways

In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, a gallium nitride HEMT device and a preparation method thereof according to the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

The foregoing and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description of the specific implementation with the accompanying drawings. Through the description of the specific embodiments, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the accompanying drawings are only for reference and description, and are not used for the technical description of the present invention. program is restricted.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of an epitaxial wafer for preparing a gallium nitride HEMT device according to an embodiment of the present invention.

As shown in the figure, the epitaxial wafer for preparing a gallium nitride HEMT device in this embodiment includes: a substrate 1, a nucleation layer 2, a graded buffer layer 3, a channel layer 4, an insertion layer 5, and a barrier layer 6 and P-GaN layer 7.

The substrate 1 , the nucleation layer 2 , the graded buffer layer 3 , the channel layer 4 , the insertion layer 5 , the barrier layer 6 and the P-GaN layer 7 are sequentially stacked from bottom to top.

Optionally, the substrate 1 is a silicon substrate, a sapphire substrate or a gallium nitride substrate.

Specifically, the homoepitaxy of the substrate 1 reduces the thickness of defects and dislocations generated during the growth of the epitaxial layer.

In a specific embodiment, the nucleation layer 2 includes, the nucleation layer includes a first nucleation layer 201 and a second nucleation layer 202, the first nucleation layer 201 is located on the substrate 1, and the second nucleation layer 202 is located on the first nucleation layer 201. a nucleation layer 201 .

Specifically, the first nucleation layer 201 is used to obtain a high crystalline quality GaN epitaxial layer, and the second nucleation layer 202 is used to ensure the quality of the nucleation layer, effectively suppressing the buried charge layer, that is, suppressing impurities in the substrate from flowing into the buffer layer diffusion.

Preferably, both the first nucleation layer 201 and the second nucleation layer 202 are made of AlN material.

In a specific embodiment, the graded buffer layer 3 includes a first buffer layer 301, a second buffer layer 302 and a third buffer layer 303;

Among them, three AlGaN buffer layers are stacked and arranged from bottom to top.

It is worth noting that the purpose of this design is to uniformly grow the graded buffer layer 3, reduce the stress between layers, and isolate the surface of the substrate 1, so that the substrate 1 will not lead out parasitic leakage channels due to the adsorption of impurities .

In a specific embodiment, in the stacked three-layer AlGaN buffer layer, the Al composition from bottom to top is 23%, 52% and 73% in sequence.

The thicknesses of the three-layer AlGaN buffer layers are 200 nm, 300 nm and 700 nm from bottom to top.

In a specific embodiment, an insertion layer 5, a barrier layer 6 and a P-GaN layer 7 are sequentially stacked on the channel layer 4 from bottom to top.

Optionally, the channel layer 4 is a GaN channel layer.

Optionally, the insertion layer 5 is an AlN insertion layer.

It is worth noting that the AlN insertion layer is used to increase the effective conduction band level between the channel layer 4 and the barrier layer 6, which can generate a narrower and deeper quantum well, which can avoid the penetration of part of the barrier layer 6. The dimensional electron gas is scattered, which can also increase the channel electron density, thereby enhancing the channel electron mobility.

In a specific embodiment, the barrier layer 6 is an AlGaN barrier layer whose Al composition is 20%.

Specifically, the barrier layer 6 provides a heterojunction barrier, saturates the two-dimensional electron gas density, and has good mobility.

In a specific embodiment, the P-GaN layer 7 is implanted with Mg+ ions into a GaN material to form a P-type GaN structure.

Among them, the amount of doping concentration of Mg+ ions in the P-GaN layer 7 is extremely large than 109 cm ^-3 .

Please refer to FIG. 2, which is a schematic structural diagram of a gallium nitride HEMT device provided by an embodiment of the present invention.

As shown in the figure, the gallium nitride HEMT device of this embodiment includes: a substrate 1, a nucleation layer 2, a first nucleation layer 201, a second nucleation layer 202, a graded buffer layer 3, and a first buffer layer 301 , the second buffer layer 302, the third buffer layer 303, the channel layer 4, the insertion layer 5, the barrier layer 6, the P-GaN layer 7, the source electrode 801, the drain electrode 802, the insulating medium layer 9, the first insulating medium layer 901 , the second insulating dielectric layer 902 and the gate electrode 10 .

As shown in the figure, the source electrode 801 and the drain electrode 802 are both located on the channel layer 4 and located on both sides of the device respectively.

Specifically, the insertion layer 5 is located between the source electrode 801 and the drain electrode 802 .

Optionally, Ti/Al metal is used for the source electrode 801 and the drain stage 802 .

In a specific embodiment, the source electrode 801 and the drain electrode 802 respectively form ohmic contact with the barrier layer.

The source electrode 801 and the drain electrode 802 are both deposited by electron beam evaporation process, and the ohmic contact positions on both sides of the source electrode 801 and the drain electrode 802 are treated by a low temperature supercritical fluid process before and after metal deposition.

In a specific embodiment, the insulating dielectric layer 9 is a double dielectric layer structure.

The first insulating dielectric layer 901 is located on the barrier layer 6 and the P-GaN layer 7 .

The second insulating medium layer 902 is located on the first insulating medium layer 901 .

A T-shaped groove is provided in the first insulating dielectric layer 901 and the second insulating dielectric layer 902, the gate electrode 10 is located in the T-shaped groove, and the bottom of the gate electrode 10 is in contact with the P-GaN layer 7 to form a Schottky contact , the upper surface of the gate electrode 10 is located above the first insulating dielectric layer 901 .

Optionally, the first insulating dielectric layer 901 is a HfO ₂ dielectric layer, HfO ₂ is a high-k material, and k is a dielectric constant, which is used to increase the capacitance of the gate electrode oxide layer.

Optionally, the second insulating dielectric layer 902 is a SiO ₂ dielectric layer for passivation.

In a specific embodiment, the gate electrode 10 is a T-type gate.

Embodiment 2

This embodiment provides a method for preparing an epitaxial wafer of a gallium nitride HEMT device, which is used to prepare the epitaxial wafer of the gallium nitride HEMT device described in the first embodiment.

Referring to FIG. 3, FIG. 3a-FIG. 3f are a flow chart of the preparation of an epitaxial wafer for preparing a gallium nitride HEMT device according to an embodiment of the present invention.

As shown in the figure, the preparation method of the epitaxial wafer of the gallium nitride HEMT device includes,

S1: select the substrate;

S2: prepare and deposit a nucleation layer, a graded buffer layer, a channel layer, an insertion layer and a barrier layer in sequence on the substrate;

S3: depositing GaN over the barrier layer, and implanting Mg ⁺ ions to form a P-type GaN layer to complete the preparation of the epitaxial wafer.

Further, the preparation method of the epitaxial wafer of the gallium nitride HEMT device of the present embodiment will be specifically described. The method includes the following steps:

In step 1, a silicon substrate layer is selected, and a nucleation layer is deposited on the silicon substrate layer, as shown in FIG. 3(a).

Specifically, a silicon substrate is selected, placed in the equipment growth chamber, MOCVD technology is used, the first nucleation layer with a thickness of 20 nm is deposited at a temperature of 600 °C, and the temperature is further increased to 1000 °C and V/III is controlled. The value of the ratio is higher and a 120 nm second nucleation layer is grown.

In step 2, a graded AlxGa1 _{- xN} buffer layer is deposited, as shown in Figure 3(b).

Specifically, a graded buffer layer is deposited on the AlN nucleation layer by the MOCVD process. The aluminum source is trimethyl aluminum, the gallium source is trimethyl gallium, and the nitrogen source is NH3. The AlGaN graded buffer layers are divided into 23%, 52%, and 73% in turn.

Step 3, depositing a channel layer, as shown in Figure 3(c).

Specifically, continue to deposit the channel layer on the AlxGa1 _{- xN} graded buffer layer by MOCVD technology with a thickness of 800nm.

Step 4, depositing an AlN insertion layer, as shown in FIG. 3(d).

Specifically, continue to deposit an AlN insertion layer with a thickness of 1 nm on the GaN channel layer by MOCVD technology.

Step 5, depositing a barrier layer, as shown in FIG. 3(e).

Specifically, continue to deposit a barrier layer with a thickness of 22 nm on the insertion layer by MOCVD technology.

Step 6, depositing a P-GaN layer, as shown in Figure 3(f).

Specifically, MOCVD technology is used to deposit GaN over the barrier layer, and Mg ⁺ ion implantation is used to form a P-type GaN layer, the doping concentration is greater than 10 ⁹ cm ^-3 , and the thickness is 7 nm to complete the preparation of the epitaxial wafer.

This embodiment also provides a method for preparing a gallium nitride HEMT device, which is used to prepare the gallium nitride HEMT device described in the first embodiment. Please refer to FIG. 4 . FIGS. 4 a to 4 f are provided by the embodiment of the present invention. Fabrication flow chart of the GaN HEMT device.

In a specific embodiment, a method for preparing a gallium nitride HEMT device includes,

S1: An epitaxial wafer is prepared on the substrate.

S2: etching the P-GaN layer, and preparing a first insulating dielectric layer on the barrier layer and the P-GaN buffer layer.

S3: etching the first insulating dielectric layer to form a T-shaped groove, the gate groove is located on the P-GaN layer, and depositing metal in the T-shaped groove to form a gate electrode.

S4: preparing a second insulating medium layer on the first insulating medium layer.

S5: Etching the second insulating medium layer, the first insulating medium layer, the barrier layer and the insertion layer to form source-drain electrode contact regions.

S6: Use a low-temperature supercritical fluid to process the contact area of the source and drain electrodes before depositing the metal, and deposit the metal in the processed area to form the source electrode and the drain electrode.

S7: The source electrode and the drain electrode are subjected to secondary treatment using supercritical fluid technology, and finally, rapid thermal annealing at 800°C is performed.

In a specific embodiment, the supercritical fluid is a carbon dioxide supercritical fluid or a nitrous oxide supercritical fluid.

Specifically, by increasing the pressure, it is easier for nitrous oxide and carbon dioxide to enter the supercritical fluid SCF state near room temperature. The SCF state is a special phase of matter. It has high permeability, high solubility, and low surface tension comparable to gas. It has good plasticity. Therefore, nitrous oxide and carbon dioxide fluids are introduced into the interface to reduce traps. method will not cause new damage. It also improves the stability of the ohmic contact.

Further, the preparation method of the epitaxial wafer of the gallium nitride HEMT device of the present embodiment will be specifically described. The method includes the following steps:

In step 1, SiN is grown on the epitaxial wafer, as shown in Fig. 4(a).

Specifically, the epitaxial wafer was cleaned, and ultrasonic cleaning was repeated with a combination of acetone and isopropanol, followed by rinsing with deionized water and blowing dry with N ₂ .

SiN was deposited on the P-GaN layer by PECVD, with a thickness of 100 nm. The selected process conditions were: SiH ₄ 13.5 sccm, NH ₃ 10 sccm, N ₂ 1000 sccm, pressure 2200 mToor, plasma radio frequency power 67 W, temperature 350 ℃.

Step 2, etching the P-GaN layer, as shown in FIG. 4(b).

First, at the required etching position for photolithography, spin-coating photoresist AZ6112, parameters: 600r, 5s; Exposure using MA6 lithography machine, exposure time 1.9s, development time 42s, post-bake 110 ℃, 2min.

Next, RIE equipment is used to etch SiN, and the process conditions are: CHF ₃ 72sccm, SF ₆ 10sccm AR 10sccm, plasma radio frequency power 100W, and pressure 35mToor. The etching depth is 100nm.

Finally, ICP is used to etch P-GaN, and the selected process conditions are: BCl3 25sccm, He15sccm, plasma radio frequency power 55W, pressure 6mToor. The etching depth is 7nm.

Step 3, wet etching SiN, as shown in FIG. 4(c).

Specifically, a HF acid solution with a concentration of 40%-42% was selected, soaked for 180 s, rinsed repeatedly with deionized water for more than 5 times, and dried with N ₂ .

Step 4, growing a first insulating dielectric layer, as shown in FIG. 4(d).

Specifically, a HfO ₂ dielectric layer with a thickness of 200 nm is grown by magnetron sputtering technology, and the target material is a high-purity HfO ₂ hot-pressed ceramic. Oxygen purity 99.999%.

Step 5, gate electrode preparation, as shown in e in FIG. 4 .

First, the mesa isolation is performed, and the photolithography process is used to select the area of the etched mesa, and the exposure parameters are the same as the exposure parameters of step 2. Etching HfO ₂ with a depth of 200nm, the selected process conditions are: CHF ₃ 72sccm, SF ₆ 12sscm, AR 5sccm, pressure 20mToor, RF power 100W; and then etch GaN with a depth of 150nm, the selected process conditions are: Cl ₂ 10sccm, BCl ₃ 25sccm, RF power 300W, vertical power 100W, pressure 10mToor.

Next, acetone + isopropanol was washed for 5 min each, followed by acetone + isopropanol for 3 min, rinsed with deionized water, and then air-dried under N ₂ .

Thirdly, a photolithography process is used to select the gate deposition area, the exposure parameters are the same as those in step 2, the selected area is etched, and HfO ₂ is etched, the process parameters are the same as above, and the etching depth is 200 nm. Then clean, the operation is the same as the above cleaning operation steps

Finally, a photolithography process was used to select the contact area of the gate electrode, and the exposure parameters were the same as those of step 2, and the stacked metal TiN/Ti/Al/TiN was grown by magnetron sputtering technology with a thickness of 100/20/250/300nm. Then peel off with acetone until the metal falls off, heat with a water bath of positive adhesive stripping solution at 75 °C for 10 min, then wash with acetone + isopropyl alcohol for 5 min each, then wash with acetone + isopropyl alcohol for 3 min, rinse with deionized water, and then dry with N ₂ .

Step 6, growing an insulating dielectric layer, as shown in FIG. 4(f).

Specifically, a SiO ₂ dielectric layer with a thickness of 200 nm is grown, and the process conditions are: N ₂ O 710 sccm, N ₂ 180 scm, SiH _{4 4} sccm, pressure 2000 mToor, radio frequency power 21 W, and temperature 350 °C.

Step 7, preparation of source electrode and drain electrode, to complete the preparation of the device, as shown in FIG. 2 .

Specifically, the source-drain electrode contact area is selected by a photolithography process, the exposure parameters are the same as those in step 2, the selected area is etched, SiO ₂ is etched, and the etching depth is 200 nm, and the selected process is the same as the etching process in step 5. Etch HfO ₂ , the etching depth is 200nm, and the selected process is the same as the etching process in step 5. Wash with acetone + isopropanol for 5 min each, then with acetone + isopropanol for 3 min, rinse with deionized water, and then blow dry under N ₂ .

Metal Ti/Al was deposited by electron beam evaporation technology with a thickness of 40/200 nm. Then peel off with acetone until the metal falls off, heat with a water bath of positive adhesive stripping solution at 75 °C for 10 min, then wash with acetone + isopropyl alcohol for 5 min each, then wash with acetone + isopropyl alcohol for 3 min, rinse with deionized water, and then dry with N ₂ .

It should be noted that the ohmic contact is treated with a low-temperature supercritical carbon dioxide or supercritical nitrous oxide fluid low-temperature treatment technology before the metal is deposited, and the same method is used for secondary treatment after the metal is deposited. The purpose of annealing is to repair the surface morphology, improve the quality of the source-drain interface layer, and improve the voltage withstand capability of the drain.

The gallium nitride HEMT device and the manufacturing method thereof according to the embodiments of the present invention use a low-temperature process of supercritical fluid for interface treatment. Supercritical fluid is a special phase of matter with high permeability of gas and high solubility of liquid. It is used to improve the quality of the interface layer of gallium nitride HEMT and make up for the defects of the interface layer. At the same time, the low-temperature annealing technology is used to improve the stability of the ohmic contact and the voltage withstand capability of the drain electrode, which provides an effective method for the preparation of high-performance gallium nitride HEMT devices.

It should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any relationship between these entities or operations. any such actual relationship or sequence exists. Moreover, the terms "comprising", "comprising" or any other variation are intended to encompass a non-exclusive inclusion such that an article or device comprising a list of elements includes not only those elements, but also other elements not expressly listed. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device that includes the element. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "up", "bottom", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying The device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (9)

1. A gallium nitride HEMT device, comprising,

the substrate, the nucleating layer, the gradual buffer layer and the channel layer are sequentially stacked from bottom to top;

the source electrode and the drain electrode are both positioned on the channel layer and are respectively positioned on two sides of the device;

an insertion layer, a barrier layer and a P-GaN layer are sequentially stacked on the channel layer from bottom to top, and the insertion layer is positioned between the source electrode and the drain electrode;

the first insulating medium layer is positioned on the barrier layer and the P-GaN layer;

the second insulating medium layer is positioned on the first insulating medium layer;

t-shaped grooves are formed in the first insulating medium layer and the second insulating medium layer, a gate electrode is located in the T-shaped grooves, the bottom of the gate electrode is in contact with the P-GaN layer to form Schottky contact, and the upper surface of the gate electrode is located above the first insulating medium layer;

the source electrode and the drain electrode form ohmic contact with the barrier layer respectively;

and carrying out interface treatment on ohmic contact positions at two sides of the source electrode and the drain electrode by using a low-temperature supercritical fluid process before and after the metal deposition.

2. The gallium nitride HEMT device of claim 1, wherein said substrate is a silicon substrate, a sapphire substrate or a gallium nitride substrate.

3. The gallium nitride HEMT device according to claim 1, wherein the nucleation layer comprises a first nucleation layer and a second nucleation layer;

wherein the first nucleation layer is located on the substrate and the second nucleation layer is located on the first nucleation layer;

the first nucleation layer and the second nucleation layer are made of AlN materials.

4. The gallium nitride HEMT device according to claim 1,

the gradient buffer layer comprises three layers of AlGaN buffer layers which are arranged in a laminated manner;

wherein, in the three AlGaN buffer layers, the Al components are 23%, 52% and 73% from bottom to top in sequence;

the three AlGaN buffer layers are 200nm, 300nm and 700nm in thickness from bottom to top in sequence.

5. The gallium nitride HEMT device according to claim 1,

the channel layer is a GaN channel layer, and the insertion layer is an AlN insertion layer;

the barrier layer is an AlGaN barrier layer, and the Al component of the barrier layer is 20%.

6. The gallium nitride HEMT device according to claim 1, wherein the P-GaN layer adopts Mg + ion implantation GaN material to form a P-type GaN structure;

wherein, in the P-GaN layerThe doping concentration and quantity of Mg + ions are greatly more than 10 ⁹ cm ^-3 。

7. The gallium nitride HEMT device of claim 1, wherein the first insulating dielectric layer is HfO ₂ A dielectric layer, the second insulating dielectric layer is SiO ₂ A dielectric layer.

8. A method for manufacturing a gallium nitride HEMT device, which is suitable for the gallium nitride HEMT device of any one of the above claims 1-7, comprising,

s1: preparing an epitaxial wafer on a substrate, wherein the epitaxial wafer comprises a nucleating layer, a gradual buffer layer, a channel layer, an insertion layer, a barrier layer and a P-GaN layer which are sequentially laminated;

s2: etching the P-GaN layer, and preparing a first insulating medium layer on the barrier layer and the P-GaN layer;

s3: etching the first insulating medium layer to form a T-shaped groove, wherein the grid electrode groove is positioned on the P-GaN layer, and metal is deposited in the T-shaped groove to form a grid electrode;

s4: preparing a second insulating medium layer on the first insulating medium layer;

s5: etching the second insulating medium layer, the first insulating medium layer, the barrier layer and the insertion layer to form a source-drain electrode contact region;

s6: processing a source-drain electrode contact area by using a low-temperature supercritical fluid before depositing metal, and depositing metal in the processed area to form a source electrode and a drain electrode;

s7: and carrying out secondary treatment on the source electrode and the drain electrode by adopting a supercritical fluid technology, and finally carrying out rapid thermal annealing at 800 ℃.

9. The method for manufacturing a gallium nitride HEMT device according to claim 8, wherein the supercritical fluid is a carbon dioxide supercritical fluid or a nitrous oxide supercritical fluid.

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