CN115188821A - Gallium nitride HEMT device and preparation method thereof - Google Patents

Gallium nitride HEMT device and preparation method thereof Download PDF

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Publication number
CN115188821A
CN115188821A CN202210821111.3A CN202210821111A CN115188821A CN 115188821 A CN115188821 A CN 115188821A CN 202210821111 A CN202210821111 A CN 202210821111A CN 115188821 A CN115188821 A CN 115188821A
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layer
gallium nitride
gan
insulating medium
drain electrode
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江希
姜涛
袁嵩
张世杰
严兆恒
何艳静
弓小武
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Jiangsu Zhuoyuan Semiconductor Co ltd
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Power Engineering (AREA)
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Abstract

The invention relates to a gallium nitride HEMT device and a preparation method thereof. The source electrode and the drain electrode are both positioned on the channel layer, an insertion layer, a barrier layer and a P-GaN layer are sequentially stacked on the channel layer from bottom to top, the insertion layer is positioned between the source electrode and the drain electrode, the first insulating medium layer is positioned on the barrier layer and the P-GaN layer, and the second insulating medium layer is positioned on the first insulating medium layer. The source electrode and the drain electrode are in ohmic contact with the barrier layer, respectively. The source electrode and the drain electrode are subjected to interface treatment by using a low-temperature supercritical fluid process before and after metal deposition. The invention adopts the low-temperature process of interface treatment by the supercritical fluid, and is used for improving the quality of the interface layer of the gallium nitride HEMT and making up the defects of the interface layer. Meanwhile, the low-temperature annealing technology is used, so that the stability of ohmic contact is improved, the voltage endurance capability of a drain electrode is improved, and an effective method is provided for preparing a high-performance gallium nitride HEMT device.

Description

Gallium nitride HEMT device and preparation method thereof
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a gallium nitride HEMT device and a preparation method thereof.
Background
The gallium nitride semiconductor material has high forbidden band width, high breakdown field strength, high electron mobility, high voltage resistance and heat resistance, and the HEMT device made of the gallium nitride semiconductor material is very suitable for being applied to the fields of high-power electronics and microwave radio frequency due to excellent switching characteristics and voltage resistance.
For a power device, improving the interface layer defect and improving the stability of ohmic contact are key nodes of the gallium nitride device process flow, the size of ohmic contact resistance has direct influence on the performance of various devices, and the larger source and drain contact resistance can cause the degradation of the output power, the gain and the power additional efficiency of the device; the extra loss also raises the channel temperature of the device, affecting the stability of the device.
After the conventional metal deposition process of the source electrode and the drain electrode, high-temperature annealing is often needed to eliminate the interface layer damage caused by heat radiation, however, the high-temperature annealing also causes decomposition and reoxidation of the electrode material, and the reliability of the dielectric layer and the voltage withstanding capability of the source electrode and the drain electrode are reduced.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a gallium nitride HEMT device and a preparation method thereof.
The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a gallium nitride HEMT device which comprises a substrate, a nucleating layer, a gradual buffer layer and a channel layer which are sequentially stacked from bottom to top.
And the source electrode and the drain electrode are both positioned on the channel layer and are respectively positioned on two sides of the device.
An insertion layer, a barrier layer and a P-GaN layer are sequentially stacked on the channel layer from bottom to top, and the insertion layer is located between the source electrode and the drain electrode.
And the second insulating medium layer is positioned on the first insulating medium layer.
T-shaped grooves are formed in the first insulating medium layer and the second insulating medium layer, the gate electrode is located in the T-shaped grooves, the bottom of the gate electrode is in contact with the P-GaN layer to form Schottky contact, and the upper surface of the gate electrode is located above the first insulating medium layer.
The source electrode and the drain electrode form ohmic contacts with the barrier layers, respectively.
And carrying out interface treatment on ohmic contact positions on two sides of the source electrode and the drain electrode by using a low-temperature supercritical fluid process before and after the metal deposition.
In one embodiment of the invention, the substrate is a silicon substrate, a sapphire substrate, or a gallium nitride substrate.
In one embodiment of the invention, the nucleation layers comprise a first nucleation layer and a second nucleation layer.
Wherein the first nucleation layer is located on the substrate and the second nucleation layer is located on the first nucleation layer. The first nucleation layer and the second nucleation layer are made of AlN materials.
In one embodiment of the present invention, the graded buffer layer includes three AlGaN buffer layers arranged in a stack.
In the three AlGaN buffer layers, the Al components are 23%, 52% and 73% from bottom to top in sequence. The three AlGaN buffer layers are 200nm, 300nm and 700nm in thickness from bottom to top in sequence.
In one embodiment of the present invention, wherein the channel layer is a GaN channel layer, the insertion layer is an AlN insertion layer. The barrier layer is an AlGaN barrier layer, and the Al component of the barrier layer is 20%.
In one embodiment of the invention, the P-GaN layer is formed by implanting Mg + ions into a GaN material to form a P-type GaN structure.
Wherein the doping concentration and quantity of Mg + ions in the P-GaN layer are greatly more than 10 9 cm -3 。
In one embodiment of the present invention, the first insulating dielectric layer is HfO 2 A dielectric layer, the second insulating dielectric layer is SiO 2 A dielectric layer.
The invention also provides a method for preparing the gallium nitride HEMT device, which is suitable for the gallium nitride HEMT device of any one of the embodiments, and comprises the following steps,
s1: and preparing an epitaxial wafer on the substrate, wherein the epitaxial wafer comprises a nucleating layer, a gradual buffer layer, a channel layer, an insertion layer, a barrier layer and a P-GaN layer which are sequentially laminated.
S2: and etching the P-GaN layer, and preparing a first insulating medium layer on the barrier layer and the P-GaN layer.
S3: and etching the first insulating medium layer to form a T-shaped groove, wherein the grid groove is positioned on the P-GaN layer, and depositing metal in the T-shaped groove to form a grid electrode.
S4: and preparing a second insulating medium layer on the first insulating medium layer.
S5: and etching the second insulating medium layer, the first insulating medium layer, the barrier layer and the insertion layer to form a source-drain electrode contact region.
S6: and processing the source and drain electrode contact region by using a low-temperature supercritical fluid before depositing metal, and depositing metal in the processed region to form a source electrode and a drain electrode.
S7: and carrying out secondary treatment on the source electrode and the drain electrode by adopting a supercritical fluid technology, and finally carrying out rapid thermal annealing at 800 ℃.
In one embodiment of the invention, the supercritical fluid is a carbon dioxide supercritical fluid or a nitrous oxide supercritical fluid.
Compared with the prior art, the invention has the beneficial effects that:
the gallium nitride HEMT device and the manufacturing method thereof adopt a low-temperature process of interface treatment by supercritical fluid. The supercritical fluid is a special phase of a substance, has high permeability of gas and high solubility of liquid, and is used for improving the quality of an interface layer of the gallium nitride HEMT and making up the defects of the interface layer. Meanwhile, the low-temperature annealing technology is used, so that the stability of ohmic contact is improved, the voltage endurance capability of the drain electrode is improved, and an effective method is provided for preparing a high-performance gallium nitride HEMT device.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are specifically described below with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic structural diagram of an epitaxial wafer for preparing a gallium nitride HEMT device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a gallium nitride HEMT device according to an embodiment of the present invention;
fig. 3 (a) -3 (f) are flow charts of the preparation of epitaxial wafers for preparing gallium nitride HEMT devices according to embodiments of the present invention;
fig. 4 (a) -4 (f) are flow charts of the preparation of the gallium nitride HEMT device according to the embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, a gallium nitride HEMT device and a method for manufacturing the same according to the present invention will be described in detail below with reference to the accompanying drawings and the detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. While the present invention has been described in connection with the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of an epitaxial wafer for fabricating a gallium nitride HEMT device according to an embodiment of the present invention.
As shown in the figure, the epitaxial wafer for preparing the gallium nitride HEMT device of the embodiment includes: substrate 1, nucleation layer 2, graded buffer layer 3, channel layer 4, insertion layer 5, barrier layer 6, and P-GaN layer 7.
The substrate 1, the nucleation layer 2, the graded buffer layer 3, the channel layer 4, the insertion layer 5, the barrier layer 6 and the P-GaN layer 7 are sequentially stacked from bottom to top.
Alternatively, the substrate 1 is a silicon substrate, a sapphire substrate, or a gallium nitride substrate.
Specifically, the substrate 1 homoepitaxy reduces the thickness of defects and dislocations generated when the epitaxial layer is grown.
In a particular embodiment, the nucleation layer 2 includes a first nucleation layer 201 and a second nucleation layer 202, the first nucleation layer 201 being located on the substrate 1, the second nucleation layer 202 being located on the first nucleation layer 201.
Specifically, the first nucleation layer 201 is used to obtain a GaN epitaxial layer with high crystalline quality, and the second nucleation layer 202 is used to ensure the quality of the nucleation layer, thereby effectively suppressing the buried charge layer, i.e., suppressing the diffusion of impurities in the substrate toward the buffer layer.
Preferably, alN material is used for both the first nucleation layer 201 and the second nucleation layer 202.
In a particular embodiment, the graded buffer layer 3 includes a first buffer layer 301, a second buffer layer 302, and a third buffer layer 303;
wherein, three AlGaN buffer layers are stacked and arranged from bottom to top.
It should be noted that the purpose of this design is to uniformly grow the graded buffer layer 3, reduce the stress between layers, and isolate the surface of the substrate 1, so that the substrate 1 will not lead out the parasitic leakage channel due to the adsorption of impurities.
In a specific embodiment, in the three AlGaN buffer layers arranged in a stacked manner, the Al composition is 23%, 52%, and 73% in this order from the bottom to the top.
The three AlGaN buffer layers are 200nm, 300nm and 700nm in thickness from bottom to top.
In a specific embodiment, the channel layer 4 is sequentially laminated with an insertion layer 5, a barrier layer 6 and a P-GaN layer 7 from bottom to top,
optionally, the channel layer 4 is a GaN channel layer.
Optionally, the insertion layer 5 is an AlN insertion layer.
It is worth noting that the AlN insert layer is used for improving the effective conduction band step between the channel layer 4 and the barrier layer 6, a narrower and deeper quantum well can be generated, not only can the two-dimensional electron gas penetrating into the barrier layer 6 be prevented from being scattered, but also the channel electron density can be improved, and therefore the channel electron mobility is enhanced
In a specific embodiment, barrier layer 6 is an AlGaN barrier layer with an Al composition of 20%.
Specifically, the barrier layer 6, which provides a heterojunction barrier, saturates the two-dimensional electron gas density and has good mobility.
In a specific embodiment, the P-GaN layer 7 is formed by implanting Mg + ions into a GaN material to form a P-type GaN structure.
Wherein the doping concentration quantity of Mg + ions in the P-GaN layer 7 is more than 109cm -3 。
Referring to fig. 2, fig. 2 is a schematic structural diagram of a gallium nitride HEMT device according to an embodiment of the present invention.
As shown in the figure, the gallium nitride HEMT device of the present embodiment includes: the semiconductor device comprises a substrate 1, a nucleation layer 2, a first nucleation layer 201, a second nucleation layer 202, a graded buffer layer 3, a first buffer layer 301, a second buffer layer 302, a third buffer layer 303, a channel layer 4, an insertion layer 5, a barrier layer 6, a P-GaN layer 7, a source electrode 801, a drain electrode 802, an insulating medium layer 9, a first insulating medium layer 901, a second insulating medium layer 902 and a gate electrode 10.
As shown, a source electrode 801 and a drain electrode 802 are both located on the channel layer 4 and on both sides of the device, respectively.
Specifically, the insertion layer 5 is located between the source electrode 801 and the drain electrode 802.
Alternatively, ti/Al metal is used for the source electrode 801 and the drain electrode 802.
In a specific embodiment, the source electrode 801 and the drain electrode 802 form ohmic contacts with the barrier layers, respectively.
The source electrode 801 and the drain electrode 802 are both deposited with metal by an electron beam evaporation process, and ohmic contact positions on both sides of the source electrode 801 and the drain electrode 802 are subjected to interface treatment by a low-temperature supercritical fluid process before and after the metal deposition.
In a specific embodiment, the insulating dielectric layer 9 is a dual dielectric layer structure.
The first insulating medium layer 901 is located on the barrier layer 6 and the P-GaN layer 7.
And a second insulating dielectric layer 902 on the first insulating dielectric layer 901.
T-shaped grooves are formed in the first insulating medium layer 901 and the second insulating medium layer 902, the gate electrode 10 is located in the T-shaped grooves, the bottom of the gate electrode 10 is in contact with the P-GaN layer 7 to form Schottky contact, and the upper surface of the gate electrode 10 is located above the first insulating medium layer 901.
Optionally, the first insulating dielectric layer 901 is HfO 2 Dielectric layer, hfO 2 Is a high-k material, k is a dielectric constant, and is used for improving the capacitance of a gate electrode oxide layer.
Optionally, the second insulating dielectric layer 902 is SiO 2 And the dielectric layer plays a passivation role.
In a particular embodiment, the gate electrode 10 is a T-gate.
Example two
The embodiment provides a method for preparing an epitaxial wafer of a gallium nitride HEMT device, which is used for preparing the epitaxial wafer of the gallium nitride HEMT device in the embodiment.
Referring to fig. 3, fig. 3 a-3 f are flow charts of epitaxial wafer fabrication for fabricating gallium nitride HEMT devices according to embodiments of the present invention.
As shown in the figure, the preparation method of the epitaxial wafer of the gallium nitride HEMT device comprises the following steps,
s1: selecting a substrate;
s2: sequentially laminating and preparing a deposition nucleating layer, a gradient buffer layer, a channel layer, an insertion layer and a barrier layer on a substrate;
s3: depositing GaN over the barrier layer and using Mg + And (5) forming a P-type GaN layer by ion implantation to finish the preparation of the epitaxial wafer.
Further, a method for manufacturing an epitaxial wafer of the gallium nitride HEMT device of the present embodiment is specifically described. The method comprises the following steps:
step one, selecting a silicon substrate layer, and depositing a nucleation layer on the silicon substrate layer, as shown in fig. 3 (a).
Specifically, a silicon substrate is selected and placed in an equipment growth chamber, an MOCVD technology is adopted, a first nucleation layer with the thickness of 20nm is deposited at the set temperature of 600 ℃, then the temperature is continuously raised to 1000 ℃, the value of the V/III ratio is controlled to be high, and a second nucleation layer with the thickness of 120nm is grown.
Step two, depositing gradient Al x Ga 1-x An N buffer layer as shown in FIG. 3 (b).
Specifically, a gradual buffer layer is deposited on the AlN nucleating layer through an MOCVD process, an aluminum source is trimethylaluminum, a gallium source is trimethylgallium, a nitrogen source is NH3, alGaN gradual buffer layers with the thicknesses of 210nm, 300nm and 700nm are sequentially grown, and Al components are 23%, 52% and 73% respectively.
Step three, depositing a channel layer, as shown in fig. 3 (c).
Specifically, the channel layer is deposited on the Al by the MOCVD technique x Ga 1-x And the thickness of the N gradual change buffer layer is 800nm.
Step four, an AlN insertion layer is deposited, as shown in fig. 3 (d).
Specifically, deposition of an AlN insertion layer with a thickness of 1nm on the GaN channel layer was continued by the MOCVD technique.
Step five, depositing a barrier layer, as shown in fig. 3 (e).
In particular, the deposition of a barrier layer over the intervening layer was continued by MOCVD techniques to a thickness of 22 nm.
And step six, depositing a P-GaN layer as shown in figure 3 (f).
Specifically, gaN is deposited over the barrier layer using MOCVD techniques, and Mg is used + Ion implantation is carried out to form a P type GaN layer, and the doping concentration order of magnitude is more than 10 9 cm -3 And the thickness is 7nm, and the preparation of the epitaxial wafer is finished.
Fig. 4 is a schematic view showing a process for fabricating a gallium nitride HEMT device according to an embodiment of the present invention, and fig. 4a to 4f are flowcharts of the process for fabricating the gallium nitride HEMT device according to the embodiment of the present invention.
In a specific embodiment, the preparation method of the gallium nitride HEMT device comprises the steps of,
s1: and preparing an epitaxial wafer on the substrate.
S2: and etching the P-GaN layer, and preparing a first insulating medium layer on the barrier layer and the P-GaN buffer layer.
S3: and etching the first insulating medium layer to form a T-shaped groove, wherein the grid groove is positioned on the P-GaN layer, and depositing metal in the T-shaped groove to form a grid electrode.
S4: and preparing a second insulating medium layer on the first insulating medium layer.
S5: and etching the second insulating medium layer, the first insulating medium layer, the barrier layer and the insertion layer to form a source-drain electrode contact region.
S6: and (3) processing the source and drain electrode contact region by using a low-temperature supercritical fluid before metal deposition, and depositing metal in the processed region to form a source electrode and a drain electrode.
S7: and (3) performing secondary treatment on the source electrode and the drain electrode by adopting a supercritical fluid technology, and finally performing rapid thermal annealing at 800 ℃.
In a particular embodiment, the supercritical fluid is a carbon dioxide supercritical fluid or a nitrous oxide supercritical fluid.
In particular, by increasing the pressure, nitrous oxide and carbon dioxide are more readily introduced into the supercritical fluid SCF state at near room temperature. The SCF state is a distinct phase of matter that is as plastic as a high permeability, high solubility and low surface tension compared to gases, so that introduction of nitrous oxide and carbon dioxide fluids into the interface to reduce traps does not cause new damage. But also improves the stability of ohmic contact.
Further, a method for manufacturing an epitaxial wafer of the gallium nitride HEMT device of the present embodiment is specifically described. The method comprises the following steps:
step 1, siN is grown on the epitaxial wafer, as shown in fig. 4 (a).
Specifically, the epitaxial wafer is cleaned, repeatedly ultrasonically cleaned with a combination of acetone and isopropyl alcohol, followed by rinsing with deionized water, N 2 And (5) drying.
Selecting PECVD to deposit SiN with the thickness of 100nm on the P-GaN layer, wherein the selected technological conditions are as follows: siH 4 13.5sccm、NH 3 10sccm、N 2 1000sccm, a pressure of 2200mToor, a plasma RF power of 67W, and a temperature of 350 ℃.
And step 2, etching the P-GaN layer as shown in FIG. 4 (b).
Firstly, photoetching a required etching position, spin-coating a photoresist AZ6112, wherein the parameters are as follows: 600r,5s;4000r,30s baking glue at 100 deg.C for 2min. And (3) exposing by using an MA6 photoetching machine for 1.9s, developing for 42s, post-baking at 110 ℃ for 2min.
Secondly, etching SiN by RIE equipment, wherein the process conditions are as follows: CHF 3 72sccm、SF 6 10sccm AR 10sccm, plasma RF power 100W, and pressure 35mToor. The etching depth is 100nm.
And finally, etching P-GaN by using ICP (inductively coupled plasma), wherein the selected process conditions are as follows: BCl3 25sccm, he15sccm, plasma radio frequency power 55W, pressure 6mToor. The etching depth is 7nm.
Step 3, wet etching the SiN, as shown in fig. 4 (c).
Specifically, HF acid solution with concentration of 40-42% is selected, soaked for 180s, and repeatedly washed for more than 5 times by deionized water, wherein N is 2 And (5) drying.
Step 4, growing a first insulating dielectric layer, as shown in fig. 4 (d).
Specifically, hfO with the thickness of 200nm is grown by utilizing the magnetron sputtering technology 2 A dielectric layer and a target material of high-purity HfO 2 And (5) hot-pressing the ceramic. The purity of oxygen is 99.999%.
Step 5, a gate electrode is prepared, as shown in fig. 4 e.
Firstly, mesa isolation is carried out, the area of the etched mesa is selected by adopting a photoetching process, and the exposure parameters are the same as those in the step 2. Etching HfO 2 The depth is 200nm, and the selected process conditions are as follows: CHF 3 72sccm、SF 6 12sscm, AR 5sccm, pressure of 20mToor and radio frequency power of 100W; and etching the GaN with the depth of 150nm, wherein the selected process conditions are as follows: cl 2 10sccm、BCl 3 25sccm, RF power 300W, vertical power 100W, and pressure 10mToor.
Secondly, cleaning with acetone and isopropanol for 5min respectively, cleaning with acetone and isopropanol for 3min, washing with deionized water, and then cleaning with N 2 And (5) drying.
Thirdly, selecting a grid deposition area by adopting a photoetching process, etching the selected area by using the exposure parameters in the step 2, and etching HfO 2 The process parameters are the same as above, and the etching depth is 200nm. Then cleaning, the operation is the same as the above cleaning operation step
And finally, selecting a gate electrode contact area by adopting a photoetching process, and growing laminated metal TiN/Ti/Al/TiN with the thickness of 100/20/250/300nm by using a magnetron sputtering technology with the exposure parameters of the step 2. Peeling with acetone until metal falls off, heating with normal glue stripping solution in water bath at 75 deg.C for 10min, cleaning with acetone and isopropanol for 5min, cleaning with acetone and isopropanol for 3min, washing with deionized water, and then N 2 And (5) drying.
And 6, growing an insulating medium layer as shown in fig. 4 (f).
Specifically, siO was grown to a thickness of 200nm 2 The process conditions of the dielectric layer are as follows: n is a radical of 2 O 710sccm、N 2 180scm、SiH 4 4sccm, a pressure of 2000mToor, a radio frequency power of 21W, and a temperature of 350 ℃.
And 7, preparing a source electrode and a drain electrode to finish the preparation of the device, as shown in figure 2.
Specifically, a photoetching process is adopted to select a source-drain electrode contact area, the exposure parameters are the same as those in the step 2, the selected area is etched, and SiO is etched 2 Etching depth of 200nm, the selected process is the same as the etching process of step 5, and HfO is etched 2 And etching depth of 200nm, and selecting the same etching process as the step 5. Acetone + isopropanol washes 5 eachmin, cleaning with acetone and isopropanol for 3min, rinsing with deionized water, and then N 2 And (5) drying.
The Ti/Al metal is deposited by electron beam evaporation technology, and the thickness is 40/200nm. Peeling with acetone until metal falls off, heating with normal glue stripping solution in water bath at 75 deg.C for 10min, cleaning with acetone and isopropanol for 5min, cleaning with acetone and isopropanol for 3min, washing with deionized water, and then N 2 And (5) drying.
It should be noted that, a low-temperature treatment technology of low-temperature supercritical carbon dioxide or supercritical nitrous oxide fluid is used for treating ohmic contact before metal deposition, the same method is adopted for secondary treatment after metal deposition, and then an annealing process of rapid thermal annealing at 800 ℃ is used for annealing, so that the surface morphology is repaired, the quality of a source-drain interface layer is improved, and the pressure resistance of a drain electrode is improved.
The gallium nitride HEMT device and the manufacturing method thereof adopt a low-temperature process of performing interface treatment by using a supercritical fluid. The supercritical fluid is a special phase of a substance, has high permeability of gas and high solubility of liquid, and is used for improving the quality of an interface layer of the gallium nitride HEMT and making up the defects of the interface layer. Meanwhile, the low-temperature annealing technology is used, so that the stability of ohmic contact is improved, the voltage endurance capability of a drain electrode is improved, and an effective method is provided for preparing a high-performance gallium nitride HEMT device.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one of 8230, and" comprising 8230does not exclude the presence of additional like elements in an article or device comprising the element. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The directional or positional relationships indicated by "upper", "lower", "left", "right", etc., are based on the directional or positional relationships shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (9)

1. A gallium nitride HEMT device, comprising,
the substrate, the nucleating layer, the gradual buffer layer and the channel layer are sequentially stacked from bottom to top;
the source electrode and the drain electrode are both positioned on the channel layer and are respectively positioned on two sides of the device;
an insertion layer, a barrier layer and a P-GaN layer are sequentially stacked on the channel layer from bottom to top, and the insertion layer is positioned between the source electrode and the drain electrode;
the first insulating medium layer is positioned on the barrier layer and the P-GaN layer;
the second insulating medium layer is positioned on the first insulating medium layer;
t-shaped grooves are formed in the first insulating medium layer and the second insulating medium layer, a gate electrode is located in the T-shaped grooves, the bottom of the gate electrode is in contact with the P-GaN layer to form Schottky contact, and the upper surface of the gate electrode is located above the first insulating medium layer;
the source electrode and the drain electrode form ohmic contact with the barrier layer respectively;
and carrying out interface treatment on ohmic contact positions at two sides of the source electrode and the drain electrode by using a low-temperature supercritical fluid process before and after the metal deposition.
2. The gallium nitride HEMT device of claim 1, wherein said substrate is a silicon substrate, a sapphire substrate or a gallium nitride substrate.
3. The gallium nitride HEMT device according to claim 1, wherein the nucleation layer comprises a first nucleation layer and a second nucleation layer;
wherein the first nucleation layer is located on the substrate and the second nucleation layer is located on the first nucleation layer;
the first nucleation layer and the second nucleation layer are made of AlN materials.
4. The gallium nitride HEMT device according to claim 1,
the gradient buffer layer comprises three layers of AlGaN buffer layers which are arranged in a laminated manner;
wherein, in the three AlGaN buffer layers, the Al components are 23%, 52% and 73% from bottom to top in sequence;
the three AlGaN buffer layers are 200nm, 300nm and 700nm in thickness from bottom to top in sequence.
5. The gallium nitride HEMT device according to claim 1,
the channel layer is a GaN channel layer, and the insertion layer is an AlN insertion layer;
the barrier layer is an AlGaN barrier layer, and the Al component of the barrier layer is 20%.
6. The gallium nitride HEMT device according to claim 1, wherein the P-GaN layer adopts Mg + ion implantation GaN material to form a P-type GaN structure;
wherein, in the P-GaN layerThe doping concentration and quantity of Mg + ions are greatly more than 10 9 cm -3 。
7. The gallium nitride HEMT device of claim 1, wherein the first insulating dielectric layer is HfO 2 A dielectric layer, the second insulating dielectric layer is SiO 2 A dielectric layer.
8. A method for manufacturing a gallium nitride HEMT device, which is suitable for the gallium nitride HEMT device of any one of the above claims 1-7, comprising,
s1: preparing an epitaxial wafer on a substrate, wherein the epitaxial wafer comprises a nucleating layer, a gradual buffer layer, a channel layer, an insertion layer, a barrier layer and a P-GaN layer which are sequentially laminated;
s2: etching the P-GaN layer, and preparing a first insulating medium layer on the barrier layer and the P-GaN layer;
s3: etching the first insulating medium layer to form a T-shaped groove, wherein the grid electrode groove is positioned on the P-GaN layer, and metal is deposited in the T-shaped groove to form a grid electrode;
s4: preparing a second insulating medium layer on the first insulating medium layer;
s5: etching the second insulating medium layer, the first insulating medium layer, the barrier layer and the insertion layer to form a source-drain electrode contact region;
s6: processing a source-drain electrode contact area by using a low-temperature supercritical fluid before depositing metal, and depositing metal in the processed area to form a source electrode and a drain electrode;
s7: and carrying out secondary treatment on the source electrode and the drain electrode by adopting a supercritical fluid technology, and finally carrying out rapid thermal annealing at 800 ℃.
9. The method for manufacturing a gallium nitride HEMT device according to claim 8, wherein the supercritical fluid is a carbon dioxide supercritical fluid or a nitrous oxide supercritical fluid.
CN202210821111.3A 2022-07-13 2022-07-13 Gallium nitride HEMT device and preparation method thereof Pending CN115188821A (en)

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