CN115188820A - P-channel metal oxide semiconductor field effect transistor based on InN/AlGaN/GaN heterojunction and preparation method - Google Patents
P-channel metal oxide semiconductor field effect transistor based on InN/AlGaN/GaN heterojunction and preparation method Download PDFInfo
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- 229910002704 AlGaN Inorganic materials 0.000 title claims abstract description 37
- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 11
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000004888 barrier function Effects 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 12
- 239000004047 hole gas Substances 0.000 claims abstract description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 51
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 45
- 230000008569 process Effects 0.000 claims description 42
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 20
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- 238000001035 drying Methods 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 238000005566 electron beam evaporation Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 10
- 238000001704 evaporation Methods 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 8
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- 229910052594 sapphire Inorganic materials 0.000 claims description 7
- 239000010980 sapphire Substances 0.000 claims description 7
- 239000011777 magnesium Substances 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052749 magnesium Inorganic materials 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 4
- 238000002791 soaking Methods 0.000 claims description 4
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 abstract description 5
- 229910002601 GaN Inorganic materials 0.000 description 41
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 238000013508 migration Methods 0.000 description 1
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- 238000007781 pre-processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention discloses a p-channel metal oxide semiconductor field effect transistor based on InN/AlGaN/GaN heterojunction and a preparation method thereof, mainly solving the problems of low hole mobility and low two-dimensional hole gas concentration of the existing p-channel MOSFET device. It includes from bottom to top: the GaN-based light-emitting diode comprises a substrate layer (1), a GaN buffer layer (2), an AlGaN barrier layer (3), a p-type layer (5) and SiO 2 A gate dielectric layer (6), a source electrode (7) and a drain electrode (8) are respectively arranged at the left end and the right end of the dielectric layer, a gate groove is etched in the middle, and a gate electrode (9) is arranged at the gate groove, the GaN-based power device is characterized in that an undoped InN channel layer (4) is additionally arranged between the AlGaN barrier layer and the p-type layer to improve the two-dimensional hole gas concentration and the hole mobility, the p-type layer is made of InN materials to improve the hole mobility, the working frequency and the output power of the device are improved, and the GaN-based power device can be used for GaN-based powerIntegrated circuits and complementary logic circuits.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) which can be used for manufacturing a GaN-based power integrated circuit and a complementary logic circuit.
Technical Field
Compared with the traditional silicon and gallium arsenide materials, the gallium nitride GaN material has the excellent characteristics of wide forbidden band, high electron drift velocity, high thermal conductivity, high breakdown electric field and the like, and can be used for manufacturing high-voltage, high-frequency and high-power electronic devices. With the development of the fields of new energy automobiles, 5G communication, aerospace and the like, gaN-based power devices and power modules have been widely applied. However, in the currently used GaN power module, the peripheral driving circuit and the logic unit are still made of conventional silicon materials. This approach can increase the size of the GaN power module and introduce parasitic inductance, greatly limiting the operating frequency and output power of the system. The ideal solution is to adopt the peripheral drive circuit and the logic unit made of GaN material to realize the monolithic integration of the GaN power device and the GaN complementary logic circuit. In recent years, complementary logic circuits based on GaN have been widely studied, but the current GaN complementary logic circuits have low operating frequency and output power, and cannot meet the requirements of power integration because p-channel MOSFETs constituting the circuits have low channel mobility, large on-resistance, and low carrier concentration, which severely limits the circuit performance.
The existing p-channel mosfet structure based on GaN/AlGaN/GaN heterojunction, as shown in fig. 1, comprises from bottom to top: the GaN-based light-emitting diode comprises a Si substrate layer, a GaN buffer layer, an AlGaN barrier layer, a p-type GaN layer and a gate dielectric layer, wherein a source electrode and a drain electrode are respectively arranged at the left end and the right end of the gate dielectric layer, a gate groove is etched in the middle of the gate dielectric layer, and a grid electrode is arranged at the position of the gate groove. The device has two main defects that firstly, because the GaN material is adopted as a p-type layer and a conductive channel, the mobility of a hole is extremely low, and the running speed of the device is seriously limited; and secondly, ionized impurity scattering and etching damage can reduce the concentration and the hole mobility of two-dimensional hole gas, so that the output power of the device is reduced.
Disclosure of Invention
The invention aims to provide a p-channel metal oxide semiconductor field effect transistor based on InN/AlGaN/GaN heterojunction and a preparation method thereof aiming at the defects of the prior art, so as to effectively improve the hole mobility and the two-dimensional hole gas concentration and improve the working frequency and the output power of a device.
The technical scheme for realizing the purpose of the invention is as follows:
1. a p-channel metal oxide semiconductor field effect transistor based on InN/AlGaN/GaN heterojunction comprises the following components from bottom to top: substrate layer, gaN buffer layer, alGaN barrier layer, p type layer, gate dielectric layer, both ends are equipped with source electrode and drain electrode respectively about this gate dielectric layer, and middle sculpture has the bars recess, and bars groove is equipped with grid, its characterized in that:
the p-type layer is made of InN materials so as to improve the hole mobility;
the gate dielectric layer is made of SiO 2 Materials to reduce gate leakage;
an undoped InN channel layer is additionally arranged between the AlGaN barrier layer and the p-type layer so as to improve the two-dimensional hole gas concentration and the hole mobility;
further, the substrate layer uses a Si substrate with a <111> crystal orientation or a c-plane sapphire substrate;
furthermore, the InN channel layer is 20-30nm thick; the thickness of the p-type InN layer is 60-70nm, and the doping concentration is 2 x 10 19 cm -3 ～4×10 19 cm -3 (ii) a The SiO 2 Gate dielectricA layer having a thickness of 5-10nm;
furthermore, the thickness of the GaN buffer layer is 4000-5000nm; the AlGaN barrier layer has the thickness of 20-30nm, and the Al component is 0.2-0.3; the thickness of the source electrode and the drain electrode is 25-40nm; the thickness of the grid electrode is 65-90nm.
2. A p-channel metal oxide semiconductor field effect transistor preparation method based on InN/AlGaN/GaN heterojunction is characterized by comprising the following steps:
1) Cleaning and drying the substrate;
2) Growing a GaN buffer layer with the thickness of 4000-5000nm on the dried substrate by adopting an MOCVD process;
3) Growing an AlGaN barrier layer with the thickness of 20-30nm on the GaN buffer layer by adopting an MOCVD process, wherein the adjustment range of the Al component is 0.2-0.3;
4) Growing an InN channel layer with the thickness of 20-30nm on the AlGaN barrier layer by adopting an MOCVD process;
5) Growing a p-type InN layer with the thickness of 60-70nm on the InN channel layer by adopting an MOCVD process, wherein the doping element is Mg, and the doping concentration is 2 multiplied by 10 19 cm -3 ～4×10 19 cm -3 ；
6) Etching a gate groove with the depth of 40-50nm in the center of the p-type InN layer by using a low-power plasma etching process;
7) Evaporating mixed metal of titanium, aluminum, nickel and gold on the left side and the right side of the p-type InN layer by using an electron beam evaporation technology, and depositing a source electrode and a drain electrode with the thickness of 25-40nm;
8) Growing SiO with the thickness of 5-10nm at the groove of the p-type InN layer by adopting the MOCVD process 2 A gate dielectric layer;
9) And (3) evaporating the mixed metal of titanium, aluminum, nickel and gold on the gate dielectric layer by using an electron beam evaporation technology, and depositing a gate with the thickness of 70-100nm to finish the manufacture of the device.
Compared with the prior art, the invention has the following advantages:
firstly, the InN material is adopted as the p-type layer and the channel layer, and the working frequency of the device can be improved due to the high hole mobility of the InN material.
Secondly, the invention adopts SiO 2 The material is used as a gate dielectric layer, so that the leakage of the gate can be reduced, and the reliability of the device is improved.
Thirdly, the undoped InN channel layer is inserted between the AlGaN barrier layer and the p-type layer, so that on one hand, the polarization electric field of the device can be enhanced, the two-dimensional hole gas concentration is improved, the output power of the device is improved, on the other hand, the influence of ionized impurity scattering and etching damage on the channel can be effectively weakened, the hole migration rate is accelerated, and the working speed of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional GaN/AlGaN/GaN heterojunction p-channel MOSFET structure;
FIG. 2 is a structural diagram of a p-channel metal oxide semiconductor field effect transistor based on InN/AlGaN/GaN heterojunction according to the present invention;
FIG. 3 is a schematic flow chart of a p-channel metal oxide semiconductor field effect transistor with the structure of FIG. 2 according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 2, the device structure of the present invention includes: the GaN-based light-emitting diode comprises a substrate 1, a GaN buffer layer 2, an AlGaN barrier layer 3, an InN channel layer 4, a p-type InN layer 5, a gate dielectric layer 6, a source electrode 7, a drain electrode 8 and a grid electrode 9. Wherein:
the substrate 1 is a Si substrate with a <111> crystal orientation or a c-plane sapphire substrate;
the GaN buffer layer 2 is positioned on the substrate 1, and the thickness of the GaN buffer layer is 4000-5000nm;
the AlGaN barrier layer 3 is positioned on the GaN buffer layer 2, the thickness of the AlGaN barrier layer is 20-30nm, and the adjustment range of Al components is 0.2-0.3;
the InN channel layer 4 is positioned on the AlGaN barrier layer 3, has the thickness of 20-30nm and is used for improving the concentration and the mobility of two-dimensional hole gas;
the p-type InN layer 5 is arranged on the InN channel layer 4, has a thickness of 60-70nm and a doping concentration of 2 × 10 19 cm -3 ～4×10 19 cm -3 (ii) a The middle of the p-type InN layer 5Etching gate groove with depth of 40-50nm, and depositing SiO 5-10nm thick on the groove 2 A gate dielectric layer 6; a grid electrode 9 is arranged on the grid dielectric layer, and the thickness of the grid electrode is 70-100nm;
the source electrode 7 and the drain electrode 8 are respectively positioned on the left side and the right side of the p-type InN layer 5, and the thickness of the source electrode and the drain electrode is 25-40nm.
Referring to fig. 3, three examples are given as follows for a method for fabricating a p-channel mosfet based on InN/AlGaN/GaN heterojunction.
Example 1A substrate was prepared<111>The thickness of the buffer layer of the crystal orientation Si is 4000nm, the thickness of the barrier layer is 20nm, the Al component is 0.2, the thickness of the channel layer is 20nm, the thickness of the p-type layer is 60nm, and the doping concentration is 2 multiplied by 10 19 cm -3 The thickness of the gate dielectric layer is 5nm, the thickness of the source electrode and the drain electrode is 25nm, and the thickness of the grid electrode is 70 nm.
Step one, carrying out cleaning and drying pretreatment on the Si substrate.
1.1 Placing the Si substrate 1 in an acetone solution for ultrasonic cleaning for 5min;
1.2 Soaking the cleaned substrate in ethanol solution for 5min;
1.3 The soaked substrate is taken out and put into a drying oven to be dried at the temperature of 100 ℃.
And secondly, growing the GaN buffer layer by using an MOCVD process, as shown in a figure 3 (a).
Putting the pretreated Si substrate into an MOCVD reaction chamber, adjusting the temperature of the reaction chamber to 950 ℃, simultaneously introducing ammonia gas with the flow of 2500sccm and a gallium source with the flow of 150sccm, and growing a GaN buffer layer 2 with the thickness of 4000nm on the substrate under the condition of keeping the pressure of 20 Torr.
And thirdly, growing the AlGaN barrier layer by using an MOCVD process, as shown in a figure 3 (b).
The temperature of the MOCVD reaction chamber was adjusted to 1100 ℃, and at the same time, ammonia gas at a flow rate of 2000sccm, a gallium source at a flow rate of 250sccm, and an aluminum source at a flow rate of 100sccm were introduced, and an AlGaN barrier layer 3 having a thickness of 20nm and an Al component of 0.2 was grown on the GaN buffer layer under a condition of maintaining the pressure at 20 Torr.
And step four, growing the InN channel layer by using an MOCVD process, as shown in a figure 3 (c).
The temperature of the MOCVD reaction chamber was adjusted to 600 ℃, ammonia gas at a flow rate of 1800sccm and an indium source at a flow rate of 100sccm were simultaneously introduced, and an InN channel layer 4 having a thickness of 20nm was grown on the AlGaN barrier layer under a condition of maintaining a pressure of 15 Torr.
And step five, growing the p-type InN layer by adopting an MOCVD process, as shown in a figure 3 (d).
Adjusting the temperature of the MOCVD reaction chamber to 600 ℃, simultaneously introducing ammonia gas with the flow rate of 1800sccm, a magnesium source with the flow rate of 100sccm and an indium source with the flow rate of 100sccm, and growing a film with the thickness of 60nm and the doping concentration of 2 multiplied by 10 on the InN channel layer under the condition of keeping the pressure of 15Torr 19 cm -3 P-type InN layer 5.
And step six, etching the gate groove by adopting a low-power plasma etching process, as shown in a figure 3 (e).
Adjusting the etching power of the equipment to be 30W and using Cl 2 And BCl 3 And etching a gate groove with the depth of 40nm in the center of the p-type InN layer.
Step seven, depositing source and drain, as shown in fig. 3 (f).
And evaporating mixed metal of titanium, aluminum, nickel and gold on the left side and the right side of the p-type InN layer by adopting an electron beam evaporation technology, and depositing a source electrode 7 and a drain electrode 8 which are both 25nm in thickness.
Step eight, growing SiO by adopting MOCVD process 2 And (g) a gate dielectric layer, as shown in FIG. 3 (g).
Adjusting the temperature of the MOCVD reaction chamber to 900 ℃, simultaneously introducing silane with the flow rate of 1000sccm and oxygen with the flow rate of 160sccm, and growing SiO with the thickness of 5nm on the groove of the p-type InN layer under the condition of keeping the pressure of 20Torr 2 And a gate dielectric layer 6.
Step nine, a gate is deposited, as shown in fig. 3 (h).
And evaporating mixed metal of titanium, aluminum, nickel and gold on the gate dielectric layer by adopting an electron beam evaporation technology, and depositing a gate 9 with the thickness of 70nm to finish the manufacture of the device.
Example 2, c-plane sapphire was used as a substrate, the thickness of the buffer layer was 4500nm, the thickness of the barrier layer was 25nm, and the Al component was present0.25, a channel layer thickness of 25nm, a p-type layer thickness of 65nm, a doping concentration of 3 × 10 19 cm -3 The thickness of the gate dielectric layer is 7nm, the thickness of the source electrode and the drain electrode is 35nm, and the thickness of the gate electrode is 87 nm.
And step A, cleaning and drying the sapphire substrate.
A1 Placing the sapphire substrate 1 in an acetone solution for ultrasonic cleaning for 15min;
b1 Soaking the cleaned substrate in ethanol solution for 8min;
c1 The soaked substrate is taken out and put into a drying oven, and drying treatment is carried out at the temperature of 110 ℃.
And step B, growing the GaN buffer layer by using an MOCVD process, as shown in figure 3 (a).
And putting the pretreated sapphire substrate into an MOCVD reaction chamber, and growing a GaN buffer layer 2 with the thickness of 4500nm on the substrate.
The growth process conditions are as follows: the chamber temperature was 1050 deg.C, the chamber pressure was 40Torr, and the gases introduced were ammonia gas at a flow rate of 2700sccm and a gallium source at a flow rate of 170 sccm.
And step C, growing the AlGaN barrier layer by using an MOCVD process, as shown in a figure 3 (b).
An AlGaN barrier layer 3 having a thickness of 25nm and an Al composition of 0.25 was grown on the GaN buffer layer.
The growth process conditions are as follows: the temperature of the MOCVD reaction chamber was 1120 ℃, the pressure of the reaction chamber was 40Torr, and the introduced gases were ammonia gas at a flow rate of 2100sccm, a gallium source at a flow rate of 260sccm, and an aluminum source at a flow rate of 130 sccm.
And D, growing the InN channel layer by using an MOCVD process, as shown in a figure 3 (c).
An InN channel layer 4 with a thickness of 25nm was grown on the AlGaN barrier layer.
The growth process conditions are as follows: the temperature of the MOCVD reaction chamber was 700 ℃ and the pressure in the reaction chamber was 30Torr, and ammonia gas and an indium source were introduced at 1900sccm and 130sccm, respectively.
And E, growing the p-type InN layer by using an MOCVD process, as shown in a figure 3 (d).
Growing the InN channel layer with the thickness of 65nm and the doping concentration of 3 multiplied by 10 19 cm -3 P-type InN layer 5.
The growth process conditions are as follows: the temperature of the MOCVD reaction chamber was 700 ℃ and the pressure of the reaction chamber was 30Torr, and the introduced gas was ammonia gas at a flow rate of 1900sccm, a magnesium source at a flow rate of 200sccm, and an indium source at a flow rate of 130 sccm.
Step F, etching the gate recess using a low power plasma etch process, as shown in fig. 3 (e).
Adjusting the etching power of the equipment to be 40W and using Cl 2 And BCl 3 And etching a gate groove with the depth of 45nm in the center of the p-type InN layer.
Step G, depositing source and drain electrodes, as shown in fig. 3 (f).
And evaporating mixed metal of titanium, aluminum, nickel and gold on the left side and the right side of the p-type InN layer by adopting an electron beam evaporation technology, and depositing a source electrode 7 and a drain electrode 8 with the thicknesses of 35 nm.
Step H, growing SiO by MOCVD process 2 And (g) a gate dielectric layer, as shown in FIG. 3 (g).
Growing SiO with the thickness of 7nm on the groove of the p-type InN layer 2 And a gate dielectric layer 6.
The growth process conditions are as follows: the MOCVD reaction chamber temperature was 1050 deg.C, the reaction chamber pressure was 40Torr, and the gases fed were silane at a flow rate of 1050sccm and oxygen at a flow rate of 190 sccm.
Step I, the gate is deposited, as in fig. 3 (h).
And evaporating mixed metal of titanium, aluminum, nickel and gold on the gate dielectric layer by adopting an electron beam evaporation technology, and depositing a gate 9 with the thickness of 87nm to finish the manufacture of the device.
Example 3 production of a substrate<111>The thickness of the buffer layer of Si in the crystal orientation is 5000nm, the thickness of the barrier layer is 30nm, the Al component is 0.3, the thickness of the channel layer is 30nm, the thickness of the p-type layer is 70nm, and the doping concentration is 4 multiplied by 10 19 cm -3 The thickness of the gate dielectric layer is 10nm, the thickness of the source electrode and the drain electrode is 40nm, and the thickness of the gate electrode is 100nm.
Step 1, preprocessing a Si substrate.
Placing the Si substrate 1 in an acetone solution for ultrasonic cleaning for 20min; soaking the cleaned substrate in an ethanol solution for 10min; taking out the soaked substrate, putting the substrate into a drying box, and drying at 120 ℃.
Step 2, growing a GaN buffer layer by using an MOCVD process, as shown in fig. 3 (a).
And putting the pretreated Si substrate into an MOCVD reaction chamber, keeping the temperature of the reaction chamber at 1100 ℃ and the pressure at 60Torr, introducing ammonia gas with the flow of 3000sccm and a gallium source with the flow of 180sccm simultaneously, and growing a GaN buffer layer 2 with the thickness of 5000nm on the substrate.
And 3, growing the AlGaN barrier layer by using an MOCVD process, as shown in a figure 3 (b).
While keeping the temperature of the MOCVD reaction chamber at 1150 ℃ and the pressure at 60Torr, ammonia gas with a flow rate of 2200sccm, a gallium source with a flow rate of 270sccm and an aluminum source with a flow rate of 150sccm were introduced, and an AlGaN barrier layer 3 with a thickness of 30nm and an Al composition of 0.3 was grown on the GaN buffer layer.
And 4, growing the InN channel layer by using an MOCVD process, as shown in a figure 3 (c).
The temperature of the MOCVD reaction chamber was maintained at 800 ℃ and the pressure at 40Torr, while introducing ammonia gas at a flow rate of 2000sccm and an indium source at a flow rate of 150sccm, and an InN channel layer 4 having a thickness of 30nm was grown on the AlGaN barrier layer.
And 5, growing the p-type InN layer by adopting an MOCVD process, as shown in a figure 3 (d).
Maintaining the temperature of the MOCVD reaction chamber at 800 deg.C and the pressure at 40Torr, introducing ammonia gas at a flow of 2000sccm, a magnesium source at a flow of 300sccm, and an indium source at a flow of 150sccm, and growing a layer of 70nm thick and a doping concentration of 4 × 10 on the InN channel layer 19 cm -3 P-type InN layer 5.
Step 6, etching the gate recess by using a low power plasma etching process, as shown in fig. 3 (e).
Adjusting the etching power of the equipment to be 50W and using Cl 2 And BCl 3 And a gate groove with the depth of 50nm is etched in the center of the p-type InN layer 5.
And evaporating mixed metal of titanium, aluminum, nickel and gold on the left side and the right side of the p-type InN layer by adopting an electron beam evaporation technology, and depositing a source electrode 7 and a drain electrode 8 which are both 40nm in thickness.
Keeping the temperature of the MOCVD reaction chamber at 1200 ℃ and the pressure at 60Torr, simultaneously introducing silane with the flow of 1100sccm and oxygen with the flow of 210sccm, and growing SiO with the thickness of 10nm on the groove of the p-type InN layer 2 And a gate dielectric layer 6.
Step 9, deposit the grid, as in figure 3 (h).
And evaporating mixed metal of titanium, aluminum, nickel and gold on the gate dielectric layer by adopting an electron beam evaporation technology, and depositing a gate 9 with the thickness of 100nm to finish the manufacture of the device.
The foregoing description is only three specific examples of the present invention and should not be construed as limiting the invention in any way, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made without departing from the principle and structure of the invention, but these modifications and variations will still fall within the scope of the appended claims.
Claims (12)
1. A p-channel metal oxide semiconductor field effect transistor based on InN/AlGaN/GaN heterojunction comprises the following components from bottom to top: substrate layer (1), gaN buffer layer (2), alGaN barrier layer (3), p type layer (5), gate dielectric layer (6), both ends are equipped with source electrode (7) and drain electrode (8) respectively about this gate dielectric layer, and middle sculpture has the bars recess, and groove department is equipped with grid (9), its characterized in that:
the p-type layer (5) is made of InN materials so as to improve the hole mobility;
the gate dielectric layer (6) is made of SiO 2 Materials to reduce gate leakage;
an undoped InN channel layer (4) is additionally arranged between the AlGaN barrier layer (3) and the p-type layer (5) to improve the two-dimensional hole gas concentration and the hole mobility.
2. The transistor of claim 1, wherein: the substrate layer (1) is a Si substrate with a <111> crystal orientation or a c-plane sapphire substrate.
3. The transistor of claim 1, wherein:
the InN channel layer (4) is 20-30nm thick;
the thickness of the p-type InN layer (5) is 60-70nm, and the doping concentration is 2 multiplied by 10 19 cm -3 -4×10 19 cm -3 ；
The SiO 2 And the thickness of the gate dielectric layer (6) is 5-10nm.
4. The transistor of claim 1, wherein:
the thickness of the GaN buffer layer (2) is 4000-5000nm;
the AlGaN barrier layer (3) is 20-30nm thick, and the Al component is 0.2-0.3;
the thickness of the source electrode (7) and the thickness of the drain electrode (8) are both 25-40nm;
the thickness of the grid (9) is 70-100nm.
5. A method for manufacturing a p-channel metal oxide semiconductor field effect tube based on InN/AlGaN/GaN heterojunction is characterized by comprising the following steps:
1) Cleaning and drying the substrate (1);
2) Growing a GaN buffer layer (2) with the thickness of 4000-5000nm on the dried substrate by adopting an MOCVD process;
3) Growing an AlGaN barrier layer (3) with the thickness of 20-30nm on the GaN buffer layer (2) by adopting an MOCVD process, wherein the adjusting range of the Al component is 0.2-0.3;
4) An InN channel layer (4) with the thickness of 20-30nm is grown on the AlGaN barrier layer (3) by adopting an MOCVD process;
5) Growing a p-type InN layer (5) with the thickness of 60-70nm on the InN channel layer (4) by adopting an MOCVD process, wherein the doping element is Mg, and the doping concentration is 2 multiplied by 10 19 cm -3 ～4×10 19 cm -3 ；
6) Etching a gate groove with the depth of 40-50nm in the center of the p-type InN layer (5) by using a low-power plasma etching process;
7) Evaporating mixed metal of titanium, aluminum, nickel and gold on the left side and the right side of the p-type InN layer (5) by using an electron beam evaporation technology, and depositing a source electrode (7) and a drain electrode (8) with the thicknesses of 25-40nm;
8) Growing SiO with the thickness of 5-10nm on the groove of the p-type InN layer (5) by adopting the MOCVD process 2 A gate dielectric layer (6);
9) And (3) evaporating the mixed metal of titanium, aluminum, nickel and gold on the gate dielectric layer by using an electron beam evaporation technology, and depositing a gate (9) with the thickness of 70-100nm to finish the manufacture of the device.
6. The method of claim 4, wherein the substrate is cleaned and dried in step 1) using a standard cleaning process, and the following is achieved:
1a) Placing the substrate in an acetone solution for ultrasonic cleaning for 5-20min;
1b) Soaking the cleaned substrate in ethanol solution for 5-10min;
1c) Taking out the soaked substrate, putting the substrate into a drying box, and drying at the temperature of 100-120 ℃.
7. The method as claimed in claim 4, wherein the MOCVD process adopted in step 2) is to set the following condition parameters for the reaction chamber:
the temperature of the reaction chamber is 950-1100 ℃,
the pressure in the reaction chamber is kept at 20-60Torr,
introducing two gases of ammonia gas with the flow rate of 2500-3000sccm and a gallium source with the flow rate of 150-180sccm into the reaction chamber.
8. The method as claimed in claim 4, wherein the MOCVD process adopted in step 3) is to set the following condition parameters for the reaction chamber:
the temperature of the reaction chamber is 1100-1150 ℃,
the pressure in the reaction chamber is kept at 20-60Torr,
and introducing three gases of ammonia gas with the flow rate of 2000-2200sccm, a gallium source with the flow rate of 250-270sccm and an aluminum source with the flow rate of 100-150sccm into the reaction chamber.
9. The method as claimed in claim 4, wherein the MOCVD process adopted in the step 4) is to set the following condition parameters for the reaction chamber:
the temperature of the reaction chamber is 600-800 ℃,
the pressure in the reaction chamber is kept at 15-40Torr,
introducing two gases of ammonia gas with the flow rate of 1800-2000sccm and indium source with the flow rate of 100-150sccm into the reaction chamber.
10. The method as claimed in claim 4, wherein the MOCVD process adopted in the step 5) is to set the following condition parameters for the reaction chamber:
the temperature of the reaction chamber is 600-800 ℃,
the pressure in the reaction chamber is kept at 15-40Torr,
and introducing three gases of ammonia gas with the flow rate of 1800-2000sccm, a magnesium source with the flow rate of 100-300sccm and an indium source with the flow rate of 100-150sccm into the reaction chamber.
11. The method of claim 4, wherein the low power plasma etching process used in step 6) is set with the following condition parameters:
the etching gas is Cl 2 And BCl 3 ，
The etching power is 30-50W.
12. The method as claimed in claim 4, wherein the MOCVD process adopted in step 8) is to set the following condition parameters for the reaction chamber:
the temperature of the reaction chamber is 900-1200 ℃,
the pressure in the reaction chamber is kept at 20-60Torr,
two gases, silane at a flow rate of 1000-1100sccm and oxygen at a flow rate of 160-210sccm, are simultaneously introduced into the reaction chamber.
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