CN115036310A - CMOS device based on GaN/YAlN/GaN heterojunction and manufacturing method thereof - Google Patents

CMOS device based on GaN/YAlN/GaN heterojunction and manufacturing method thereof Download PDF

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CN115036310A
CN115036310A CN202210712707.XA CN202210712707A CN115036310A CN 115036310 A CN115036310 A CN 115036310A CN 202210712707 A CN202210712707 A CN 202210712707A CN 115036310 A CN115036310 A CN 115036310A
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gan
layer
thickness
yaln
isolation groove
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许晟瑞
刘旭
贠博祥
张涛
张雅超
薛军帅
王心颢
卢灏
徐爽
高源�
张进成
郝跃
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

Abstract

The invention discloses a CMOS device based on a GaN/YAlN/GaN heterojunction and a manufacturing method thereof, and mainly solves the problems of low carrier concentration and low mobility of the existing GaN-based CMOS. It includes from bottom to top: the device comprises a substrate, a buffer layer, a GaN n-type channel layer, a YAlN barrier layer, a GaN p-type channel layer, a p-GaN layer and an insulated gate dielectric layer, wherein an isolation groove with the depth reaching the middle part of the n-type channel layer is arranged in the middle; a right gate electrode is arranged on the p-GaN layer on the right side of the isolation groove, and a right source electrode and a right drain electrode are arranged at two ends of the YAlN barrier layer to form an n-type field effect transistor; and a left gate electrode is arranged on the insulating gate dielectric layer on the left side of the isolation groove, a left source electrode and a left drain electrode are arranged at two ends of the p-GaN layer to form a p-type field effect tube, and the two field effect tubes are interconnected. The invention can improve the carrier concentration and mobility of the CMOS device, improve the working frequency and output power of the device, and can be used for a full GaN power system.

Description

CMOS device based on GaN/YAlN/GaN heterojunction and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a GaN-based complementary metal oxide semiconductor field effect transistor CMOS which can be used for monolithic integration of a power switch and other peripheral circuits, namely an all-GaN power system.
Technical Field
Compared with Si materials applied to traditional electronic power devices, the III-nitride semiconductor material has the advantages of large forbidden band width, high breakdown electric field strength, high saturated electron mobility, large thermal conductivity, small dielectric constant, strong radiation resistance and the like. Furthermore, polarization-induced carrier density in gallium nitride is independent of temperature. Therefore, GaN is considered a good candidate material for power integrated circuits that are applied under harsh environmental conditions.
In current power modules involving GaN devices, the peripheral logic control and drive circuitry is still implemented by a separate Si CMOS integrated circuit. This approach can take up a lot of circuit board space and can create parasitic inductance, which greatly limits the high switching frequency advantage of GaN HEMT devices, and thus the frequency of the system is affected. Monolithic integration of GaN drive logic and GaN power switching devices is extremely important to achieve small volume power modules with low parasitic inductance and high switching speed. The 'full GaN' solution helps to release the full potential of GaN power electronic devices, especially the high-speed switching capability, can greatly suppress parasitic inductance generated by off-chip interconnection, and can also enhance system-level function and reliability. In recent two years, complementary logic circuits based on GaN have been studied and proven, as have monolithic GaN CL gates with true "CMOS-like" behavior. The GaN-based complementary logic integrated circuit is just at a starting stage at present, the performance of a device needs to be further optimized, the carrier concentration and the mobility need to be improved, and particularly the current GaN-based p-channel MOSFET has low channel mobility and high on-resistance.
The structure of a conventional CMOS device adopting a GaN/AlGaN/GaN heterojunction is shown in figure 1, and the conventional CMOS device is composed of a substrate, a buffer layer, a GaN n-type channel layer, an AlGaN barrier layer and a p-GaN layer from bottom to top, wherein an isolation groove is arranged in the middle; a right gate electrode is arranged on the p-GaN layer on the right side of the isolation groove, and a right source electrode and a right drain electrode are arranged at two ends of the barrier layer on the right side of the isolation groove to form an n-type field effect transistor n-FET; and a left gate electrode is arranged on the insulated gate dielectric layer on the left side of the isolation groove, and a left source electrode and a left drain electrode are arranged at two ends of the p-GaN layer on the left side of the isolation groove to form a p-type field effect transistor p-FET. This device suffers from the following three disadvantages:
firstly, tensile strain is generated due to lattice mismatch between the AlGaN material and the GaN material, and the larger strain causes deterioration of crystal quality and reduces device performance.
Secondly, the polarization strength of the AlGaN barrier layer is limited, and the concentration and the mobility of two-dimensional hole gas generated by the polarization effect are not high enough, so that the response speed of the device is limited.
And thirdly, the polarization strength of the barrier layer can be enhanced only by improving the Al component of AlGaN, so that not only is the lattice mismatch between layers further increased, but also the difficulty of the epitaxial technology is increased, and in addition, the critical relaxation thickness of the material is also influenced to be sharply reduced, so that the concentration of two-dimensional electron gas and two-dimensional hole gas is influenced, and the output characteristic of the device is deteriorated.
Disclosure of Invention
The invention aims to provide a CMOS device based on a GaN/YAlN/GaN heterojunction and a manufacturing method thereof aiming at the defects of the prior art, so as to effectively reduce the strain of a barrier layer, improve the crystal quality, enhance the polarization strength of the barrier layer, improve the carrier concentration and the mobility, improve the working frequency and the output power of the device and improve the reliability of the device.
The technical scheme for realizing the purpose of the invention is as follows:
1. a GaN/YAlN/GaN heterojunction-based CMOS device comprising, from bottom to top: the GaN-based light-emitting diode comprises a substrate, a buffer layer, a GaN n-type channel layer, a barrier layer, a p-GaN layer and an insulated gate dielectric layer, wherein an isolation groove is arranged among the p-GaN layer, the barrier layer and the GaN n-type channel layer, and the depth of the isolation groove reaches the middle part of the GaN n-type channel layer; a right gate electrode is arranged on the p-GaN layer on the right side of the isolation groove, and a right source electrode and a right drain electrode are arranged at two ends of the barrier layer on the right side of the isolation groove to form an n-type field effect transistor n-FET; the left insulated gate dielectric layer of the isolation groove is provided with a left gate electrode, and the two ends of the left p-GaN layer of the isolation groove are provided with a left source electrode and a left drain electrode to form a p-type field effect transistor p-FET, and the p-FET is characterized in that:
an undoped GaN p-type channel layer with the thickness of 20nm-40nm is additionally arranged between the p-GaN layer and the barrier layer on the two sides of the isolation groove so as to improve the carrier mobility;
the barrier layer is made of YAlN material with 85-94% of Al component and 15-30 nm of thickness, so that the strain of the barrier layer is reduced, and the polarization strength of the barrier layer is enhanced.
Further, the substrate employs Si of <111> crystal orientation.
Furthermore, the buffer layer is made of GaN material, and the thickness of the buffer layer is 3-4.5 μm.
Further, the thickness of the p-GaN layer is 70nm-80nm, and the doping concentration is 3 multiplied by 10 19 cm -3 -4×10 19 cm -3 。
Further, the thickness of the GaN n-type channel layer is 150nm-480 nm.
Furthermore, the insulated gate dielectric layer adopts Al 2 O 3 The material has a thickness of 10nm-20 nm.
2. A preparation method of a CMOS device based on a GaN/YAlN/GaN heterojunction is characterized by comprising the following steps:
1) growing a buffer layer with the thickness of 3-4.5 microns on a substrate by utilizing an MOCVD process;
2) growing a GaN n-type channel layer with the thickness of 150nm-480nm on the buffer layer by utilizing an MOCVD (metal organic chemical vapor deposition) process;
3) growing a YAlN barrier layer with 15nm-30nm of Al component of 85% -94% on the GaN n-type channel layer by using an MOCVD process;
4) growing an undoped GaN p-type channel layer with the thickness of 20nm-40nm on the YAlN barrier layer by using an MOCVD process;
5) growing a p-GaN layer with the thickness of 70nm-80nm on the GaNp type channel layer by utilizing an MOCVD process;
6) carrying out selective dry etching on the p-GaN layer, wherein the etching depth is from the surface to the interface of the GaN p-type channel layer and the YAlN barrier layer;
7) depositing Ti/Al/Ni/Au metal lamination with the thickness of 20nm/120nm/40nm/50nm in sequence at two ends of the etched YAlN barrier layer by adopting an electron beam evaporation process, and then depositing N at 830-900 DEG C 2 Forming a right source electrode and a right drain electrode by rapid thermal annealing in the environment;
8) step etching is carried out on the YAlN barrier layer on the left side of the right drain electrode by adopting a plasma reactive ion etching process to form an isolation groove with the depth of 150 nm;
9) depositing Ni/Au metal lamination with the thickness of 15nm/20nm at two ends of the p-GaN layer on the left side of the isolation groove by adopting an electron beam evaporation process, and forming O at 550 DEG C 2 Annealing in the environment to form a left source electrode and a left drain electrode, simultaneously performing the same electron beam evaporation deposition of a metal lamination on the p-GaN layer on the right side of the isolation groove, and manufacturing a right gate electrode to form an n-type field effect transistor n-FET on the right side of the isolation groove;
10) etching the p-GaN layer on the left side of the isolation groove by using a low-damage GaN etching technology, wherein the etching depth is 55nm-68nm, and the N temperature is 450 ℃ -500 DEG C 2 Annealing in the atmosphere to form a gate groove;
11) depositing an insulated gate dielectric layer with the thickness of 10nm-20nm on the gate groove by adopting an atomic layer deposition process;
12) depositing Ti/Au metal lamination layers with the thickness of 20nm/100nm on the insulated gate dielectric layer by adopting an electron beam evaporation process to manufacture a left gate electrode so as to form a p-type n-type field effect transistor p-FET on the left side of the isolation groove;
13) and respectively evaporating Ti/Au metal laminated layers on the electrodes of the n-FET and the p-FET by adopting an electron beam evaporation process to realize the interconnection of the n-FET and the p-FET of the two FETs and finish the manufacture of the device.
Compared with the prior art, the invention has the following advantages:
1. according to the invention, the undoped GaN p channel layer is inserted between the YAlN barrier layer and the p-GaN layer, so that the influence of ionized impurity scattering on a current carrier can be effectively weakened, the mobility of the two-dimensional hole gas 2DHG is improved, and the speed of the p-FET of the p-type field effect transistor is effectively improved.
2. The invention adopts YAlN as the barrier layer, the material belongs to transition metal nitride, and the material has strong polarization effect and can generate a plurality of effects:
firstly, the carrier density in the GaN n channel layer and the p channel layer can be obviously improved, thereby improving the current and power characteristics of the device,
secondly, the lattice-matched stress-free epitaxial growth can be realized by adjusting the alloy components and the GaN, and the stress-free growth not only can effectively improve the crystal quality, but also can greatly reduce the difficulty of the epitaxial process.
And thirdly, lattice matching can be realized between YAlN and GaN, the state of a heterogeneous interface is effectively improved, the influence of interface scattering on a current carrier is weakened, the mobility of two-dimensional electron gas 2DEG and two-dimensional hole gas 2DHG is improved, and the switching characteristic of the device is effectively improved.
Drawings
FIG. 1 is a block diagram of a prior art GaN/AlGaN/GaN heterojunction based CMOS device;
FIG. 2 is a block diagram of a GaN/YAlN/GaN heterojunction based CMOS device of the present invention;
FIG. 3 is a schematic flow chart of the present invention for fabricating a GaN/YAlN/GaN heterojunction based CMOS device.
Detailed Description
Embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, the CMOS device based on GaN/YAlN/GaN heterojunction of the present invention comprises, from bottom to top: the GaN/YAlN/GaN heterojunction field effect transistor comprises a substrate 1, a buffer layer 2, a GaNn type channel layer 3, a barrier layer 4, a GaNp type channel layer 5, a p-GaN layer 6 and an insulated gate dielectric layer 7, wherein the GaN/YAlN/GaN heterojunction is formed by the GaN n type channel layer 3, the barrier layer 4 and the GaN p type channel layer 5; an isolation groove 8 is arranged among the p-GaN layer 6, the GaN p-type channel layer 5, the barrier layer 4 and the GaN n-type channel layer 3, and the depth of the isolation groove 8 reaches the middle part of the GaN n-type channel layer 3; a right gate electrode 9 is arranged on the p-GaN layer 6 on the right side of the isolation groove 8, and a right source electrode 10 and a right drain electrode 11 are arranged at two ends of the barrier layer 4 on the right side of the isolation groove 8 to form an n-type field effect transistor n-FET; and a left gate electrode 12 is arranged on the insulated gate dielectric layer 7 on the left side of the isolation groove 8, and a left source electrode 13 and a left drain electrode 14 are arranged at two ends of the p-GaN layer 6 on the left side of the isolation groove 8 to form a p-type field effect transistor p-FET. Wherein:
the substrate 1 is made of Si with a <111> crystal orientation;
the buffer layer 2 is made of GaN material, and the thickness of the buffer layer is 3-4.5 μm;
the thickness of the GaN n-type channel layer 3 is 150nm-480 n;
the barrier layer 4 is made of YAlN material with 85-94% of Al component and 15-30 nm of thickness to reduce the strain of the barrier layer and enhance the polarization strength of the barrier layer, and is positioned on the GaN n-type channel layers 3 at two sides of the isolation groove 8;
the GaNp type channel layer 5 is 20nm-40nm thick and undoped and is positioned on the barrier layers 4 at two sides of the isolation groove 8;
the thickness of the p-GaN layer 6 is 70nm-80nm, and the doping concentration is 3 multiplied by 10 19 cm -3 -4×10 19 cm -3 On the GaN p-type channel layers 5 on both sides of the isolation trench 8;
the insulated gate dielectric layer 7 adopts Al 2 O 3 A material having a thickness of 10nm to 20nm is located on the p-GaN layer 6 at the left side of the isolation trench 8.
Referring to fig. 3, the present invention provides three embodiments of a GaN/YAlN/GaN heterojunction based CMOS structure and a method of fabricating the same.
Example 1A GaN buffer layer having a thickness of 3 μm, a GaN n-channel layer having a thickness of 150nm, and Y 0.15 Al 0.85 Thickness of N barrier layerDegree of 15nm, GaNp channel layer thickness of 20nm, Al 2 O 3 The thickness of the insulated gate dielectric layer is 10nm, the thickness of the p-GaN layer is 70nm, and the doping concentration is 3 multiplied by 10 19 cm -3 The CMOS device of (a).
Step one, a GaN buffer layer is epitaxially grown, as shown in fig. 3 (a).
The Si substrate with the <111> crystal orientation is placed in an MOCVD reaction chamber, the temperature of the reaction chamber is set to 950 ℃, the pressure is set to 20Torr, a nitrogen source with the flow of 2500sccm and a gallium source with the flow of 20sccm are simultaneously introduced, and a GaN buffer layer 2 with the thickness of 3 mu m grows on the Si substrate.
Step two, the GaN n channel layer is epitaxial, as shown in fig. 3 (b).
Keeping the temperature of the reaction chamber at 950 ℃, keeping the pressure of the reaction chamber at 20Torr, simultaneously introducing a nitrogen source with the flow of 2500sccm and a gallium source with the flow of 20sccm, and growing a 150 nm-thick GaN n channel layer 3 on the GaN buffer layer.
And step three, extending the YAlN barrier layer, as shown in FIG. 3 (c).
Keeping the temperature of the reaction chamber at 950 ℃, keeping the pressure of the reaction chamber at 20Torr, simultaneously introducing a nitrogen source with the flow of 2500sccm, an yttrium source with the flow of 60sccm and an aluminum source with the flow of 300sccm, and growing Y with the thickness of 15nm on the GaN n channel layer 0.15 Al 0.85 An N barrier layer 4.
Step four, the GaN p channel layer is epitaxially grown, as shown in fig. 3 (d).
Keeping the temperature of the reaction chamber at 950 ℃, keeping the pressure of the reaction chamber at 20Torr, simultaneously introducing a nitrogen source with the flow of 2500sccm and a gallium source with the flow of 20sccm, and growing a GaNp channel layer 5 with the thickness of 20nm on the YAlN barrier layer.
And step five, extending the p-GaN layer, as shown in figure 3 (e).
Keeping the temperature of the reaction chamber at 950 ℃, keeping the pressure of the reaction chamber at 20Torr, simultaneously introducing a nitrogen source with the flow of 2500sccm, a gallium source with the flow of 150sccm and a magnesium source with the flow of 100sccm, and growing a p-GaN layer 6 with the thickness of 70nm on the GaNp channel layer.
Step six, dry etching the p-GaN layer, as shown in FIG. 3 (f).
Using Cl 2 /BCl 3 And selectively etching the p-GaN layer by using the dry etching of plasma, and controlling the etching depth from the surface to the interface between the GaNp type channel layer and the YAlN barrier layer by using time.
And step seven, manufacturing a right source electrode and a right drain electrode, as shown in fig. 3 (g).
Depositing metal on the etched YAlN barrier layer by electron beam evaporation process, wherein the metal lamination layer is Ti/Al/Ni/Au, the thickness is 20nm/120nm/40nm/50nm, and the temperature is 830 ℃ N 2 The right source electrode 10 and the right drain electrode 11 are formed by rapid thermal annealing in ambient for 30 s.
And step eight, performing step etching to form an isolation groove, as shown in fig. 3 (h).
Defining active regions of n-type field effect transistor n-FET and p-type field effect transistor p-FET using a photolithographic mask using a Cl-based mask 2 /BCl 3 The inductively coupled plasma reactive ion etching of (a) the right drain electrode (the YAlN barrier layer on the left side was step-etched to an etching depth of 150nm, forming an isolation trench 8 from the p-GaN layer to the middle of the n-channel layer.
And a ninth step of manufacturing a left source electrode, a left drain electrode and a right gate electrode, as shown in fig. 3 (i).
Depositing Ni/Au metal lamination layers with the thickness of 15nm/20nm on the p-GaN layer at the left side of the isolation groove and the p-GaN layer at the right side of the isolation groove by using an electron beam evaporation process, and forming O at 550 DEG C 2 After annealing for 5 minutes in the ambient atmosphere, the left source electrode 13 and the left drain electrode 14 were formed on the p-GaN layer on the left side of the isolation trench, and the right gate electrode 9 was formed on the p-GaN layer on the right side of the isolation trench.
Step ten, etching the gate groove, as shown in fig. 3 (j).
Using low damage Cl 2 /BCl 3 Etching the p-GaN on the left side of the isolation groove by a slow etching process at the etching rate of 2.4nm/min and the etching depth of 55nm, and then using NH to etch the sample 3 :H 2 O (1:6) at 55 deg.C for 5 minutes to remove surface contaminants and residual photoresist, and N at 450 deg.C 2 Annealing for 5 minutes in the environment reduces surface damage caused by etching, and a gate groove is obtained.
Step eleven, depositing an insulated gate dielectric layer as shown in fig. 3 (k).
Depositing by using an atomic layer deposition process to deposit Al with the thickness of 10nm on the gate groove 2 O 3 And an insulated gate dielectric layer 7.
Step twelve, a left gate electrode is fabricated, as shown in fig. 3 (l).
And depositing a Ti/Au metal lamination layer with the thickness of 20nm/100nm on the insulated gate dielectric layer by using an electron beam evaporation process to form the left gate electrode 12.
So far, a p-type FET p-FET is formed on the left side of the isolation trench, and an n-type FET n-FET is formed on the right side of the isolation trench.
Step thirteen, devices are interconnected, as shown in fig. 3 (m).
And (3) evaporating and plating a Ti/Au metal lamination on the electrodes of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET by using an electron beam evaporation process to realize the interconnection of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET and complete the manufacture of the device.
Example 2 production of GaN buffer layer with thickness of 4 μm, GaN n-channel layer with thickness of 420nm, Y 0.1 Al 0.9 The thickness of the N barrier layer is 25nm, the thickness of the GaNp channel layer is 30nm, the thickness of the p-GaN layer is 75nm, and the doping concentration is 3.5 multiplied by 10 19 cm -3 、Al 2 O 3 And the thickness of the insulated gate dielectric layer is 15 nm.
Step 1, a GaN buffer layer is epitaxially grown, as shown in fig. 3 (a).
A <111> crystal orientation Si substrate was placed in an MOCVD reaction chamber, the conditions of the reaction chamber were set at 1000 ℃ and 40Torr, and a GaN buffer layer 2 having a thickness of 4 μm was grown on the Si substrate under the process conditions of introducing a nitrogen source having a flow rate of 2800sccm and a gallium source having a flow rate of 40sccm into the reaction chamber, as shown in FIG. 3 (a).
Step 2, the GaN n channel layer is epitaxially grown, as shown in fig. 3 (b).
Keeping the temperature of the reaction chamber at 1000 ℃ and the pressure of the reaction chamber at 40Torr, simultaneously introducing a nitrogen source with the flow of 2800sccm and a gallium source with the flow of 40sccm into the reaction chamber, and growing a GaN n channel layer 3 with the thickness of 420nm on the GaN buffer layer by adopting an MOCVD method.
Step 3, epitaxy of the YAlN barrier layer, as shown in fig. 3 (c).
Maintaining the temperature of the reaction chamber at 1000 ℃ and the pressure of the reaction chamber at 40Torr, introducing a nitrogen source with the flow rate of 2800sccm, an yttrium source with the flow rate of 40sccm and an aluminum source with the flow rate of 320sccm into the reaction chamber, and growing Y with the thickness of 25nm on the GaN n channel layer by adopting an MOCVD method 0.1 Al 0.9 An N barrier layer 4.
Step 4, epitaxial growth of the GaN p channel layer, as shown in fig. 3 (d).
Keeping the temperature of the reaction chamber at 1000 ℃ and the pressure of the reaction chamber at 40Torr, simultaneously introducing a nitrogen source with the flow of 2800sccm and a gallium source with the flow of 40sccm into the reaction chamber, and growing a GaNp channel layer 5 with the thickness of 30nm on the YAlN barrier layer by adopting an MOCVD method.
And 5, extending the p-GaN layer, as shown in figure 3 (e).
And keeping the temperature of the reaction chamber at 1000 ℃ and the pressure of the reaction chamber at 40Torr, simultaneously introducing a nitrogen source with the flow of 2800sccm, a gallium source with the flow of 160sccm and a magnesium source with the flow of 190sccm into the reaction chamber, and growing a p-GaN layer 6 with the thickness of 75nm on the GaNp channel layer by adopting an MOCVD method.
Step 6, dry etching the p-GaN layer, as shown in FIG. 3 (f).
By using Cl 2 /BCl 3 And selectively etching the p-GaN layer by the dry etching of plasma, wherein the etching depth is from the surface to the interface of the GaN p-type channel layer and the YAlN barrier layer.
Step 7, manufacturing a right source electrode and a right drain electrode, as shown in fig. 3 (g).
Depositing metal on the etched YAlN barrier layer by electron beam evaporation process, wherein the metal lamination layer is Ti/Al/Ni/Au, the thickness is 20nm/120nm/40nm/50nm, and the temperature is 850 deg.C 2 The right source electrode 10 and the right drain electrode 11 are formed by rapid thermal annealing in ambient for 30 s.
And 8, performing step etching to form an isolation groove, as shown in fig. 3 (h).
Defining active regions of n-type field effect transistor n-FET and p-type field effect transistor p-FET using a photolithographic mask using a Cl-based mask 2 /BCl 3 The inductive coupling plasma reactive ion etching is used for right leakageThe YAlN barrier layer on the left side of the electrode is subjected to step etching, the etching depth is 150nm, and an isolation groove 8 from the p-GaN layer to the middle part of the n channel layer is formed.
And 9, manufacturing a left source electrode, a left drain electrode and a right gate electrode, as shown in fig. 3 (i).
Depositing Ni/Au metal lamination layers with the thickness of 15nm/20nm on the p-GaN layer at the left side of the isolation groove and the p-GaN layer at the right side of the isolation groove by using an electron beam evaporation process, and forming O at 550 DEG C 2 After annealing for 5 minutes in the ambient atmosphere, the left source electrode 13 and the left drain electrode 14 were formed on the p-GaN layer on the left side of the isolation trench, and the right gate electrode 9 was formed on the p-GaN layer on the right side of the isolation trench.
And step 10, manufacturing an insulated gate dielectric layer and a left gate electrode.
10.1) Using Low-damage Cl 2 /BCl 3 Etching the p-GaN on the left side of the isolation groove by a slow etching process, wherein the etching rate is 2.4nm/min, the etching depth is 58nm, and then using NH to the sample 3 :H 2 O (1:6) at 55 deg.C for 5 minutes to remove surface contaminants and residual photoresist, and N 2 Annealing for 5 minutes at 470 ℃ in the environment to reduce surface damage caused by etching, and obtaining the gate groove. As shown in fig. 3 (j).
10.2) depositing Al with the thickness of 15nm on the gate groove by utilizing an atomic layer deposition process 2 O 3 And an insulated gate dielectric layer 7. As shown in fig. 3 (k).
10.3) depositing a Ti/Au metal lamination with the thickness of 20nm/100nm on the insulated gate dielectric layer 7 by using an electron beam evaporation process to manufacture a left gate electrode 12, as shown in FIG. 3(l)
So far, a p-type field effect transistor p-FET is formed on the left side of the isolation trench, and an n-type field effect transistor n-FET is formed on the right side of the isolation trench.
And 11, evaporating Ti/Au metal lamination on the electrodes of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET by using an electron beam evaporation process to realize the interconnection of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET, and finishing the manufacture of the device as shown in figure 3 (m).
Example 3A GaN buffer layer 4.5 μm thick, a GaN n-channel layer 480nm thick, and Y 0.05 Al 0.95 N potentialThe barrier layer thickness is 30nm, the GaN p-channel layer thickness is 40nm, the p-GaN layer thickness is 80nm, and the doping concentration is 4 multiplied by 10 19 cm -3 、Al 2 O 3 And the thickness of the insulated gate dielectric layer is 20 nm.
Step A, a GaN buffer layer is epitaxially grown, as shown in FIG. 3 (a).
The <111> crystal orientation Si substrate is placed in an MOCVD reaction chamber, the temperature of the reaction chamber is set to be 1300 ℃, the pressure is set to be 60Torr, a nitrogen source with the flow rate of 4000sccm and a gallium source with the flow rate of 50sccm are simultaneously introduced, and a GaN buffer layer 2 with the thickness of 4.5 mu m is grown on the Si substrate.
Step B, the GaN n channel layer is epitaxial, as shown in fig. 3 (B).
And growing a GaN n channel layer 3 with the thickness of 480nm on the GaN buffer layer under the process conditions that the temperature of the reaction chamber is kept at 1300 ℃, the pressure of the reaction chamber is kept at 60Torr, and a nitrogen source with the flow rate of 4000sccm and a gallium source with the flow rate of 50sccm are simultaneously introduced.
Step C, the YAlN barrier layer is extended as shown in fig. 3 (C).
Growing Y with the thickness of 30nm on the GaN n channel layer under the process conditions that the temperature of the reaction chamber is kept at 1300 ℃, the pressure of the reaction chamber is kept at 60Torr, and a nitrogen source with the flow rate of 4000sccm, an yttrium source with the flow rate of 30sccm and an aluminum source with the flow rate of 350sccm are simultaneously introduced 0.05 Al 0.95 An N barrier layer 4.
And D, extending the GaNp channel layer, as shown in figure 3 (D).
And growing a GaN p channel layer 5 with the thickness of 40nm on the YAlN barrier layer under the process conditions that the temperature of the reaction chamber is kept at 1300 ℃, the pressure of the reaction chamber is kept at 60Torr, and a nitrogen source with the flow rate of 4000sccm and a gallium source with the flow rate of 50sccm are simultaneously introduced.
And E, extending the p-GaN layer, as shown in figure 3 (E).
And growing a p-GaN layer 6 with the thickness of 80nm on the GaN p channel layer under the process conditions that the temperature of the reaction chamber is kept at 1300 ℃, the pressure of the reaction chamber is kept at 60Torr, and a nitrogen source with the flow rate of 3000sccm, a gallium source with the flow rate of 180sccm and a magnesium source with the flow rate of 300sccm are simultaneously introduced.
Step F, dry etching the p-GaN layer, as shown in FIG. 3 (F).
Using Cl 2 /BCl 3 And selectively etching the p-GaN layer by using the dry etching of plasma, and controlling the etching depth from the surface to the interface between the GaNp type channel layer and the YAlN barrier layer by using time.
Step G, a right source electrode and a right drain electrode are fabricated as shown in fig. 3 (G).
Depositing metal on the etched YAlN barrier layer by electron beam evaporation process, wherein the metal lamination layer is Ti/Al/Ni/Au, the thickness is 20nm/120nm/40nm/50nm, and the thickness is N 2 And performing rapid thermal annealing at 900 ℃ for 30s in the environment to form the right source electrode 10 and the right drain electrode 11.
And step H, performing step etching to form an isolation groove, as shown in FIG. 3 (H).
Defining active regions of n-type field effect transistor n-FET and p-type field effect transistor p-FET using a photolithographic mask using a Cl-based mask 2 /BCl 3 The inductively coupled plasma reactive ion etching of (a) step-etching the YAlN barrier layer on the left side of the right drain electrode to an etching depth of 150nm, forming an isolation trench 8 formed from the p-GaN layer to the middle of the n channel layer.
And step I, manufacturing a left source electrode, a left drain electrode and a right gate electrode, as shown in figure 3 (I).
Depositing Ni/Au metal lamination layers with the thickness of 15nm/20nm on the p-GaN layer at the left side of the isolation groove and the p-GaN layer at the right side of the isolation groove by using an electron beam evaporation process, and forming O at 550 DEG C 2 After annealing for 5 minutes in the ambient atmosphere, the left source electrode 13 and the left drain electrode 14 were formed on the p-GaN layer on the left side of the isolation trench, and the right gate electrode 9 was formed on the p-GaN layer on the right side of the isolation trench.
And step J, manufacturing a left gate electrode.
J1) Using low damage Cl 2 /BCl 3 Etching the left side of the isolation groove at the speed of 2.4nm/min in p-GaN at the depth of 68nm by using a slow etching process; and using NH on the etched sample 3 :H 2 O (1:6) at 55 deg.C for 5 minutes to remove surface contaminants and residual photoresist, and N at 450 deg.C 2 Annealing for 5 minutes in the environment to reduce surface damage caused by etching to obtain a gate groove pattern, shown in (3 j)；
J2) Depositing by using an atomic layer deposition process to deposit Al with the thickness of 20nm on the gate groove 2 O 3 An insulated gate dielectric layer 7, as shown in fig. 3 (k);
J3) a Ti/Au metal stack is deposited on the insulated gate dielectric layer 7 by an electron beam evaporation process to a thickness of 20nm/100nm to fabricate a left gate electrode 12, as shown in fig. 3 (l).
So far, a p-type field effect transistor p-FET is formed on the left side of the isolation trench, and an n-type field effect transistor n-FET is formed on the right side of the isolation trench.
Step K, interconnection of devices, as shown in FIG. 3 (m).
And (3) evaporating and plating a Ti/Au metal lamination on the electrodes of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET by using an electron beam evaporation process so as to realize interconnection of the n-type field effect transistor n-FETp and the p-FET of the n-type field effect transistor p-FET and complete the manufacture of the device.
The foregoing description is only three specific examples of the present invention and should not be construed as limiting the invention in any way, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made without departing from the principle and structure of the invention, but these modifications and variations will still fall within the scope of the appended claims.

Claims (10)

1. A GaN/YAlN/GaN heterojunction-based CMOS device comprising, from bottom to top: the GaN-based light-emitting diode comprises a substrate (1), a buffer layer (2), a GaN n-type channel layer (3), a barrier layer (4), a p-GaN layer (6) and an insulated gate dielectric layer (7), wherein an isolation groove (8) is arranged among the p-GaN layer (6), the barrier layer (4) and the GaN n-type channel layer (3), and the depth of the isolation groove (8) reaches the middle part of the GaN n-type channel layer (3); a right gate electrode (9) is arranged on the p-GaN layer (6) on the right side of the isolation groove (8), and a right source electrode (10) and a right drain electrode (11) are arranged at two ends of the barrier layer (4) on the right side of the isolation groove (8) to form an n-type field effect transistor n-FET; be equipped with left gate electrode (12) on isolation trench (8) left insulated gate dielectric layer (7), isolation trench (8) left p-GaN layer (6) both ends are equipped with left source electrode (13), left drain electrode (14), form p type field effect transistor p-FET, its characterized in that:
an undoped GaNp type channel layer (5) with the thickness of 20nm-40nm is additionally arranged between the p-GaN layer (6) and the barrier layer (4) on the two sides of the isolation groove (8) so as to improve the carrier mobility;
the barrier layer (4) is made of YAlN material with 85-94% of Al component and 15-30 nm of thickness, so that strain of the barrier layer is reduced, and polarization strength of the barrier layer is enhanced.
2. The device of claim 1, wherein: the substrate (1) is made of Si with a <111> crystal orientation.
3. The device of claim 1, wherein: the buffer layer (2) is made of GaN material, and the thickness of the buffer layer is 3-4.5 μm.
4. The device of claim 1, wherein: the thickness of the GaN n-type channel layer (3) is 150nm-480 nm.
5. The device of claim 1, wherein: the thickness of the p-GaN layer (6) is 70nm-80nm, and the doping concentration is 3 multiplied by 10 19 cm -3 -4×10 19 cm -3 。
6. The device of claim 1, wherein: the insulated gate dielectric layer (7) adopts Al 2 O 3 The material has a thickness of 10nm-20 nm.
7. A preparation method of a CMOS device based on a GaN/YAlN/GaN heterojunction comprises the following steps:
1) growing a buffer layer (2) with the thickness of 3-4.5 microns on a substrate (1) by utilizing an MOCVD process;
2) growing a 150nm-480nm GaN n-type channel layer (3) on the buffer layer by using an MOCVD (metal organic chemical vapor deposition) process;
3) growing a YAlN barrier layer (4) with 15nm-30nm of Al component of 85% -94% on the GaN n-type channel layer by using an MOCVD process;
4) growing an undoped GaNp type channel layer (5) of 20nm to 40nm on the YAlN barrier layer by using an MOCVD process;
5) growing a p-GaN layer (6) with the thickness of 70nm-80nm on the GaNp type channel layer by utilizing an MOCVD process;
6) carrying out selective dry etching on the p-GaN layer, wherein the etching depth is from the surface to the interface of the GaNp type channel layer and the YAlN barrier layer;
7) depositing Ti/Al/Ni/Au metal lamination with the thickness of 20nm/120nm/40nm/50nm at two ends of the etched YAlN barrier layer by adopting an electron beam evaporation process, and then performing N deposition at the temperature of 830-900 DEG C 2 Forming a right source electrode (10) and a right drain electrode (11) by rapid thermal annealing in the environment;
8) step etching is carried out on the YAlN barrier layer on the left side of the right drain electrode (11) by adopting a plasma reactive ion etching process to form an isolation groove (8) with the depth of 150 nm;
9) depositing Ni/Au metal lamination with the thickness of 15nm/20nm at two ends of the p-GaN layer on the left side of the isolation groove by adopting an electron beam evaporation process, and forming O at 550 DEG C 2 Annealing in the environment to form a left source electrode (13) and a left drain electrode (14), and simultaneously performing the same electron beam evaporation deposition of metal lamination on the p-GaN layer on the right side of the isolation groove to manufacture a right gate electrode (9) so as to form an n-type field effect transistor (n-FET) on the right side of the isolation groove;
10) etching the p-GaN layer on the left side of the isolation groove by using a low-damage GaN etching technology, wherein the etching depth is 55nm-68nm, and the N temperature is 450 ℃ -500 DEG C 2 Annealing in the atmosphere to form a gate groove;
11) depositing an insulated gate dielectric layer (7) with the thickness of 10nm-20nm on the gate groove by adopting an atomic layer deposition process;
12) depositing a Ti/Au metal lamination layer with the thickness of 20nm/100nm on the insulated gate dielectric layer by adopting an electron beam evaporation process to manufacture a left gate electrode (12) so as to form a p-type n-type field effect transistor p-FET on the left side of the isolation groove;
13) and respectively evaporating Ti/Au metal laminations on the electrodes of the n-FET and the p-FET by adopting an electron beam evaporation process to realize the interconnection of the n-FET and the p-FET of the two field effect transistors and finish the manufacture of the device.
8. The method as claimed in claim 7, wherein the MOCVD process adopted in the steps 1), 2) and 4) is to set the following condition parameters for the reaction chamber:
the temperature of the reaction chamber is 950 ℃ and 1300 ℃,
the pressure in the reaction chamber is maintained at 20-60Torr,
a nitrogen source with the flow rate of 2500-.
9. The method as claimed in claim 7, wherein the MOCVD process used in step 3) sets the following condition parameters for the reaction chamber:
the temperature of the reaction chamber is 950 ℃ and 1300 ℃,
the pressure in the reaction chamber is maintained at 20-60Torr,
a nitrogen source with the flow rate of 2500-4000sccm, an yttrium source with the flow rate of 30-60sccm and an aluminum source with the flow rate of 280-350sccm are simultaneously introduced into the reaction chamber.
10. The method as claimed in claim 7, wherein the MOCVD process adopted in the step 5) is to set the following condition parameters for the reaction chamber:
the temperature of the reaction chamber is 950 ℃ and 1300 ℃,
the pressure in the reaction chamber is maintained at 20-60Torr,
ammonia gas with the flow rate of 2500-.
CN202210712707.XA 2022-06-22 2022-06-22 CMOS device based on GaN/YAlN/GaN heterojunction and manufacturing method thereof Pending CN115036310A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116364819A (en) * 2023-05-31 2023-06-30 江西兆驰半导体有限公司 LED epitaxial wafer, preparation method thereof and LED

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116364819A (en) * 2023-05-31 2023-06-30 江西兆驰半导体有限公司 LED epitaxial wafer, preparation method thereof and LED
CN116364819B (en) * 2023-05-31 2023-12-15 江西兆驰半导体有限公司 LED epitaxial wafer, preparation method thereof and LED

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