CN115188761A

CN115188761A - Semiconductor structure

Info

Publication number: CN115188761A
Application number: CN202110373396.4A
Authority: CN
Inventors: 华文宇; 何波涌
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2021-04-07
Filing date: 2021-04-07
Publication date: 2022-10-14

Abstract

A semiconductor structure, comprising: the substrate comprises a plurality of mutually-separated active regions, the active regions are arranged along a first direction and are parallel to a second direction, and the first direction is vertical to the second direction; the first grooves are arranged along the second direction and penetrate through the active regions along the first direction; the word line gate structure is positioned in the first groove and comprises a first side area and a second side area which are opposite, and the second side area is adjacent to the active area; the first isolation structure is positioned in the first groove, is adjacent to the first side region of the word line grid structure, is positioned between the word line grid structure and the active region, and is also positioned in part of the active region; a plurality of capacitor structures located on the first side of each active region; and the bit line structures are arranged along the first direction and are parallel to the second direction. The performance of the semiconductor structure is improved.

Description

Semiconductor structure

Technical Field

The invention relates to the field of semiconductors, in particular to a semiconductor structure.

Background

A Dynamic Random Access Memory (DRAM) is a semiconductor Memory, and the main action principle is to represent whether a binary bit (bit) is 1 or 0 by using the amount of charges stored in a capacitor.

A basic memory cell of a Dynamic Random Access Memory (DRAM) is composed of a transistor and a storage capacitor, and a memory array is composed of a plurality of memory cells. Therefore, the size of the memory chip area depends on the area size of the basic memory cell.

The existing dynamic random access memory is still to be improved.

Disclosure of Invention

The present invention provides a semiconductor structure to improve the performance of a dynamic random access memory.

To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a first surface and a second surface which are opposite, the substrate comprises a plurality of mutually-separated active areas, the active areas are arranged along a first direction and are parallel to a second direction, and the first direction and the second direction are mutually vertical; a plurality of first grooves located in the substrate, the first grooves extending from a first surface to a second surface, the plurality of first grooves being arranged along a second direction, and the first grooves penetrating the plurality of active regions along the first direction; a word line gate structure located in the first recess, the word line gate structure including opposing first and second side regions therein, the second side region adjoining the active region; the first isolation structure is positioned in the first groove, is adjacent to the first side region of the word line grid structure, is positioned between the word line grid structure and the active region, and is also positioned in part of the active region; a plurality of capacitor structures located on a first side of each of the active regions; the bit line structures are arranged along a first direction and are parallel to a second direction.

Optionally, the word line gate structure includes a gate dielectric layer located on the surface of the sidewall and the bottom surface of the first groove, and a gate layer located on the surface of the gate dielectric layer.

Optionally, a bottom plane of the first isolation structure in a direction towards the second side of the substrate is lower than half a height of the gate layer.

Optionally, the material of the gate layer includes polysilicon or a metal, and the metal includes tungsten.

Optionally, the gate layer includes a first subsection located at the bottom of the first groove and a second subsection located on the first subsection, and the first subsection and the second subsection are made of different materials.

Optionally, the ratio of the height of the second division to the height of the first division ranges from 1:4 to 4:1.

Optionally, the material of the first subsection comprises a metal, the metal comprises tungsten, and the material of the second subsection comprises polysilicon; a bottom plane of the first isolation structure in a direction towards the second side of the substrate is lower than a bottom plane of the second section in a direction towards the second side of the substrate.

Optionally, the material of the first subsection comprises polysilicon, the material of the second subsection comprises metal, and the metal comprises tungsten; a bottom plane of the first isolation structure in a direction towards the second side of the substrate is lower than a bottom plane of the first section in a direction towards the second side of the substrate.

Optionally, the bottom surface of the gate dielectric layer is exposed in the active region.

Optionally, the method further includes: a first doped region located on a first side of the active region; each capacitor structure is electrically connected with one first doped region.

Optionally, a projection of the capacitor structure on the first surface of the active region coincides with at least a portion of the first doped region.

Optionally, the method further includes: and the capacitor plug is positioned between the capacitor structure and the first doping region and electrically connected with the capacitor structure and the first doping region.

Optionally, the method further includes: the top surface of the word line gate structure facing the first side of the substrate is lower than the bottom surface of the first doped region facing the second side of the substrate.

Optionally, the method further includes: a second doped region located on a second side of the active region; each bit line structure is electrically connected with a second doped region in one active region respectively.

Optionally, the method further includes: a bit line plug located between the bit line structure and the second doped region, the bit line plug electrically connecting the bit line structure and the second doped region.

Optionally, a second isolation structure is arranged between adjacent active regions; the second side of the substrate exposes the second isolation structure.

Optionally, the method further includes: the first dielectric layer is positioned on the second surface of the active area and on the second isolation structure, a third groove is formed in the first dielectric layer, and the surface of the second surface of the active area is exposed by the third groove; the bit line structure is located in the third groove.

Optionally, the bit line structure includes a barrier layer on a sidewall surface and a bottom surface of the third recess, and a bit line layer on the barrier layer.

Optionally, the material of the second isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.

Optionally, the material of the first isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.

Optionally, the method further includes: a second dielectric layer located on the first isolation structure and the first surface of the active region; the capacitor structure is located in the second dielectric layer.

Optionally, the capacitor structure includes: the electrode structure comprises a first electrode layer, a second electrode layer and a dielectric layer positioned between the first electrode layer and the second electrode layer.

Optionally, the shape of the dielectric layer includes: planar or "U" shaped.

Optionally, each of the capacitor structures is located on the active region adjacent to the second side region.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

according to the semiconductor structure, on one hand, the bit line structure is located on the second surface of the substrate, and the capacitor structure is located on the first surface of the substrate, so that the difficulty and the cost of a manufacturing process are greatly simplified; on the other hand, the word line gate structure is positioned in the substrate, so that the space in the direction vertical to the surface of the substrate can be saved, and the density of the memory array unit can be improved; on the other hand, a first isolation structure is arranged between the word line gate structure and the active region, the second side region of the word line gate structure is adjacent to the active region, and the first side region of the word line gate structure is adjacent to the first isolation structure, so that the first isolation structure can isolate the first side region of the word line gate structure from the active region, the word line gate structure is prevented from being simultaneously contacted with the active regions on two adjacent sides to generate two channels to form a parasitic device, and the transistor is not easy to turn off. Thereby reducing leakage current and improving the performance of the semiconductor structure.

Further, the material of the gate layer comprises polysilicon or tungsten, and the bottom plane of the first isolation structure in the direction towards the second surface of the substrate is lower than half of the height of the gate layer, so that the channel of the first side area of the word line gate structure can be completely cut off.

Further, the gate layer comprises a first subsection and a second subsection on the first subsection, the material of the first subsection comprises metal, the metal comprises tungsten, and the material of the second subsection comprises polysilicon; a bottom plane of the first isolation structure in a direction towards the second side of the substrate is lower than a bottom plane of the second section in a direction towards the second side of the substrate. Therefore, the bottom plane of the first isolation structure is lower than that of the second subsection only, and the effect of cutting off the channel of the first side area of the word line grid electrode structure can be achieved.

Further, still include: the capacitor plug is positioned between the capacitor structure and the first doping region on the first surface of the active region, and the capacitor structure is electrically connected with the first doping region through the capacitor plug, so that the process window for forming the capacitor structure and the capacitor plug can be enlarged.

Furthermore, the bottom surface of the gate dielectric layer is exposed in the active region. . The second sides of the active regions are separated from each other so that a capacitance generated after forming the bit line structure on the second sides of the active regions is reduced.

Further, a top surface of the word line gate structure facing the first side of the substrate is lower than a bottom surface of the first doped region facing the second side of the substrate. Therefore, a channel formed in the active region by the subsequent word line gate structure cannot be overlapped with the first doped region, and the performance of the first doped region is prevented from being influenced.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure in one embodiment;

FIGS. 2-5 are schematic structural diagrams of a semiconductor structure according to an embodiment of the invention;

FIG. 6 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention;

FIG. 7 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention;

FIG. 9 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

Detailed Description

As described in the background, the existing dynamic random access memory has yet to be improved. The analysis will now be described with reference to specific examples.

FIG. 1 is a schematic diagram of a semiconductor structure according to an embodiment.

Please refer to fig. 1, which includes: a substrate 100; a word line gate structure 101 located within the substrate 100; a source doped region 103 and a drain doped region 102 in the substrate 100 at two sides of the word line gate structure 101; a bit line structure 105 electrically connected to the source doped region 103 through the source plug 104; and a capacitor structure 107 electrically connected to the drain doped region 102 through the capacitor plug 106.

The forming process of the semiconductor structure comprises the following steps: the source doping region 103 and the drain doping region 102 are formed, the word line gate structure 101 is formed in the substrate 100, the source plug 104 and the bit line structure 105 are formed, the capacitor plug 106 is formed, and the capacitor structure 107 is formed. The channel of the semiconductor structure is U-shaped, and the source doped region 103 and the drain doped region 102 are on the horizontal sides of the word line gate structure 101. The bit line structure 105 and the capacitor structure 107 are on the same side of the transistor and are located above the substrate in the fabrication process. The capacitor plug 106 of the capacitor structure 107 needs to pass through the bit line structure 105, so that the overall process complexity is high, and extremely high requirements are imposed on the photolithography process and the alignment.

In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure, wherein on one hand, the bit line structure is located on the second surface of the substrate, and the capacitor structure is located on the first surface of the substrate, thereby greatly simplifying the difficulty and cost of the manufacturing process; on the other hand, the word line gate structure is positioned in the substrate, so that the space in the direction vertical to the surface of the substrate can be saved, and the density of the memory array unit can be improved; on the other hand, a first isolation structure is arranged between the word line gate structure and the active region, the second side region of the word line gate structure is adjacent to the active region, and the first side region of the word line gate structure is adjacent to the first isolation structure, so that the first isolation structure can isolate the first side region of the word line gate structure from the active region, the word line gate structure is prevented from being simultaneously contacted with the active regions on two adjacent sides to generate two channels to form a parasitic device, and the transistor is not easy to turn off. Thereby reducing leakage current and improving the performance of the semiconductor structure.

In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.

Fig. 2 to 5 are schematic structural diagrams of a semiconductor structure according to an embodiment of the invention.

Referring to fig. 2 to 5, fig. 4 is a top view of the second side 400 of the substrate in fig. 2 and 3, fig. 5 is a top view of the first side 300 of the substrate in fig. 2 and 3, fig. 2 is a schematic cross-sectional view taken along a section line MM1 in fig. 4, fig. 3 is a schematic cross-sectional view taken along a section line NN1 in fig. 4, and the semiconductor structure includes: the substrate comprises a first face 300 and a second face 400 which are opposite to each other, the substrate comprises a plurality of mutually-separated active regions 201, the plurality of active regions 201 are arranged along a first direction X, the plurality of active regions 201 are parallel to a second direction Y, and the first direction X and the second direction Y are mutually perpendicular.

In this embodiment, the substrate is made of silicon.

In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.

In the present embodiment, a second isolation structure 202 is disposed between adjacent active regions 201, and the second isolation structure 202 is exposed at the substrate second surface 400.

The material of the second isolation structure 202 comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride.

In the present embodiment, the material of the second isolation structure 202 includes silicon oxide.

With continued reference to fig. 2 to 5, the semiconductor structure further includes: a plurality of first grooves (not shown) in the substrate, the first grooves extending from the first surface 300 to the second surface 400, the plurality of first grooves being arranged along the second direction Y, and the first grooves penetrating the plurality of active regions 201 along the first direction X; a word line gate structure located in the first recess, the word line gate structure including a first side region (not labeled) and a second side region (not labeled) opposite to each other, the second side region being adjacent to the active region 201.

The word line gate structure comprises a gate dielectric layer 208 positioned on the side wall surface and the bottom surface of the first groove and a gate layer 209 positioned on the surface of the gate dielectric layer 208. The word line gate structure is positioned in the substrate, so that the space in the direction vertical to the surface of the substrate can be saved, and the density of the memory array unit can be improved.

In the present embodiment, the material of the gate dielectric layer 208 includes silicon oxide or a low K (K is less than 3.9) material; the material of the gate layer 209 comprises polysilicon.

In another embodiment, the material of the gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material comprises aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal comprising tungsten.

In another embodiment, the word line gate structure further comprises a work function layer between the gate dielectric layer and the gate electrode layer. The material of the work function layer comprises an N-type work function material or a P-type work function material, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride.

In other embodiments, the gate layer includes a first subsection at the bottom of the first recess and a second subsection on the first subsection, and the first subsection and the second subsection are made of different materials.

With continued reference to fig. 2-5, the semiconductor structure further includes: the first isolation structure 210 is located in the first groove, the first isolation structure 210 is adjacent to the first side region of the word line gate structure, the first isolation structure 210 is located between the word line gate structure and the active region 201, and the first isolation structure 210 is also located in a part of the active region 201.

In this embodiment, the first isolation structure 210 is also located on the top surface of the word line gate structure.

The first isolation structure 210 is located between the word line gate structure and the active region 201, and the second side region of the word line gate structure is adjacent to the active region 201, so that the first isolation structure 210 can isolate the first side region of the word line gate structure from the active region 201, and prevent the word line gate structure from contacting the active regions 201 on two adjacent sides at the same time to generate two channels to form a parasitic device, so that the transistor is not easily turned off, and leakage current can be reduced.

The material of the first isolation structure 210 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride.

In the present embodiment, the material of the first isolation structure 210 includes silicon oxide.

In this embodiment, a bottom plane of the first isolation structure 210 in a direction towards the substrate second side 400 is lower than half a height of the gate layer 209. Therefore, the isolation function of the first isolation structure 210 enables the channel of the first side region of the word line gate structure to be completely turned off, and leakage current can be reduced.

With continued reference to fig. 2-5, the semiconductor structure further includes: a plurality of capacitor structures 212 located on the first side 300 of each of the active regions 201; a plurality of bitline structures 215 on the second side 400 of the substrate, the plurality of bitline structures 215 arranged along a first direction X, and the plurality of bitline structures 215 parallel to a second direction Y.

In this embodiment, the semiconductor structure further includes: a first doped region 206 located at the first side 300 of the active region 201; each of the capacitor structures 212 is electrically connected to one of the first doped regions 206.

The first doped region 206 has doped ions therein, and the type of the doped ions is N-type or P-type; the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

In the present embodiment, the top surface of the wordline gate structure facing the first side 300 of the substrate is lower than the bottom plane of the first doped region 206 facing the second side 400 of the substrate. Therefore, the channel formed in the active region 201 by the subsequent word line gate structure does not coincide with the first doped region 206, and the performance of the first doped region 206 is prevented from being affected.

Each of the capacitive structures 212 is located on the active region 201 adjacent to the second side region, and a projection of the capacitive structure 212 on the first face 300 of the active region 201 coincides with at least a portion of the first doped region 206.

The capacitor structure 212 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer.

The shape of the dielectric layer includes: planar or "U" shaped.

When the shape of the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

When the dielectric layer is in a U shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

The material of the first electrode layer includes: a metal or metal nitride; the material of the second electrode layer includes: a metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

In this embodiment, a capacitor plug 211 is further disposed between the capacitor structure 212 and the first doped region 206, and the capacitor plug 211 is electrically connected to the capacitor structure 212 and the first doped region 206.

The material of the capacitor plug 211 includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

In another embodiment, the capacitor plug can be excluded and the capacitor structure is electrically connected in direct contact with the first doped region.

In this embodiment, the semiconductor structure further includes: a second dielectric layer (not shown) on the first isolation structure 202 and on the first side of the active region 201; the capacitive structure 212 is located within the second dielectric layer.

In this embodiment, the semiconductor structure further includes: a second doped region 213 located at the second side 400 of the active region 201; each bit line structure 215 is electrically connected to the second doped region 213 in one active region 201.

The second doping region 213 has doped ions therein, and the type of the doped ions is N-type or P-type; the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

In the present embodiment, the conductivity type of the doped ions in the second doped region 213 is the same as the conductivity type of the doped ions in the first doped region 206.

In this embodiment, the semiconductor structure further includes: a first dielectric layer 214 located on the second side 400 of the active region 201 and on the second isolation structure 202, wherein a third groove (not shown) is formed in the first dielectric layer 214, and the surface of the second side 400 of the active region 201 is exposed by the third groove; the bit line structure 215 is located in the third recess.

The bit line structure 215 includes a barrier layer (not shown) on the sidewall surface and the bottom surface of the third recess, and a bit line layer (not shown) on the barrier layer.

The material of the barrier layer comprises metal nitride; the bit line layer material comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

In another embodiment, a bit line plug is further disposed between the bit line structure and the second doped region, and the bit line plug electrically connects the bit line structure and the second doped region.

In the semiconductor structure, on one hand, the capacitor structure 212 is located on the first side 300 of the substrate, and the bit line structure 215 is located on the second side 400 of the substrate, so that the difficulty and cost of the manufacturing process are greatly reduced; on the other hand, the word line gate structure is positioned in the substrate, so that the space in the direction vertical to the surface of the substrate can be saved, and the density of the memory array unit can be improved; on the other hand, the first isolation structure 210 is arranged between the word line gate structure and the active region 201, the second side region of the word line gate structure is adjacent to the active region 201, and the first side region of the word line gate structure is adjacent to the first isolation structure 210, so that the first isolation structure 210 can isolate the first side region of the word line gate structure from the active region 201, and the situation that the word line gate structure is simultaneously contacted with the active regions 201 on two adjacent sides to generate two channels to form a parasitic device is avoided, so that the transistor is not easily turned off. Thereby reducing leakage current and improving the performance of the semiconductor structure.

FIG. 6 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present invention.

Referring to fig. 6, the view direction of fig. 6 is the same as that of fig. 2, and fig. 6 is different from fig. 2 in that: the second surface 400 of the active region is exposed out of the surface of the gate dielectric layer 208.

In this embodiment, the method further includes: a fifth groove (not shown) in the active region 201 at the bottom of the word line gate structure, the fifth groove extending from the second surface 400 of the substrate to the first surface 300, the fifth groove exposing the surface of the gate dielectric layer 208, and the first isolation structure 214 being further located in the fifth groove; a plurality of second doping regions 313 are located in the second side 400 of the active region 201, the plurality of second doping regions 313 are separated from each other, and the fifth recess is located between the adjacent second doping regions 313.

The second sides 400 of the active regions 201 are separated from each other so that the capacitance generated after the bit line structures 215 are formed on the second doped regions 313 is reduced.

FIG. 7 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

The view direction of fig. 7 is the same as that of fig. 2, and fig. 7 differs from fig. 2 in that: the gate layer comprises a first subsection 405 at the bottom of the first groove and a second subsection 406 on the first subsection 405, and the first subsection 405 and the second subsection 406 are made of different materials.

In this embodiment, the material of the first subsection 405 comprises a metal, the metal comprises tungsten, and the material of the second subsection 406 comprises polysilicon.

In this embodiment, a bottom plane of the first isolation structure 410 in a direction towards the second side 400 of the substrate is lower than a bottom plane of the second section 406 in a direction towards the second side 400 of the substrate.

Thus, the bottom plane of the first isolation structure 410 is lower than the bottom plane of the second partition 406, so as to achieve the effect of turning off the channel of the first side region of the word line gate structure.

The ratio of the height of the second section 406 to the height of the first section 405 is 1:4 to 4:1. Therefore, the effects of reducing the resistance and the leakage current of the formed word line gate structure can be balanced.

FIG. 8 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention.

The view direction of fig. 8 is the same as that of fig. 2, and fig. 8 differs from fig. 2 in that: the gate layer comprises a first subsection 505 at the bottom of the first groove and a second subsection 506 on the first subsection 505, wherein the first subsection 505 and the second subsection 506 are made of different materials.

In this embodiment, the material of the first subsection 505 comprises polysilicon and the material of the second subsection 506 comprises a metal, the metal comprising tungsten.

In this embodiment, the bottom plane of the first isolation structure 510 in the direction towards the second side 400 of the substrate is lower than the bottom plane of the first subsection 505 in the direction towards the second side 400 of the substrate. Thereby ensuring that the first isolation structure 510 can completely isolate the first side region of the word line gate structure from the active region 201, and achieving the effect of turning off the channel of the first side region of the word line gate structure.

FIG. 9 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

The view direction of fig. 9 is the same as that of fig. 7, and fig. 9 differs from fig. 7 in that: the second surface 400 of the active region is exposed out of the surface of the gate dielectric layer 208.

In this embodiment, the method further includes: a fifth groove (not shown) in the active region 201 at the bottom of the word line gate structure, the fifth groove extending from the second surface 400 of the substrate to the first surface 300, the fifth groove exposing the surface of the gate dielectric layer 208, and the first isolation structure 214 being further located in the fifth groove; a plurality of second doped regions 613 located in the second side 400 of the active region 201, wherein the plurality of second doped regions 613 are separated from each other, and the fifth recess is located between adjacent second doped regions 613.

The second sides 400 of the active regions 201 are separated from each other so that the resulting capacitance is reduced after the bitline structures 215 are formed on the second doped regions 613.

The view direction of fig. 10 is the same as that of fig. 8, and fig. 10 differs from fig. 8 in that: the second surface 400 of the active region exposes the surface of the gate dielectric layer 208.

In this embodiment, the method further includes: a fifth groove (not shown) in the active region 201 at the bottom of the word line gate structure, the fifth groove extending from the second surface 400 of the substrate to the first surface 300, the fifth groove exposing the surface of the gate dielectric layer 208, the first isolation structure 214 being further located in the fifth groove; a plurality of second doped regions 713 located in the second plane 400 of the active region 201, the plurality of second doped regions 713 being separated from each other, and the fifth recess being located between adjacent second doped regions 713.

The second sides 400 of the active regions 201 are separated from each other so that the resulting capacitance is reduced after the bitline structures 215 are formed on the second doped regions 713.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

the substrate comprises a first surface and a second surface which are opposite, the substrate comprises a plurality of mutually-separated active areas, the active areas are arranged along a first direction and are parallel to a second direction, and the first direction and the second direction are mutually vertical;

a plurality of first grooves located in the substrate, the first grooves extending from a first surface to a second surface, the plurality of first grooves being arranged along a second direction, and the first grooves penetrating the plurality of active regions along the first direction;

a word line gate structure located in the first recess, the word line gate structure including opposing first and second side regions therein, the second side region adjoining the active region;

the first isolation structure is positioned in the first groove, is adjacent to the first side region of the word line grid structure, is positioned between the word line grid structure and the active region, and is also positioned in part of the active region;

a plurality of capacitor structures located on the first face of each of the active regions;

the bit line structures are arranged along a first direction and are parallel to a second direction.

2. The semiconductor structure of claim 1, wherein the wordline gate structure comprises a gate dielectric layer on the sidewall surface and the bottom surface of the first recess and a gate layer on a surface of the gate dielectric layer.

3. The semiconductor structure of claim 2, wherein a bottom plane of the first isolation structure in a direction toward the substrate second side is lower than half of the gate layer height.

4. The semiconductor structure of claim 2, wherein the material of the gate layer comprises polysilicon or a metal comprising tungsten.

5. The semiconductor structure of claim 2, wherein the gate layer includes a first subsection at a bottom of the first recess and a second subsection above the first subsection, the first and second subsections being of different materials.

6. The semiconductor structure of claim 5, wherein a ratio of a height of the second subsection to a height of the first subsection ranges from 1:4 to 4:1.

7. The semiconductor structure of claim 6, wherein a material of the first subsection comprises a metal, the metal comprises tungsten, and a material of the second subsection comprises polysilicon; a bottom plane of the first isolation structure in a direction towards the second side of the substrate is lower than a bottom plane of the second section in a direction towards the second side of the substrate.

8. The semiconductor structure of claim 6, wherein a material of the first subsection comprises polysilicon, a material of the second subsection comprises a metal, and the metal comprises tungsten; a bottom plane of the first isolation structure in a direction towards the second side of the substrate is lower than a bottom plane of the first section in a direction towards the second side of the substrate.

9. The semiconductor structure of claim 2, wherein the active region further exposes a bottom surface of the gate dielectric layer.

10. The semiconductor structure of claim 1, further comprising: a first doped region located on a first side of the active region; each capacitor structure is electrically connected with one first doped region.

11. The semiconductor structure of claim 10, wherein a projection of the capacitive structure onto the first side of the active region coincides with at least a portion of the first doped region.

12. The semiconductor structure of claim 10, further comprising: and the capacitor plug is positioned between the capacitor structure and the first doping region and electrically connected with the capacitor structure and the first doping region.

13. The semiconductor structure of claim 10, further comprising: the top surface of the word line gate structure facing the first surface of the substrate is lower than the bottom surface of the first doping region facing the second surface of the substrate.

14. The semiconductor structure of claim 1, further comprising: a second doped region located on a second side of the active region; each bit line structure is electrically connected with a second doped region in one active region respectively.

15. The semiconductor structure of claim 14, further comprising: a bit line plug located between the bit line structure and the second doped region, the bit line plug electrically connecting the bit line structure and the second doped region.

16. The semiconductor structure of claim 1, wherein there is a second isolation structure between adjacent active regions; the second side of the substrate exposes the second isolation structure.

17. The semiconductor structure of claim 16, further comprising: the first dielectric layer is positioned on the second surface of the active area and on the second isolation structure, a third groove is formed in the first dielectric layer, and the surface of the second surface of the active area is exposed by the third groove; the bit line structure is located in the third groove.

18. The semiconductor structure of claim 17, wherein the bitline structure comprises a barrier layer on a sidewall surface and a bottom surface of the third recess, and a bitline layer on the barrier layer.

19. The semiconductor structure of claim 16, wherein the material of the second isolation structure comprises a dielectric material comprising silicon oxide.

20. The semiconductor structure of claim 1, wherein the material of the first isolation structure comprises a dielectric material comprising silicon oxide.

21. The semiconductor structure of claim 1, further comprising: a second dielectric layer located on the first isolation structure and the first surface of the active region; the capacitor structure is located in the second dielectric layer.

22. The semiconductor structure of claim 1, wherein the capacitive structure comprises: the electrode structure comprises a first electrode layer, a second electrode layer and a dielectric layer positioned between the first electrode layer and the second electrode layer.

23. The semiconductor structure of claim 22, wherein the shape of the dielectric layer comprises: planar or "U" shaped.

24. The semiconductor structure of claim 1, wherein each of the capacitive structures is located on an active region adjacent to the second side region.