CN115174882B - Ramp signal module and gamma correction circuit - Google Patents
Ramp signal module and gamma correction circuit Download PDFInfo
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- CN115174882B CN115174882B CN202211088735.5A CN202211088735A CN115174882B CN 115174882 B CN115174882 B CN 115174882B CN 202211088735 A CN202211088735 A CN 202211088735A CN 115174882 B CN115174882 B CN 115174882B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/68—Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits
- H04N9/69—Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits for modifying the colour signals by gamma correction
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
- G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
Abstract
The application discloses ramp signal module and gamma correction circuit. The ramp signal module includes a plurality of stages of ramp signal generating circuits connected to a common output terminal, each stage of ramp signal generating circuit including: a first capacitor, a first end of the first capacitor is connected to the initial voltage through the first input switch, and is connected to the termination voltage through the second input switch; the first end of the second capacitor is grounded; the first branch circuit and the second branch circuit are connected in parallel between the second end of the first capacitor and the second end of the second capacitor, the clock signal received by each stage of ramp signal generating circuit is selected from one of the sequential pulse signal groups, pulses of at least two clock signals are not repeated, and the first path switch and the second path switch are alternately switched on under the control of the clock signals so as to generate ramp signals with step change from initial voltage to final voltage at the common output end. The module can simply, flexibly and accurately generate the ramp signal and has low requirement on the frequency of the clock signal.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a ramp signal module and a gamma correction circuit.
Background
With the continuous development of display technology and semiconductor technology, organic Light-Emitting diodes (OLEDs) have been widely used in the display fields of mobile phones, home appliances, automobiles, and the like. Since the human eye's perception of light intensity is nonlinear, a gamma (gamma) correction circuit needs to be disposed in the OLED driving chip to make the display gray scale and brightness meet the gamma curve requirement.
The mainstream gamma correction circuit is realized by a Digital-to-Analog Converter (DAC), which converts a Digital code into an Analog voltage signal to drive an OLED device, so as to display a gray image conforming to the linearity of human eyes. However, as the display resolution increases, the area and power consumption of the conventional resistor-string DAC structure far exceed the tolerable range of the chip size and power consumption, and therefore, a gamma correction circuit architecture suitable for high-resolution display needs to be provided, in which the single-slope DAC circuit has the advantages of small area and low power consumption, and is widely applied to a high-resolution display driving circuit.
The conventional ramp signal generation is most commonly implemented by a current steering (current steering) structure, which generates a ramp signal by controlling a current flowing through a fixed resistor, and an integration (integrating) structure, which generates a continuous ramp signal by charging a fixed capacitor with a fixed current. Both of these methods require setting an accurate current to realize an accurate ramp step, and are easily affected by process, temperature, voltage fluctuation (corner), etc., resulting in low accuracy of the gamma voltage. In addition, the conventional circuit configuration for generating the ramp signal is not suitable for a high-frequency device, and the circuit function is highly likely to fail once the input frequency of the circuit configuration is too high.
It is desirable to provide an improved ramp signal module to address the above-mentioned problems.
Disclosure of Invention
In view of the foregoing problems, it is an object of the present invention to provide a ramp signal module and a gamma correction circuit, which can simply, flexibly and accurately generate a ramp signal and can be applied to a high frequency device.
According to an aspect of the present invention, there is provided a ramp signal module including a plurality of stages of ramp signal generating circuits connected to a common output terminal, each of the stages of ramp signal generating circuits including: a first capacitor, a first end of the first capacitor is connected to an initial voltage through a first input switch and is connected to a termination voltage through a second input switch; a second capacitor, a first end of the second capacitor is grounded; and a first branch and a second branch connected in parallel between the second terminal of the first capacitor and the second terminal of the second capacitor, the first branch including a first path switch, the second branch including a second path switch and a voltage follower connected in series, wherein the ramp signal generating circuit of each stage alternately turns on the first path switch and the second path switch under control of a corresponding clock signal of the stage to generate a ramp signal having a step change from the initial voltage to the final voltage at the common output terminal, the clock signal received by the ramp signal generating circuit of each stage is selected from one of sequential pulse signal groups, and pulses of at least two of the clock signals are not repeated.
Optionally, the number of stages of the ramp signal generating circuit is M, and the frequency of the step change of the ramp signal is M times of the frequency of the clock signal.
Optionally, in each stage of the ramp signal generating circuit, in a pre-charge stage, the first input switch and the second path switch are turned on, the initial voltage charges the first capacitor, in a step signal generating stage, the second input switch and the first path switch are turned on, and the end voltage drives charges to flow between the first capacitor and the second capacitor, so that the voltage at the second end of the second capacitor is stepped, the pre-charge stage and the step signal generating stage are alternately executed, a sub-ramp signal that is stepped from the initial voltage to the end voltage is generated at the second end of the second capacitor, the sub-ramp signals generated by each stage of the ramp signal generating circuit are summarized as the ramp signal at the common output terminal, and the number of times of step change of the ramp signal is the sum of the number of times of step change of the sub-ramp signals at each stage.
Optionally, each stage of the ramp signal generating circuit further includes: and the second end of the second capacitor is connected to the initial voltage through the initialization switch, and in an initialization stage, the initialization switch, the first input switch and the second path switch are conducted, so that the voltage at all places of the circuit is initialized.
Optionally, each time the pre-charge stage and the step signal generation stage are executed, the voltage variation at the second end of the second capacitor is: Δ Vramp = (Vstart-Vend) × C1/(C1 + C2), where Δ Vramp is the variation, vstart is the voltage value of the initial voltage, vend is the voltage value of the termination voltage, C1 is the capacitance value of the first capacitor, and C2 is the capacitance value of the second capacitor.
Optionally, the number of times of executing the pre-charge stage and the step signal generation stage is N times, and the capacitance value of the first capacitor and the capacitance value of the second capacitor satisfy: C1/(C1 + C2) =1/N.
Optionally, the method further includes: the time sequence controller is used for generating a reset signal and the sequence pulse signal group, and the reset signal is used for controlling the initialization switch; and a not gate disposed in the ramp signal generating circuit of each stage, for generating an inverted clock signal of a specific duty ratio of the stage according to the corresponding clock signal of the stage, wherein the clock signal and the inverted clock signal are alternately active in the precharge stage and the step signal generating stage, so that the first path switch and the second path switch are alternately turned on.
Optionally, under the condition that the clock number and the frequency of the clock signal received by each stage of the ramp signal generating circuit are both fixed values, the slope of the ramp signal is adjusted by adjusting the initial voltage and/or the termination voltage; and/or adjusting the slope of the ramp signal by adjusting the frequency of the clock signal in the case that the initial voltage and the termination voltage are fixed values.
Optionally, when the voltage value of the initial voltage is greater than the voltage value of the termination voltage, the slope of the ramp signal is a negative number; when the voltage value of the initial voltage is smaller than that of the termination voltage, the slope of the ramp signal is a positive number; when the voltage value of the initial voltage is equal to the voltage value of the termination voltage, the slope of the ramp signal is zero.
According to another aspect of the present invention, there is provided a gamma correction circuit including: the ramp signal module as described above, providing a ramp signal; and a processing unit performing gamma correction on the display device according to the ramp signal.
The ramp signal unit step length self-adaptation that the ramp signal module of this application provided can be simple and convenient, nimble, accurately generate ramp signal to can reduce the frequency requirement to clock signal through setting up the number of ramp signal generating circuit, can be good be applied to in the high frequency circuit.
Further, when the capacitance values of the first capacitor and the second capacitor are fixed values and the voltage values of the initial voltage and the termination voltage are determined values, the slope signal module can still adjust the slope of the slope signal by controlling parameters such as the frequency of the clock signal, and therefore the slope signal module can be flexibly applied to various scenes.
Further, the gamma correction circuit has the advantage of self-adaptive step length, under fixed clock frequency, when gamma correction is carried out at every time, only initial voltage and slope terminal voltage need to be set, slope unit step length is adaptive to different terminal voltages and is adjusted automatically, slope signals with different slopes can be generated easily, complex calculation and time sequence switching are not needed, gamma curve correction can be efficiently completed, and the efficiency of chip volume production is greatly improved. The circuit design has lower requirements on the sequence, the circuit is simpler to realize, and the area and the power consumption can be obviously saved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1a shows a block circuit diagram of a ramp signal module according to a first embodiment of the present invention;
fig. 1b shows a waveform diagram of a clock signal of a ramp signal module according to a first embodiment of the invention;
fig. 2a shows a block circuit diagram of a ramp signal module according to a second embodiment of the present invention;
fig. 2b shows a waveform diagram of a clock signal of a ramp signal module according to a second embodiment of the invention;
FIG. 3 shows a circuit schematic of a ramp signal generating circuit according to an embodiment of the present invention;
fig. 4 shows an operation timing diagram of the ramp signal generating circuit according to the embodiment of the present invention;
fig. 5 shows an equivalent circuit diagram of a ramp signal generating circuit in a first stage according to an embodiment of the present invention;
fig. 6 shows an equivalent circuit diagram of the ramp signal generating circuit in the second stage according to the embodiment of the present invention;
fig. 7 shows an equivalent circuit diagram of the ramp signal generating circuit at the third stage according to the embodiment of the present invention;
fig. 8 illustrates a waveform diagram of a ramp signal according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
It should be understood that, in the embodiments of the present application, a and B are connected/coupled, which means that a and B may be connected in series or in parallel, or a and B may pass through other devices, and the embodiments of the present application do not limit this.
The term "unit step size (Δ V)" used herein refers to the minimum step voltage amplitude of the ramp signal.
The main function of the ramp signal module is to generate a ramp signal, which can be used in a circuit requiring a linear voltage change, and is generally used as a reference signal, a slope compensation signal or a scan voltage generation circuit, etc.
The ramp signal module provided by the present application can be applied to various systems, such as a display system, a communication system, a power transmission system, a detection system, etc., and more particularly, for example, in a gamma correction circuit of the display system. The display system is, for example but not limited to: a Light Emitting Diode (LED) Display system, an Organic Light Emitting Diode (OLED) Display system, a mini LED Display system, a micro OLED Display system, or the like, a Liquid Crystal Display (LCD) Display system, or the like.
The ramp signal module provided by the invention reduces the requirement on the frequency of the clock signal by arranging a plurality of cascade ramp signal generating circuits, so that the circuit can be suitable for a high-frequency circuit, and the unit step length of the ramp signal is self-adaptively adjusted according to the initial voltage and the final voltage of the ramp signal by configuring the proportion of capacitors and the conduction condition of the circuit, thereby reducing the complexity of the circuit while ensuring the precision of the ramp signal.
Embodiments of the ramp signal module and the gamma correction circuit provided in the present application will be described below with reference to the accompanying drawings.
Fig. 1a shows a block circuit diagram of a ramp signal module according to a first embodiment of the present invention; fig. 1b shows a waveform diagram of a clock signal of a ramp signal module according to a first embodiment of the present invention.
As shown in fig. 1a, the ramp signal module 10 of this embodiment includes a two-stage ramp signal generating circuit 100, wherein the circuit terminals of each stage of ramp signal generating circuit at least include an initial voltage receiving terminal vs for receiving an initial voltage Vstart, a termination voltage receiving terminal ve for receiving a termination voltage Vend, a reset signal terminal clk1, a clock signal terminal clk2 and an output terminal out, the reset signal terminal clk1 is for receiving a reset signal clk rst The clock signal terminal clk2 is used for receiving the clock signal ph1, and the output terminal out is used for providing the sub-ramp signal Vrampx.
In this embodiment, the output terminals out of the two-stage ramp signal generating circuit 100 are commonly connected to a common output terminal, and the common output terminal sums the sub-ramp signals Vramp1 and Vramp2 provided by the two-stage ramp signal generating circuit 100 to obtain the ramp signal Vramp. It should be understood that the common output terminal may be a circuit for summing voltages, or may be only a circuit terminal commonly connected to the two-stage ramp signal generating circuit 100, which is not limited in this application.
In this embodiment, the initial voltage Vstart and the end voltage Vend are the highest value and the lowest value of a preset ramp signal in a working period, the ramp signal is stepped step by step at the initial voltage Vstart and the end voltage Vend, and a user can adjust the initial voltage Vstart and the end voltage Vend according to actual needs; reset signal clk rst Should have a period corresponding to that of the ramp signalThe making periods are consistent and are effective at the starting time of each working period so as to initialize the circuit; the clock signal ph1 received by each stage of the ramp signal generating circuit 100 is selected from one of the sequential pulse signal groups, the frequency of each stage of the clock signal is the same, and the pulses of the two clock signals ph1 and ph2 are not repeated. As shown in fig. 2b, in this embodiment, the duty ratios of the two-stage clock signals ph1 and ph2 are both 1/2, and the phase difference is 180 °, which may also be called that the two-stage clock signals ph1 and ph2 are complementary; in other embodiments, if the number of stages of the ramp signal generating circuit 100 is M, the phase difference between two adjacent clock signals is 360 °/M, and the duty ratio is 1/M.
In the embodiment of the present invention, if the number of stages of the ramp signal generating circuit 100 included in the ramp signal module is M, the frequency of the clock signals of each stage is the same, and the phase difference between the clock signals of two adjacent stages is 360 °/M, the frequency of the step change of the ramp signal Vramp is M times of the frequency of the clock signals. That is, when the clock signal received by each stage of the ramp signal generating circuit 100 is not repeated, the number of steps of the ramp signal Vramp provided by the ramp signal module 10 in a unit time is the sum of the number of steps of the sub-ramp signal provided by each stage of the ramp signal generating circuit 100 in the unit time. In this embodiment, the frequency of the clock signal ph1 received by each stage of the ramp signal generating circuit 100 is the same as the frequency of the sub-ramp signal and is half of the frequency of the ramp signal provided by the ramp signal module 10.
The ramp signal module 10 shown in fig. 1a can reduce the frequency of the clock signal to 1/2 of the frequency of the conventional art, and thus is more suitable for high frequency circuits and high frequency devices. It should be understood that the present application does not limit the number of stages of the ramp signal generating circuit included in the ramp signal module, and when the frequency of the device/circuit to which the ramp signal module is applied is too high, the frequency requirement on the clock signal can be reduced by providing more stages of the ramp signal generating circuit, so that the ramp signal module can normally generate the required ramp signal.
Fig. 2a shows a block diagram of a circuit configuration of a ramp signal module according to a second embodiment of the present invention; fig. 2b shows a waveform diagram of a clock signal of a ramp signal module according to a second embodiment of the present invention.
The ramp signal module 20 shown in fig. 2a is different from the ramp signal module 10 shown in fig. 1a in that the ramp signal module 20 is provided with a four-stage ramp signal generating circuit 100, i.e., the sub-ramp signals Vramp1, vramp2, vramp3 and Vramp4 provided by the four-stage ramp signal generating circuit 100 in the ramp signal module 20 are summed to obtain the ramp signal Vramp.
As shown in fig. 2b, in this embodiment, if the number of stages of the ramp signal generating circuit 100 is 4, the phase difference between the clock signals of two adjacent stages is 90 °, and the duty ratio is 1/4. Compared with the ramp signal module 10, the ramp signal module 20 reduces the frequency requirement of the clock signal by a half, i.e., reduces the frequency of the clock signal to 1/4 of that of the conventional technology.
In the above embodiments, it should be understood that the specific form of each clock signal is only an example, the clock signals shown in fig. 1b and 2b are signals received by the first path switch or the second path switch in each stage of the ramp signal generating circuit 100, but are not necessarily signals directly received by each stage of the ramp signal generating circuit 100, for example, an external timing controller may be used to generate the clock signals of each stage of the ramp signal generating circuit 100, or a timing controller may be provided inside each stage of the ramp signal generating circuit 100 to generate the clock signals, as long as the first path switch and the second path switch in each stage of the ramp signal generating circuit 100 can receive corresponding signals to achieve the control effect. In addition, the parameters of amplitude, proportion, period, etc. of the clock signals shown in fig. 1b and 2b are only examples and should not be construed as limiting the present application.
Furthermore, it should be understood that when the hardware circuit structure of the ramp signal module is fixed, the relationship between the ramp signal and the clock signal frequency can be adjusted by deactivating a part of the ramp signal generating circuits or receiving the same clock signal by a part of the ramp signal generating circuits, for example, the ramp signal module 20 shown in fig. 2a can reduce the frequency of the clock signal to 1/3 of the frequency of the clock signal in the conventional technology, and only one ramp signal generating circuit needs to be deactivated or two ramp signal generating circuits need to receive the same clock signal.
FIG. 3 shows a circuit schematic of a ramp signal generating circuit according to an embodiment of the present invention; fig. 4 shows an operation timing diagram of the ramp signal generating circuit according to the embodiment of the present invention; fig. 5 shows an equivalent circuit diagram of a ramp signal generating circuit in a first stage according to an embodiment of the present invention; fig. 6 shows an equivalent circuit diagram of the ramp signal generating circuit in the second stage according to the embodiment of the present invention; fig. 7 shows an equivalent circuit diagram of the ramp signal generating circuit in the third stage according to the embodiment of the present invention. In fig. 3-7, the operation principle of the ramp signal generating circuit is described in detail by taking the single ramp signal generating circuit 100 included in the dual-channel ramp signal module 10 shown in fig. 1a and the clock signal shown in fig. 1b as an example, it should be understood that when the ramp signal generating circuit 100 is applied to a multi-channel ramp signal module, the duty ratio and the phase of the clock signal need to be adjusted accordingly.
As shown in fig. 3, each stage of the ramp signal generating circuit 100 in the embodiment of the present invention includes: the circuit comprises a first input end P1, a second input end P2, an initialization switch sw1, a first input switch sw3a, a second input switch sw3b, a first path switch sw2a, a second path switch sw2b, a first capacitor C1, a second capacitor C2 and an operational amplifier Opamp.
The first input terminal P1 receives an initial voltage Vstart, and the second input terminal P2 receives a termination voltage Vend. The first input terminal P1 is connected to the first end (i.e. the lower plate) of the first capacitor C1 via a first input switch sw3a, and the second input terminal P2 is connected to the first end of the first capacitor C1 via a second input switch sw3 b.
A second terminal (i.e., an upper plate) of the first capacitor C1 and a second terminal (i.e., an upper plate) of the second capacitor C2 are connected to each other via a first path switch sw2a, and a first terminal of the second capacitor C2 (i.e., a lower plate) is grounded.
The second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 are also connected to each other via a second path switch sw2b and a voltage follower. Specifically, the first input terminal P1 is connected to the positive input terminal of the operational amplifier Opamp via the initialization switch sw1, the second terminal of the second capacitor C2 is connected to the positive input terminal of the operational amplifier Opamp, the negative input terminal of the operational amplifier Opamp is directly connected to the output terminal thereof to form the voltage follower, and the output terminal of the operational amplifier Opamp is connected to the second terminal of the first capacitor C1 via the second path switch sw2 b.
The second terminal of the second capacitor C2 serves as an output terminal P3 of the ramp signal generating circuit 100 to output a ramp signal Vramp.
Under the clock control of the ramp signal generating circuit 100, the initialization switch sw1, the first input switch sw3a, the second input switch sw3b, the first path switch sw2a and the second path switch sw2b are respectively configured in different states, so that the lower plate (i.e. the first end) of the first capacitor C1 is alternately connected to a set initial voltage Vstart and a set final voltage Vend, and a step voltage is realized according to the size proportion of the first capacitor and the second capacitor by using charge sharing to generate a step ramp signal close to a full swing amplitude.
The operation process of the ramp signal generating circuit 100 can be divided into an initialization stage and a ramp signal generating stage, in the initialization stage, the lower plate of the first capacitor C1 and the upper plate of the second capacitor C2 are connected to the initial voltage Vstart of the ramp signal to be generated; in the ramp signal generating phase, the lower plate of the first capacitor C1 is alternately connected to the initial voltage Vstart and the end voltage Vend of the ramp signal to be generated, so that the level of the upper plate of the second capacitor C2 changes in a step from the initial voltage Vstart to the end voltage Vend according to the proportional relationship between the capacitance values of the first capacitor C1 and the second capacitor C2.
Specifically, the ramp signal generation phase includes a precharge phase and a step signal generation phase which are alternately performed. That is, after the initialization phase is completed, the initialization switch sw1 is turned off, and the first input switch sw3a, the second input switch sw3b, the first path switch sw2a, and the second path switch sw2b are controlled by clock signals with a period T and a duty ratio of 50%. When the first input switch sw3a and the second path switch sw2b are turned on, the second input switch sw3b and the first path switch sw2a are turned off; when the first input switch sw3a and the second path switch sw2b are turned off, the second input switch sw3b and the first path switch sw2a are turned on.
In the ramp signal generating phase, the time for each switch to remain on/off is T/2, and an exemplary clock signal for controlling the initialization switch sw1, the first input switch sw3a, the second input switch sw3b, the first path switch sw2a, and the second path switch sw2b can refer to fig. 2a. It should be understood that the frequency and duty ratio of the clock signal can be freely set according to actual needs, so that ramp signals different from those shown in fig. 6 are generated, and the parameters such as the frequency and duty ratio of the clock signal are not limited in the present application. In the ramp signal generating circuit provided by the invention, the generation of the ramp signal is not influenced by the duty ratio of the clock signal, so that the clock signal with any duty ratio can be selected, and the application range of the ramp signal generating circuit is expanded.
As one example, clock signals respectively controlling the initialization switch, the first input switch, the second input switch, the first path switch, and the second path switch are generated using a timing controller (not shown). Specifically, referring to fig. 4, the timing controller is configured to generate a reset signal sw1 that is active in an initialization stage, alternate an active clock signal sw2a/sw3b and an inverted clock signal sw2b/sw3a in a precharge stage and a step signal generation stage, and transmit the reset signal to the initialization switch, transmit the clock signal sw2a/sw3b to the second input switch and the first path switch, and transmit the inverted clock signal sw2b/sw3a to the first input switch and the second path switch.
As another example, the control reset signal sw1 (clk shown in FIG. 1 b) may also be generated by a timing controller (not shown) rst ) And clock signals sw2a/sw3b (ph 1 shown in fig. 1 b), and the clock signals sw2a/sw3b are inverted by the not gate arranged in the stage of ramp signal generating circuit to obtain inverted clock signals sw2b/sw3a.
In some embodiments, the clock signal and the inverted clock signal have a period T and a duty cycle of 1/2.
In other embodiments, when the clock number and the frequency of the clock signal are both fixed values, the slope of the ramp signal is adjusted by adjusting the initial voltage and/or the termination voltage; and/or adjusting the slope of the ramp signal by adjusting the frequency of the clock signal in the case that the initial voltage and the termination voltage are both fixed values.
The specific operation principle of the ramp signal generating circuit according to the embodiment of the present application will be described in detail with reference to fig. 4 to 7.
In a first phase t1, the initialization phase: fig. 4 shows an equivalent circuit diagram of the ramp signal generating circuit in the first stage as shown in fig. 5, in which the clock signal controls the initialization switch sw1, the first input switch sw3a, and the second path switch sw2b to be turned on, the second input switch sw3b, and the first path switch sw2a to be turned off. The initial voltage Vstart charges the ramp signal Vramp, the lower plate of the first capacitor C1, and the upper plate of the second capacitor C2 to the initial voltage Vstart, and the output voltage of the operational amplifier Opamp and the upper plate of the first capacitor C1 are also initialized to the initial voltage Vstart under the driving of the operational amplifier Opamp.
In the second phase t2, i.e. the precharge phase: compared with the first stage, the clock signal shown in fig. 4 turns off the initialization switch sw1, at this time, the clock signal controls the first input switch sw3a and the second path switch sw2b to be turned on, the second input switch sw3b, the first path switch sw2a and the initialization switch sw1 to be turned off, and an equivalent circuit diagram of the ramp signal generating circuit in the second stage is shown in fig. 6. The lower plate of the first capacitor C1 is still connected to the initial voltage Vstart, the upper plate of the second capacitor C2 is in a hold state, the hold time is T/2, and the ramp signal is Vramp (n). Calculating the amount of charge Q1 on the first capacitor C1 according to the formula Q = C U C1 = (Vramp (n) -Vstart) × C1, charge amount Q1 on the second capacitor C2 C2 = Vramp (n) × C2, the total charge amount on the first capacitor C1 and the second capacitor C2 is as shown in formula (1):
Q1= Q1 C1 + Q1 C2 =(Vramp(n)-Vstart)*C1+Vramp(n)*C2 （1）
in the third stage t3, i.e., the step signal generation stage: compared with the second stage, the clock signal shown in fig. 4 controls the initialization switch sw1 to be turned off, at this time, the clock signal controls the second input switch sw3b and the first path switch sw2a to be turned on, and the first path switch sw2a is turned onFig. 7 shows an equivalent circuit diagram of the ramp signal generating circuit in the second stage when the input switch sw3a, the second path switch sw2b and the initialization switch sw1 are turned off. The lower plate of the first capacitor C1 is connected to the end voltage Vend, the upper plate of the first capacitor C1 is electrically connected with the upper plate of the second capacitor C2, and the holding time is T/2. At this time, the charge amount Q2 on the first capacitor C1 C1 = (Vramp (n + 1) -Vend) × C1, charge amount Q2 on second capacitor C2 C2 = Vramp (n + 1) × C2, the total charge amount on the first capacitor C1 and the second capacitor C2 is as shown in equation (2):
Q2= Q2 C1 + Q2 C2 =(Vramp(n+1)-Vend)*C1+Vramp(n+1)*C2 （2）
in the fourth phase T4, i.e., the full ramp generation phase, the clock signal shown in fig. 4 is configured to repeat the second and third phases N-1 times with a fixed period T until the initialization switch sw1 is turned on again, i.e., the initialization phase is entered again, and the next ramp signal starts to be generated.
The complete ramp signal is generated from the second stage to the fourth stage, and the voltage change of each step signal is shown in formula (3):
ΔVramp=Vramp(n+1)-Vramp(n) （3）
the law of conservation of charge is known as:
Q1=Q2 （4）
combining equations (1) - (4), the voltage change Δ Vramp = (Vstart-Vend) × of each step signal can be obtained
That is, each time the precharge stage and the step signal generation stage are performed, the voltage value of the ramp signal changes by (Vstart-Vend) ×
。
Thus, the final voltage of the full ramp signal is:
Vramp(end)=Vstart-ΔVramp*N=Vstart-（Vstart-Vend）**N
if the first power is turned onThe capacitance ratio of the capacitor and the second capacitor is set to satisfy
If the value is =1/N, vramp (end) = Vend, and the finally formed ramp signal is as shown in the ramp signal waveform diagram shown in fig. 8. The capacitance value proportion and the step number N of the first capacitor and the second capacitor have a specific proportion, and the proportion is 1:1 but not limited to 1:1. it should be understood that, the ratio of the first capacitor to the second capacitor and the number N of step signals of the ramp signal can be freely set according to actual needs, so as to generate a ramp signal different from that shown in fig. 8.
Some examples of the ramp signal module of the embodiment of the present invention are described above, however, the embodiment of the present invention is not limited thereto, and there may be other extensions and modifications.
For example, the capacitance provided by the embodiment of the present application may be a lumped-parameter capacitance element, or a same or similar capacitance group is added, or may also be other equivalent elements having functions similar to the capacitance, where the equivalent structure described herein is, for example and without limitation, a microstrip line, a varactor, a conductor structure with a certain pattern, or the like, which may provide a capacitive impedance. For example, the voltage follower provided in the embodiment of the present application may be formed by an operational amplifier, or may be formed by a component such as a transistor.
For another example, the ramp signal generating circuit may be a discrete device or may be a circuit unit. In other implementations, the ramp signal generating circuit block described above may be packaged in a device.
Also, those of ordinary skill in the art will recognize that the various example structures and methods described in connection with the embodiments disclosed herein can be implemented with various configurations or adjustments, with reasonable variations on each structure or structure, but such implementations should not be considered as beyond the scope of the present application. Furthermore, it should be understood that the connection relationship between the components of the amplifier in the foregoing figures in the embodiments of the present application is an illustrative example, and does not set any limit to the embodiments of the present application.
Fig. 8 shows a waveform diagram of a ramp signal according to an embodiment of the present invention, according to an exemplary configuration. For ease of understanding, fig. 8 shows a clock signal ph11 of the conventional technique, a clock signal ph12 received by one of the ramp signal generating circuits in the ramp signal module of the first embodiment shown in fig. 1a, and a clock signal ph13 received by one of the ramp signal generating circuits in the ramp signal module of the second embodiment shown in fig. 2a.
As shown in fig. 8, the ramp signal Vramp is stepped in steps at the initial voltage Vstart and the end voltage Vend, and if the frequency of the step of the ramp signal is N, the frequency of the clock signal ph11 required in the conventional technology is N in order to realize the ramp signal Vramp, whereas the ramp signal module of the first embodiment provided in the present application is provided with a two-stage ramp signal generating circuit, so that the frequency of the clock signal ph12 is reduced to N/2, and the ramp signal module of the second embodiment provided in the present application is provided with a four-stage ramp signal generating circuit, so that the frequency of the clock signal ph12 is reduced to N/4. Therefore, the technical scheme of the application effectively reduces the frequency requirement on the clock signal and is applicable to high-frequency devices and high-frequency circuits.
In addition, the present application also provides a gamma correction circuit (not shown), which comprises a ramp signal generating circuit as shown in fig. 1a and a processing unit, wherein the processing unit uses the ramp signal provided by the ramp signal generating circuit as a gamma voltage to perform gamma correction on the display device, and the specific circuit structure of the gamma correction circuit is not limited in the present application.
Further, the present application also provides a display device including the ramp signal module or the gamma correction circuit.
The ramp signal generating circuit provided by the application has the following advantages:
1) The utility model provides an efficiency that the slope signal module can be very big improvement slope signal produces, when producing the same slope signal, required clock signal frequency is lower, therefore lower to hardware circuit's requirement, and application scope is more extensive, especially in application occasions such as the display drive of high-resolution, has solved that the clock leads to the unable normal pain point problem that produces of slope signal too fast, has very big advance.
2) The utility model provides a ramp signal produces module, at first electric capacity, under the fixed condition of second electric capacity size ratio, the initial voltage Vstart and the final voltage Vend that set up ramp signal that can be nimble, ramp signal unit step length can automatic adaptation initial voltage Vstart and final voltage Vend, ramp signal's slope can be controlled in a flexible way promptly, and the conventional art is at first electric capacity, under the fixed condition of second electric capacity size ratio, ramp signal's unit step length is fixed, the slope is fixed promptly, can't change, so this scheme ramp signal's production circuit can all be suitable for in the different circuits of slope requirement, the range of application is more extensive.
3) The utility model provides a ramp signal produces circuit, ramp signal unit step length self-adaptation, need not complicated calculation and can realize the ramp signal from initial voltage Vstart and final voltage Vend, and the step number that initial voltage Vstart and ramp signal can only be set for to traditional technology, for realizing different final voltage Vend, need combine initial voltage Vstart and unit step length to carry out complicated calculation, control step signal number just can realize, and in some applications, ramp signal step signal's number is fixed, then can only realize the step length change through increasing the different proportional capacitance of multiunit, the area and the consumption of chip have been increased undoubtedly like this, the complexity of chip has been improved, be unfavorable for the volume production of chip.
4) The ramp signal generating circuit can control the initial voltage Vstart to be smaller than the termination voltage Vend, so as to realize a positive slope ramp signal, namely a ramp signal with the ramp signal gradually increasing along with time, and also can control the initial voltage Vstart to be larger than the termination voltage Vend, so as to realize a negative slope ramp signal, namely a ramp signal with the ramp signal gradually decreasing along with time.
5) The ramp signal generating circuit has the advantages that the unit step length of the ramp signal is self-adaptive, when the capacitance values of the first capacitor and the second capacitor are fixed values and the voltage values of the initial voltage Vstart and the final voltage Vend are both determined values, the slope of the ramp signal can be adjusted by controlling the frequency, the duty ratio and other parameters of the clock signal, and therefore the ramp signal generating circuit can be flexibly applied to various scenes.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
In accordance with embodiments of the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (9)
1. A ramp signal module comprising a plurality of stages of ramp signal generating circuits connected to a common output terminal, each of said stages of ramp signal generating circuits comprising:
a first capacitor, a first end of the first capacitor is connected to an initial voltage through a first input switch and is connected to a termination voltage through a second input switch;
a second capacitor, a first end of the second capacitor is grounded; and
a first branch and a second branch connected in parallel between the second terminal of the first capacitor and the second terminal of the second capacitor, the first branch including a first path switch, the second branch including a second path switch and a voltage follower connected in series,
each stage of the ramp signal generating circuit alternately switches on the first path switch and the second path switch under the control of the corresponding clock signal of the stage, the switching-on times of the first path switch and the second path switch are respectively N times, and the capacitance value of the first capacitor and the capacitance value of the second capacitor meet the following conditions:
wherein C1 is the capacitance value of the first capacitor, C2 is the capacitance value of the second capacitor,
to generate a ramp signal at the common output that steps from the initial voltage to the final voltage,
the clock signals received by the ramp signal generating circuits of each stage are selected from one of sequential pulse signal groups, and the pulses of at least two of the clock signals are not repeated.
2. The ramp signal module according to claim 1, wherein the ramp signal generating circuit has a number of stages M, and the clock signal received by the ramp signal generating circuit at each stage is not repeated, and the ramp signal changes in steps at a frequency M times the frequency of the clock signal.
3. The ramp signal module according to claim 1, wherein in each stage of the ramp signal generating circuit, the first input switch and the second path switch are turned on and the initial voltage charges the first capacitor in a pre-charge stage,
in a step signal generation phase, the second input switch and the first path switch are turned on, and the termination voltage drives charges to flow between the first capacitor and the second capacitor, so that the voltage on the second end of the second capacitor is stepped,
alternately performing the pre-charge phase and the step signal generation phase, generating a sub-ramp signal that steps from the initial voltage to the final voltage from across the second terminal of the second capacitance,
the sub-ramp signals generated by the ramp signal generating circuits of each stage are summarized into the ramp signals on the common output end, and the number of times of step change of the ramp signals is the sum of the number of times of step change of the sub-ramp signals of each stage.
4. The ramp signal module according to claim 3, wherein each stage of the ramp signal generating circuit further comprises:
an initialization switch via which a second terminal of the second capacitor is connected to the initial voltage,
in an initialization phase, the initialization switch, the first input switch and the second path switch are turned on, thereby initializing voltages around the circuit.
5. The ramp signal module according to claim 3, wherein the voltage at the second end of the second capacitor changes by an amount of:
ΔVramp=（Vstart-Vend）* 
，
Δ Vramp is the variation, vstart is the voltage of the initial voltage, vend is the voltage of the final voltage, C1 is the capacitance of the first capacitor, and C2 is the capacitance of the second capacitor.
6. The ramp signal module according to claim 4, further comprising:
the time sequence controller is used for generating a reset signal and the sequence pulse signal group, and the reset signal is used for controlling the initialization switch; and
and the NOT gate is arranged in the ramp signal generating circuit of each stage and used for generating an inverted clock signal of the stage according to the corresponding clock signal of the stage, and the clock signal and the inverted clock are alternately effective in the pre-charging stage and the step signal generating stage, so that the first path switch and the second path switch are alternately conducted.
7. The ramp signal module according to claim 1, wherein in a case where the number of clocks and the frequency of the clock signal received by the ramp signal generating circuit of each stage are both fixed values, the slope of the ramp signal is adjusted by adjusting the initial voltage and/or the termination voltage; and/or
Adjusting the slope of the ramp signal by adjusting the frequency of the clock signal when the initial voltage and the termination voltage are fixed values.
8. The ramp signal module according to claim 1,
when the voltage value of the initial voltage is greater than that of the termination voltage, the slope of the ramp signal is negative;
when the voltage value of the initial voltage is smaller than that of the termination voltage, the slope of the ramp signal is a positive number;
when the voltage value of the initial voltage is equal to the voltage value of the termination voltage, the slope of the ramp signal is zero.
9. A gamma correction circuit, comprising:
the ramp signal module according to any one of claims 1 to 8, providing a ramp signal; and
and the processing unit is used for carrying out gamma correction on the display device according to the ramp signal.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020058487A (en) * | 2000-12-30 | 2002-07-12 | 박종섭 | Cmos image sensor |
| CN104333352A (en) * | 2014-11-19 | 2015-02-04 | 格科微电子（上海）有限公司 | Ramp signal generating circuit and image sensor |
| CN204156831U (en) * | 2014-11-19 | 2015-02-11 | 格科微电子（上海）有限公司 | Ramp generator and imageing sensor |
| CN112446183A (en) * | 2019-08-15 | 2021-03-05 | 天津大学青岛海洋技术研究院 | Two-step single slope analog-to-digital converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2012019411A (en) * | 2010-07-08 | 2012-01-26 | Toshiba Corp | Solid-state imaging device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020058487A (en) * | 2000-12-30 | 2002-07-12 | 박종섭 | Cmos image sensor |
| CN104333352A (en) * | 2014-11-19 | 2015-02-04 | 格科微电子（上海）有限公司 | Ramp signal generating circuit and image sensor |
| CN204156831U (en) * | 2014-11-19 | 2015-02-11 | 格科微电子（上海）有限公司 | Ramp generator and imageing sensor |
| CN112446183A (en) * | 2019-08-15 | 2021-03-05 | 天津大学青岛海洋技术研究院 | Two-step single slope analog-to-digital converter |
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