CN115314694B - Ramp signal generating circuit and gamma correction circuit - Google Patents
Ramp signal generating circuit and gamma correction circuit Download PDFInfo
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- CN115314694B CN115314694B CN202211231526.1A CN202211231526A CN115314694B CN 115314694 B CN115314694 B CN 115314694B CN 202211231526 A CN202211231526 A CN 202211231526A CN 115314694 B CN115314694 B CN 115314694B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/68—Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits
- H04N9/69—Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits for modifying the colour signals by gamma correction
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
- H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
- H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
- H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
- G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
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Abstract
The application discloses ramp signal generating circuit and gamma correction circuit. The ramp signal generating circuit includes: a first capacitor, a first end of which is charged by an initial voltage; the first end of the second capacitor is connected to the termination voltage through the first switch, and a second switch is arranged between the first end of the first capacitor and the first end of the second capacitor; and an output terminal connected between the first terminal of the first capacitor and the second switch, wherein the first switch and the second switch are alternately turned on to generate a ramp signal at the output terminal, the ramp signal having a step change from an initial voltage to a final voltage. The circuit can accurately generate a ramp signal of a non-fixed slope based on a simple hardware circuit structure and facilitates control of parameters of the ramp signal.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a ramp signal generating circuit and a gamma correction circuit.
Background
With the continuous development of display technology and semiconductor technology, organic Light-Emitting diodes (OLEDs) have been widely used in the display fields of mobile phones, home appliances, automobiles, and the like. Since the human eye's perception of light intensity is nonlinear, a gamma (gamma) correction circuit needs to be disposed in the OLED driving chip to make the display gray scale and brightness meet the gamma curve requirement.
The conventional gamma correction circuit is implemented by a Digital-to-Analog Converter (DAC), which converts a Digital code into an Analog voltage signal for driving an OLED device to display a gray image conforming to the linearity of human eyes. However, as the display resolution increases, the area and power consumption of the conventional resistor-string DAC structure far exceed the tolerable range of the chip size and power consumption, and therefore, a gamma correction circuit architecture suitable for high-resolution display needs to be provided, in which the single-slope DAC circuit has the advantages of small area and low power consumption, and is widely applied to a high-resolution display driving circuit.
However, in some OLED driving chip applications, the voltage amplitude of the single-slope digital-to-analog conversion circuit is very large, so that when the OLED driving chip is applied with a high resolution, the slope of the single-slope digital-to-analog conversion is very large, the wave deformation is very steep, the gamma curve suitable for human eyes cannot be accurately adjusted, and the display effect is very poor.
It is desirable to provide an improved ramp signal generating circuit to solve the above problems.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a ramp signal generating circuit and a gamma correction circuit for accurately generating a ramp signal having a non-constant slope based on a simple hardware circuit configuration.
According to an aspect of the present invention, there is provided a ramp signal generating circuit including: a first capacitor, a first end of the first capacitor being charged by an initial voltage; a second capacitor, a first end of the second capacitor is connected to a termination voltage via a first switch, and a second switch is arranged between the first end of the first capacitor and the first end of the second capacitor; and an output terminal connected between the first terminal of the first capacitor and the second switch, wherein the first switch and the second switch are alternately turned on to generate a ramp signal at the output terminal, which is stepped from the initial voltage to the final voltage.
Optionally, in the ramp signal generation period, the step size of the ramp signal gradually decreases with the increase of the number of steps, and at the end of the ramp signal generation period, the voltage value of the ramp signal approaches the voltage value of the termination voltage.
Optionally, the step size of the ramp signal satisfies:
where Δ Vramp is a step size of the ramp signal, vstart is a voltage value of the initial voltage, vend is a voltage value of the end voltage, m is a ratio of capacitance values of the first capacitor and the second capacitor, and n is a stepped occurrenceThe number of times.
Optionally, the step size of the ramp signal is adjusted by setting a ratio of capacitance values of the first capacitor and the second capacitor.
Optionally, the method further includes: and the initialization switch is connected between the first end of the first capacitor and the initial voltage, and in an initialization stage at the beginning of each ramp signal generation period, the initialization switch and the second switch are turned on to charge the first capacitor and the second capacitor, so that circuit initialization is completed.
Optionally, the method further includes: and a timing controller for generating a first clock signal and a second clock signal which are complementary to each other to control the first switch and the second switch, respectively, wherein the first switch is turned on and the second switch is turned off during a pre-charge period, the termination voltage charges the second capacitor, the first switch is turned off and the second switch is turned on during a step generation period, and charges flow between the first capacitor and the second capacitor to form a step change of the ramp signal, and the pre-charge period and the step generation period are alternately performed to generate the ramp signal.
Optionally, the parameters of the ramp signal are adjusted by adjusting at least one of the initial voltage, the termination voltage, the first clock signal and the second clock signal, wherein, when the number and frequency of pulses of the first clock signal and the second clock signal are fixed values, the step length of the step of the ramp signal is adjusted by adjusting the initial voltage and/or the termination voltage; and/or under the condition that the initial voltage and the termination voltage are fixed values, adjusting the step length of the step of the ramp signal by adjusting the frequency of the clock signal and the frequency of the second clock signal; and/or adjusting the number of the steps of the ramp signal by adjusting the number of pulses of the clock signal and the second clock signal when the initial voltage and the termination voltage are fixed values.
Optionally, when the pre-charge phase and the step generation phase are alternately performed, the duty ratios of the first clock signal and the second clock signal are both 1/2.
Optionally, when the voltage value of the initial voltage is greater than the voltage value of the termination voltage, the slope of the ramp signal is a negative number; when the voltage value of the initial voltage is smaller than that of the termination voltage, the slope of the ramp signal is a positive number; when the voltage value of the initial voltage is equal to the voltage value of the termination voltage, the slope of the ramp signal is zero.
According to another aspect of the present invention, there is provided a gamma correction circuit including: the ramp generating circuit as described above, which provides a ramp signal; and a processing unit performing gamma correction on the display device according to the ramp signal.
According to the ramp signal generation circuit and the gamma correction circuit, the conducting states of the first switch and the second switch are adjusted, the charge flow between the first capacitor and the second capacitor is utilized, the step change nonlinear ramp signal is generated, the precision and the stability of the ramp signal are considered, the design difficulty of the circuit is reduced, and the hardware cost and the occupied area are saved.
In addition, the embodiment of the invention can generate a parabolic ramp signal, is very suitable for generating a gamma curve, is applied to a high-brightness OLED driving circuit, and solves the problem that low gray scale cannot be normally generated. That is, the slope of the ramp signal is high at high luminance, the amplitude of change of each gray-scale voltage is large, and the accuracy is low, and the slope of the ramp signal is low at low gray-scale, the amplitude of change of each gray-scale voltage is small, and the accuracy is high.
Furthermore, under the condition that the size ratio of the first capacitor to the second capacitor is fixed, parameters of initial voltage, final voltage, a first clock signal and a second clock signal can be set, the unit step length of the ramp signal can automatically adapt to the initial voltage and the final voltage, namely, the parameters of the slope, the step length, the step number and the like of the ramp signal can be flexibly controlled, and the method can be flexibly applied to various scenes.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a circuit schematic of a ramp signal generating circuit according to an embodiment of the present invention;
fig. 2 shows an operation timing diagram of a ramp signal generating circuit according to an embodiment of the present invention;
fig. 3 shows an equivalent circuit diagram of a ramp signal generating circuit in an initialization stage according to an embodiment of the present invention;
fig. 4 shows an equivalent circuit diagram of a ramp signal generating circuit in a precharge phase according to an embodiment of the present invention;
fig. 5 shows an equivalent circuit diagram of the ramp signal generating circuit in the step generation phase according to the embodiment of the present invention;
fig. 6a and 6b show waveform diagrams of ramp signals according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For purposes of clarity, the various features in the drawings are not drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
It should be understood that, in the embodiments of the present application, a and B are connected/coupled, which means that a and B may be connected in series or in parallel, or a and B may pass through other devices, and the embodiments of the present application do not limit this.
The term "step size" (Δ Vramp) as used herein refers to the amount of voltage change in the ramp signal that occurs in one step; the term "slope" may refer to a slope of a line formed by connecting the start points of each step of the ramp signal.
The main function of the ramp signal generating circuit is to generate a ramp signal, which can be used in a circuit requiring a linear voltage change, and is generally used as a reference signal, a slope compensation signal or in a scan voltage generating circuit, etc.
The ramp signal generating circuit provided by the present application can be applied to various systems, such as a display system, a communication system, a power transmission system, a detection system, etc., and more particularly, for example, in a gamma correction circuit of a display system. The display system is, for example but not limited to: a Light Emitting Diode (LED) Display system, an Organic Light Emitting Diode (OLED) Display system, a mini LED Display system, a micro OLED Display system, or the like, a Liquid Crystal Display (LCD) Display system, or the like.
The ramp signal generating circuit provided by the invention realizes the self-adaptive adjustment of unit step length of the ramp signal according to the initial voltage and the termination voltage of the ramp signal by configuring the proportion of the capacitor and the conduction state of the circuit, and generates the ramp signal with a non-fixed slope, thereby reducing the complexity of the circuit while ensuring the precision of the ramp signal.
Embodiments of the ramp signal generating circuit and the gamma correction circuit provided in the present application will be described below with reference to the accompanying drawings.
Fig. 1 shows a circuit schematic of a ramp signal generating circuit according to an embodiment of the present invention.
As shown in fig. 1, the ramp signal generating circuit 100 includes: the first input terminal P1, the second input terminal P2, the initialization switch SW1, the first switch SW2a, the second switch SW2b, the first capacitor C1, the second capacitor C2 and the output terminal P3.
The first input terminal P1 receives an initial voltage Vstart, and the second input terminal P2 receives a termination voltage Vend. The first input terminal P1 is connected to a first terminal (i.e., an upper plate) of the first capacitor C1 via the initialization switch SW1, and the second input terminal P2 is connected to a first terminal (i.e., an upper plate) of the second capacitor C2 via the first switch SW2 a. The upper plate of the first capacitor C1 and the upper plate of the second capacitor C2 are connected to each other via a second switch SW2b, and the output terminal P3 is connected between the upper plate of the first capacitor C1 and the second switch SW2b. The second terminal (i.e., the lower plate) of the first capacitor C1 and the second terminal (i.e., the lower plate) of the second capacitor C2 are both connected to a ground reference potential.
Under the clock control of the ramp signal generating circuit 100, the initialization switch SW1, the first switch SW2a, and the second switch SW2b are configured to be in corresponding states in each stage, so that charge flows between the first capacitor C1 and the second capacitor C2, and a step-change ramp signal Vramp is generated.
In a period of generating a ramp signal, the working process of the ramp signal generating circuit 100 may be divided into an initialization stage and a ramp signal generating stage, in the initialization stage, the initialization switch SW1 and the second switch SW2b are turned on, and the upper plate of the first capacitor C1 and the upper plate of the second capacitor C2 are connected to an initial voltage Vstart of the ramp signal to be generated, so as to charge the first capacitor C1 and the second capacitor C2, thereby completing the circuit initialization, where the voltage value of the ramp signal is the voltage value of the initial voltage Vstart; in the ramp signal generation phase, the upper plate of the second capacitor C2 is alternately connected to the upper plate of the first capacitor C1 and the termination voltage Vend of the ramp signal to be generated, the first capacitor C1 and the second capacitor C2 generate a stepped ramp signal based on the principle of charge sharing, that is, the level of the ramp signal at the output terminal P3 is stepped from the initial voltage Vstart to the termination voltage Vend according to the proportional relationship and the step number between the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2, and the step size of the step change of the ramp signal gradually decreases with the increase of the step number, and at the end of the period, the voltage value of the ramp signal approaches the voltage value of the termination voltage Vend.
Specifically, the ramp signal generation phase includes a precharge phase and a step generation phase which are alternately performed. That is, after the initialization phase is completed, the initialization switch SW1 is turned off, and the first switch SW2a and the second switch SW2b are controlled by complementary first and second clock signals, for example, complementary clock signals with a period T and a duty ratio of 50%. The first switch SW2a and the second switch SW2b are alternately turned on, that is, when the first switch SW2a is turned on, the second switch SW2b is turned off; when the first switch SW2a is turned off, the second switch SW2b is turned on.
In the ramp signal generation phase, the respective switches are maintained on/off for a time period T/2, and an exemplary clock signal for controlling the initialization switch SW1, the first switch SW2a and the second switch SW2b can refer to fig. 2. It should be understood that the frequency and the duty ratio of the clock signal can be freely set according to actual needs, so that ramp signals different from those shown in fig. 6a and 6b are generated, and the frequency, the duty ratio and other parameters of the clock signal are not limited in the present application. In the ramp signal generating circuit provided by the invention, the generation of the ramp signal is not influenced by the duty ratio of the clock signal, so that the clock signal with any duty ratio can be selected, and the application range of the ramp signal generating circuit is expanded.
Alternatively, a timing controller (not shown) is used to generate clock signals that respectively control the initialization switch SW1, the first switch SW2a, and the second switch SW2b. Specifically, referring to fig. 2, the timing controller is configured to generate a reset signal SW1 that is active in an initialization phase, alternate between a first clock signal SW2a and a second clock signal SW2b that are active in a precharge phase and a step generation phase, and transmit the reset signal SW1 to the initialization switch SW1, the first clock signal SW2a to the first switch SW2a, and the second clock signal SW2b to the second switch SW2b.
In the embodiment of the present invention, before the ramp signal generating circuit leaves the factory, the step size of the ramp signal can be adjusted by setting the ratio of the capacitance values of the first capacitor and the second capacitor, so as to adapt to the actual requirements of the customer. After the ramp signal generating circuit leaves the factory, the parameters of the ramp signal may be adjusted by adjusting at least one of the initial voltage, the termination voltage, the first clock signal, and the second clock signal. For example, when the number and frequency of pulses of the first clock signal and the second clock signal are fixed values, the step length of the ramp signal is adjusted by adjusting the initial voltage and/or the termination voltage; under the condition that the initial voltage and the termination voltage are fixed values, the step length of the step of the ramp signal is adjusted by adjusting the frequency of the clock signal and the frequency of the second clock signal; when the initial voltage and the final voltage are fixed values, the number of the ramp signal generation steps is adjusted by adjusting the number of pulses of the clock signal and the second clock signal.
In the embodiment of the invention, when the voltage value of the initial voltage is greater than that of the termination voltage, the slope of the ramp signal is a negative number; when the voltage value of the initial voltage is smaller than that of the termination voltage, the slope of the ramp signal is a positive number; when the voltage value of the initial voltage is equal to the voltage value of the termination voltage, the slope of the ramp signal is zero.
The ramp signal generating circuit has the advantage of self-adaptive step length, only initial voltage and final voltage need to be set, the step voltage of the ramp signal adapts to corresponding initial voltage and final voltage for automatic adjustment, the accurate ramp signal can be efficiently provided without complex calculation and time sequence switching, and the efficiency of chip mass production is improved. The circuit design has lower requirements on time sequences, does not need operational amplifier, is simpler to realize, and can obviously save area and power consumption.
Furthermore, the ramp signal generated by the ramp signal generating circuit has a non-fixed slope, and can provide a ramp signal with a larger relative slope (i.e. a longer step length) in a high gray scale and provide a ramp signal with a smaller relative slope (i.e. a smaller step length) in a low gray scale, so that a gamma curve generated by using the ramp signal is more friendly to human eyes.
Some examples of the ramp signal generating circuit of the embodiment of the present invention have been described above, but the embodiment of the present invention is not limited thereto, and there may be extensions and modifications in other ways.
For example, it should be understood that the reference ground potential in the foregoing embodiments may be replaced in alternative embodiments with other non-zero reference potentials (having positive or negative voltage magnitudes) or controlled varying reference signals.
For another example, the capacitor provided in the embodiments of the present application may be a lumped-parameter capacitor element, or a same or similar capacitor group is added, or may also be other equivalent elements having functions similar to the capacitor, where the equivalent structure is, for example and without limitation, a microstrip line, a varactor, a conductor structure with a certain pattern, or the like, which can provide a capacitive impedance. For example, the voltage follower provided in the embodiments of the present application may be formed by an operational amplifier, or may be formed by a device such as a transistor.
For another example, the ramp signal generating circuit may be a discrete device, or may be a circuit unit. In other implementations, the aforementioned ramp signal generating circuit may be packaged in a device.
Also, those of ordinary skill in the art will recognize that the various example structures and methods described in connection with the embodiments disclosed herein can be implemented with various configurations or adjustments, with reasonable variations on each structure or structure, but such implementations should not be considered as beyond the scope of the present application. Furthermore, it should be understood that the connection relationship between the various components of the amplifier in the foregoing figures in this application embodiment is an illustrative example, and does not set any limit to this application embodiment.
In addition, the present application also provides a gamma correction circuit (not shown), which includes a ramp signal generating circuit as shown in fig. 1 and a processing unit, wherein the processing unit uses the ramp signal provided by the ramp signal generating circuit as a gamma voltage to perform gamma correction on the display device, and the present application does not limit the specific circuit structure of the gamma correction circuit.
The following describes in detail a specific operation principle of the ramp signal generating circuit according to the embodiment of the present application with reference to fig. 2 to 5. Fig. 2 shows an operation timing diagram of the ramp signal generating circuit according to an embodiment of the present invention, based on an exemplary configuration. Fig. 3 shows an equivalent circuit diagram of the ramp signal generating circuit in the first stage according to the embodiment of the present invention. Fig. 4 shows an equivalent circuit diagram of the ramp signal generating circuit in the second stage according to the embodiment of the present invention. Fig. 5 shows an equivalent circuit diagram of the ramp signal generating circuit in the third stage according to the embodiment of the present invention.
As shown in fig. 2, a ramp signal generation cycle includes an initialization phase T1 and a ramp signal generation phase T2, which generates a parabolic ramp signal.
In the initialization stage T1, the reset signal SW1 shown in fig. 2 is asserted, the first clock signal SW2a is deasserted, and the second clock signal SW2b is asserted, so as to control the initialization switch SW1 and the second switch SW2b in the ramp signal generating circuit 100 shown in fig. 1 to be turned on and the first switch SW2a to be turned off, respectively, and an equivalent circuit diagram of the ramp signal generating circuit in the initialization stage is shown in fig. 3. In this stage, the initial voltage Vstart charges the upper plates of the first capacitor C1 and the second capacitor C2 to the initial voltage Vstart, and the voltage value of the ramp signal Vramp corresponds to the voltage value of the initial voltage Vstart.
In the ramp signal generation phase T2, the precharge phase T1 and the step generation phase T2 are alternately performed to generate a stepped ramp signal. In the ramp signal generation phase T2, the reset signal sw1 remains inactive, and the first clock signal sw2a and the second clock signal sw2b are alternately active. In this example, the periods of the first clock signal sw2a and the second clock signal sw2b are both T, and the duty ratio is 50%.
In the precharge phase t1, the reset signal SW1 shown in fig. 2 is inactive, the first clock signal SW2a is active, and the second clock signal SW2b is inactive, so that the initialization switch SW1 and the second switch SW2b in the ramp signal generating circuit 100 shown in fig. 1 are controlled to be off, the first switch SW2a is controlled to be on, respectively, an equivalent circuit diagram of the ramp signal generating circuit in the initialization phase is shown in fig. 4, and an "x" in the equivalent circuit diagram shown in fig. 4 indicates that the circuit is off. In this stage, the upper plate of the second capacitor C2 is connected to the predetermined end voltage Vend, the upper plate of the second capacitor C2 is in the hold state, and the hold time is T/2. Assuming that the voltage value of the ramp signal is Vramp (n), and n is the number of steps of the ramp signal, the amount of charge on the first capacitor C1 is Q1 C1 = Vramp (n) × C1, wherein, Q1 C1 The charge amount of the first capacitor C1 in the pre-charge stage, C1 is the capacitance value of the first capacitor C1, and Vramp (n) is the voltage value of the ramp signal; the amount of charge on the second capacitor C2 is Q1 C2 (= Vend) C2, wherein, Q1 C2 Vend is the voltage value of the end voltage Vend, and C2 is the capacitance value of the second capacitor C2. Thus, in this phase, the total charge of the upper plate of the first capacitor C1 and the upper plate of the second capacitor C2 is Q1= Q1 C1 + Q1 C2 =Vramp(n)*C1+Vend*C2。
In the step generation phase t2, the reset signal shown in FIG. 2SW1 is inactive, the first clock signal SW2a is inactive, and the second clock signal SW2b is active, so as to control the initialization switch SW1 and the first switch SW2a to be turned off and the second switch SW2b to be turned on respectively in the ramp signal generating circuit 100 shown in fig. 1, an equivalent circuit diagram of the ramp signal generating circuit in the initialization stage is shown in fig. 5, and "x" in the equivalent circuit diagram shown in fig. 5 indicates that the circuit is turned off. In this phase, the upper plate of the first capacitor C1 and the upper plate of the second capacitor C2 are now connected to each other for a holding time T/2. Compared to the precharge phase t1, the number of steps of the ramp signal in the step generation phase t2 is n +1, the voltage value of the ramp signal becomes Vramp (n + 1), and similarly, in this phase, the total charge of the upper plate of the first capacitor C1 and the upper plate of the second capacitor C2 is Q2= Q2 C1 + Q2 C2 =Vramp(n+1)*C1+Vramp(n+1)*C2。
In the ramp signal generating phase T2, the pre-charge phase T1 and the step generating phase T2 are alternately performed N times with a fixed period T until the initialization switch SW1 is closed again, that is, the initialization phase is entered, and a complete ramp signal is generated.
For each execution of the pre-charging phase t1 and the step generation phase t2, the ramp signal is stepped once, and Δ Vramp (n) = Vramp (n + 1) -Vramp (n) assuming that the voltage change (i.e., step size) of the adjacent step of the ramp signal is Δ Vramp (n), and Q1= Q2 according to the law of conservation of charge, so Δ Vramp (n) = (Vend-Vramp (n)) × C2/(C1 + C2), assuming that the capacitance values of the first capacitor C1 and the second capacitor C2 satisfy C1= mC2 (m 1= mC 2) (m 2)>1) The results of the above-mentioned experiments are deduced,
where Δ Vramp is a step size of the ramp signal, vstart is a voltage value of the initial voltage, vend is a voltage value of the end voltage, m is a ratio of capacitance values of the first capacitor and the second capacitor, and n is a number of steps.
As can be seen from the Δ Vramp equation, as the number of steps n increases, the step voltage decreases, and finally a parabolic ramp signal is generated, and the final voltage value of the parabolic ramp signal is: vramp (end) = Vstart + Δ Vramp (1) + Δ Vramp (2) + ⋯ + Δ Vramp (n) = Vstart+(Vend-Vstart)* 
. As can be seen from the formula, when n is sufficiently large,
approximately 0, the final voltage value of the ramp signal is Vramp (end) = Vstart + (Vend-Vstart) = Vend.
Fig. 6a and 6b respectively show waveforms of ramp signals according to an embodiment of the present invention, based on an exemplary configuration.
As shown in fig. 6a, in this embodiment, the voltage value of the termination voltage Vend is set to be greater than the voltage value of the initial voltage Vstart, a parabolic ramp signal Vramp with a positive slope is generated, and the step Δ Vramp of the ramp signal Vramp gradually decreases as the number of steps increases. At the end of a ramp signal generation period, the voltage value of the ramp signal Vramp approaches the voltage value of the termination voltage Vend.
As shown in fig. 6b, in this embodiment, the voltage value of the termination voltage Vend is set to be smaller than the voltage value of the initial voltage Vstart, so that a parabolic ramp signal Vramp with a negative slope is generated, and the step Δ Vramp of the ramp signal Vramp gradually decreases as the number of steps increases. At the end of a ramp signal generation period, the voltage value of the ramp signal Vramp approaches the voltage value of the termination voltage Vend.
In fig. 6a and 6b, if the period of the first clock signal and the second clock signal is T, the ramp signal is stepped once every time T, and if the number of pulses of the first clock signal or the second clock signal is M in one ramp signal generation period, the number of times of stepping of the ramp signal is M.
As can be seen from fig. 6a and 6b, the ramp signal generating circuit according to the embodiment of the present invention generates a ramp signal with a non-fixed slope, and provides a ramp signal with a larger relative slope (i.e., a longer step size) in the high gray scale and a ramp signal with a smaller relative slope (i.e., a smaller step size) in the low gray scale, so that the gamma curve generated by using the ramp signal is more friendly to human eyes.
In summary, the embodiments of the present invention provide a ramp signal generating circuit and a gamma correction circuit, which can flexibly set the initial voltage and the end voltage of a ramp signal under the condition that the size ratio of a first capacitor to a second capacitor is fixed, the step length of the ramp signal can automatically adapt to the initial voltage and the end voltage, the parabolic ramp signal from the initial voltage and the end voltage can be implemented without complex calculation, the area, the power consumption and the complexity of a chip are effectively reduced, and the mass production of the chip is facilitated.
In addition, the embodiment of the invention can generate a parabolic ramp signal, is very suitable for generating a gamma curve, is applied to a high-brightness OLED driving circuit, and solves the problem that low gray scale cannot be normally generated. That is, the slope of the ramp signal is high at high luminance, the change width of each gray-scale voltage is large, and the accuracy is low, and the slope of the ramp signal is low at low gray-scale, the change width of each gray-scale voltage is small, and the accuracy is high.
In an optional embodiment, the ramp signal generating circuit provided in the embodiment of the present invention may implement a positive slope ramp signal by controlling the initial voltage to be smaller than the termination voltage, that is, a ramp signal in which the ramp signal gradually increases with time, or may implement a negative slope ramp signal by controlling the initial voltage to be larger than the termination voltage, that is, a ramp signal in which the ramp signal gradually decreases with time.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A ramp signal generating circuit, comprising:
a first capacitor, a first end of the first capacitor is connected to an initial voltage via an initialization switch;
a second capacitor, a first end of the second capacitor is connected to a termination voltage via a first switch, and a second switch is arranged between the first end of the first capacitor and the first end of the second capacitor; and
an output terminal connected between a first terminal of the first capacitor and the second switch,
wherein, in an initialization phase, the initial voltage charges the first capacitor and the second capacitor,
during a pre-charge phase, the first switch is turned on, the second switch is turned off, the termination voltage charges the second capacitor,
during a step generation phase, the first switch is turned off, the second switch is turned on, and charge flows between the first capacitor and the second capacitor,
alternately performing the precharge phase and the step generation phase to generate a ramp signal at the output terminal with a non-fixed slope that steps from the initial voltage to the final voltage.
2. The ramp signal generating circuit according to claim 1, wherein the step size of the ramp signal gradually becomes smaller as the number of steps increases during a ramp signal generating period, and the voltage value of the ramp signal approaches the voltage value of the termination voltage at the end of the ramp signal generating period.
3. The ramp signal generating circuit according to claim 1 or 2, wherein the step size of the ramp signal satisfies:
wherein Δ Vramp is a step size of the ramp signal, vstart is a voltage value of the initial voltage, vend is a voltage value of the termination voltage, m is a ratio of capacitance values of the first capacitor and the second capacitor, and m >1,n is a number of steps occurring.
4. The ramp signal generating circuit according to claim 3, wherein the step size of the ramp signal is adjusted by setting a ratio of capacitance values of the first capacitance and the second capacitance.
5. The ramp signal generating circuit according to claim 1, wherein the initialization switch is connected between the first terminal of the first capacitor and the initial voltage,
in an initialization phase at the beginning of each ramp signal generation period, the initialization switch and the second switch are turned on to charge the first capacitor and the second capacitor, thereby completing circuit initialization.
6. The ramp signal generating circuit according to claim 1, further comprising: and a timing controller generating complementary first and second clock signals to control the first and second switches, respectively.
7. The ramp signal generating circuit according to claim 6, wherein a parameter of the ramp signal is adjusted by adjusting at least one of the initial voltage, the termination voltage, the first clock signal, and the second clock signal,
under the condition that the pulse number and the frequency of the first clock signal and the second clock signal are fixed values, adjusting the step length of the step of the ramp signal by adjusting the initial voltage and/or the termination voltage; and/or
Under the condition that the initial voltage and the termination voltage are fixed values, adjusting the step length of the step of the ramp signal by adjusting the frequency of the first clock signal and the second clock signal; and/or
And under the condition that the initial voltage and the termination voltage are fixed values, adjusting the number of the steps of the ramp signal by adjusting the number of pulses of the first clock signal and the second clock signal.
8. The ramp signal generating circuit according to claim 6, wherein the duty ratios of the first clock signal and the second clock signal are each 1/2 when the precharge phase and the step generation phase are alternately performed.
9. The ramp signal generating circuit according to claim 6, wherein the slope of the ramp signal is negative when the voltage value of the initial voltage is greater than the voltage value of the termination voltage;
when the voltage value of the initial voltage is smaller than that of the termination voltage, the slope of the ramp signal is a positive number;
when the voltage value of the initial voltage is equal to the voltage value of the termination voltage, the slope of the ramp signal is zero.
10. A gamma correction circuit, comprising:
the ramp signal generating circuit according to any of claims 1 to 9, providing a ramp signal; and
and the processing unit is used for carrying out gamma correction on the display device according to the ramp signal.
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