CN116168643A

CN116168643A - Ramp signal generating circuit and gamma correction circuit

Info

Publication number: CN116168643A
Application number: CN202111412852.8A
Authority: CN
Inventors: 刘建; 孙丽娜
Original assignee: Tianyi Microelectronics Beijing Co ltd
Current assignee: Tianyi Microelectronics Beijing Co ltd
Priority date: 2021-11-25
Filing date: 2021-11-25
Publication date: 2023-05-26

Abstract

The application discloses a ramp signal generating circuit and a gamma correction circuit. The ramp signal generating circuit includes: a first end of the first capacitor is connected to the initial voltage through a first input switch and is connected to the final voltage through a second input switch; the first end of the second capacitor is grounded; and a first branch and a second branch connected in parallel between the second end of the first capacitor and the second end of the second capacitor, the first branch including a first path switch, the second branch including a second path switch and a voltage follower connected in series, wherein, during the precharge phase, the first input switch and the second path switch are turned on, and during the step signal generation phase, the second input switch and the first path switch are turned on to step the voltage on the second end of the second capacitor, the precharge phase and the step signal generation phase are alternately performed, and a ramp signal is generated from an initial voltage to a termination voltage step change on the second end of the second capacitor.

Description

Ramp signal generating circuit and gamma correction circuit

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a ramp signal generating circuit and a gamma correction circuit.

Background

With the continuous development of display technology and semiconductor technology, organic Light-Emitting diodes (OLEDs) have been widely used in the display fields of mobile phones, home appliances, automobiles, and the like. Because human eyes are nonlinear to the perception of light intensity, a gamma correction circuit is required to be arranged in the OLED driving chip, so that the display gray scale and the brightness meet the requirement of a gamma curve.

The main gamma correction circuit is implemented by a resistor string Digital-to-Analog Converter (DAC), which converts a Digital code into an Analog voltage signal for driving an OLED device, and displays a gray image conforming to the linearity of human eyes. However, with the increase of display resolution, the area and power consumption of the conventional resistor-string DAC structure far exceeds the tolerable range of chip size and power consumption, so that a gamma correction circuit architecture suitable for high-resolution display needs to be provided, where the single-slope digital-to-analog conversion circuit has the advantages of small area and low power consumption, and is widely used in high-resolution display driving circuits.

The generation of a ramp signal is most commonly performed in two structures, one is a current steering (current steering) structure, in which a ramp signal is generated by controlling a current flowing through a fixed resistor, and the other is an integration (integrating) structure, in which a fixed capacitor is charged with a fixed current to generate a continuous ramp signal. Both of these methods require setting accurate current to achieve accurate ramp step, are easily affected by process, temperature, voltage fluctuations (corner), etc., resulting in lower accuracy of gamma voltages, and in high speed applications, the signal setup time is too long.

It is desirable to provide an improved ramp signal generating circuit to address the above-described problems.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a ramp signal generating circuit and a gamma correction circuit, so as to achieve both accuracy and stability of the ramp signal and reduce difficulty in designing the circuit.

According to a first aspect of the present invention, there is provided a ramp signal generating circuit comprising:

a first capacitor, a first end of which is connected to an initial voltage via a first input switch and to a final voltage via a second input switch;

a second capacitor, a first end of which is grounded; and

a first branch and a second branch connected in parallel between the second end of the first capacitor and the second end of the second capacitor, the first branch comprising a first path switch, the second branch comprising a second path switch and a voltage follower connected in series,

wherein, in a precharge phase, the first input switch and the second path switch are turned on, the initial voltage charges the first capacitor,

in a step signal generation phase, said second input switch and said first path switch are turned on, said termination voltage driving charge to flow between said first capacitor and said second capacitor, thereby causing a voltage step on a second end of said second capacitor,

the precharge phase and the step signal generation phase are alternately performed to generate a ramp signal on the second terminal of the second capacitor that steps from the initial voltage to the termination voltage.

Optionally, the method further comprises:

an initialization switch, a second end of the second capacitor is connected to the initial voltage through the initialization switch,

in an initialization phase, the initialization switch, the first input switch and the second path switch are turned on, thereby initializing the voltage across the circuit.

Optionally, the method further comprises:

and the time sequence controller is used for generating clock signals for respectively controlling the initialization switch, the first input switch, the second input switch, the first path switch and the second path switch.

Optionally, the timing controller is configured to generate a first clock valid in the initialization phase, alternately valid second and third clocks in the precharge phase and the step signal generation phase, and send the first clock to the initialization switch, the second clock to the second input switch and the first path switch, and the third clock to the first input switch and the second path switch.

Optionally, the period of the second clock and the third clock is T, and the duty ratio is 1/2.

Optionally, when the number and the frequency of the clocks of the second clock and the third clock are fixed values, adjusting the slope of the ramp signal by adjusting the initial voltage and/or the termination voltage; and/or

And adjusting the slope of the ramp signal by adjusting the frequencies of the second clock and the third clock in the case where the initial voltage and the termination voltage are fixed values.

Optionally, each time the precharge phase and the step signal generation phase are performed, the amount of change in the voltage on the second terminal of the second capacitor is:

wherein Δvramp is the variation, vstart is the voltage value of the initial voltage, vend is the voltage value of the final voltage, C1 is the capacitance value of the first capacitor, and C2 is the capacitance value of the second capacitor.

Optionally, the number of times of executing the precharge phase and the step signal generation phase is N, and the capacitance value of the first capacitor and the capacitance value of the second capacitor satisfy:

optionally, when the voltage value of the initial voltage is greater than the voltage value of the final voltage, the slope of the ramp signal is negative;

when the voltage value of the initial voltage is smaller than the voltage value of the termination voltage, the slope of the slope signal is a positive number;

when the voltage value of the initial voltage is equal to the voltage value of the end voltage, the slope of the ramp signal is zero.

According to a second aspect of the present invention, there is provided a gamma correction circuit comprising:

the ramp generating circuit as described above, which supplies a ramp signal; and

and the processing unit is used for carrying out gamma correction on the display device according to the ramp signal.

According to the ramp signal generating circuit, the first capacitor is alternately connected to the initial voltage and the termination voltage, the ramp signal with step change is generated between the first capacitor and the second capacitor, the precision and the stability of the ramp signal are considered, and the design difficulty of the circuit is reduced.

Furthermore, under the condition that the size proportion of the first capacitor and the second capacitor is fixed, the initial voltage and the final voltage of the ramp signal can be flexibly set, the unit step length of the ramp signal can be automatically adapted to the initial voltage and the final voltage, namely the slope of the ramp signal can be flexibly controlled.

According to the ramp signal generating circuit, the unit step length of the ramp signal is self-adaptive, and when the capacitance values of the first capacitor and the second capacitor are fixed values and the voltage values of the initial voltage and the termination voltage are determined values, the slope of the ramp signal can be adjusted by controlling the frequency and other parameters of the clock signal, so that the ramp signal generating circuit can be flexibly applied to various scenes.

The gamma correction circuit has the advantage of self-adaptive step length, under fixed clock frequency, when gamma correction is carried out every time, only initial voltage and slope termination voltage are required to be set, the step length of a slope unit is adapted to different termination voltage automatic adjustment, slope signals with different slopes can be easily generated, gamma curve correction can be effectively completed without complex calculation and time sequence switching, and the chip mass production efficiency is greatly improved. The circuit design has lower requirement on the time sequence, the circuit is simpler to realize, and the area and the power consumption can be obviously saved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a circuit schematic of a ramp signal generating circuit according to an embodiment of the present invention;

fig. 2 shows an operation timing chart of the ramp signal generating circuit according to the embodiment of the present invention;

fig. 3 shows an equivalent circuit diagram of a ramp signal generating circuit in a first stage according to an embodiment of the present invention;

fig. 4 shows an equivalent circuit diagram of the ramp signal generating circuit in the second stage according to an embodiment of the present invention;

fig. 5 shows an equivalent circuit diagram of the ramp signal generating circuit in a third stage according to an embodiment of the present invention;

fig. 6 shows a waveform diagram of a ramp signal according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.

It should be understood that a and B in the embodiments of the present application are connected/coupled, which means that a and B may be connected in series or parallel, or that a and B pass through other devices, which embodiments of the present application do not limit.

The term "unit step size (Δv)" as used herein refers to the minimum step voltage amplitude of the ramp signal.

The main function of the ramp signal generating circuit is to generate a ramp signal which can be used in a circuit requiring a linear change in voltage, typically used as a reference signal, a slope compensation signal, or used in a scan voltage generating circuit, etc.

The ramp signal generating circuit provided by the present application can be applied to various systems, for example, to a display system, a communication system, a power transmission system, a detection system, and the like, and more specifically, for example, to be utilized in a gamma correction circuit of a display system. Among them, display systems are for example but not limited to: a light emitting diode (Light Emitting Diode, LED) display system, an organic light emitting diode (Organic Light Emitting Diode, OLED) display system, a mini LED display system, a micro OLED display system, etc., a liquid crystal (Liquid Crystal Display, LCD) display system, etc.

The ramp signal generating circuit provided by the invention realizes the self-adaptive adjustment of the unit step length of the ramp signal according to the initial voltage and the termination voltage of the ramp signal by configuring the proportion of the capacitor and the conduction condition of the circuit, thereby reducing the complexity of the circuit while ensuring the precision of the ramp signal.

Embodiments of a ramp signal generating circuit and a gamma correction circuit provided in the present application will be described below with reference to the accompanying drawings.

Fig. 1 shows a circuit schematic of a ramp signal generating circuit according to an embodiment of the present invention. Fig. 2 shows an operation timing chart of the ramp signal generating circuit according to an embodiment of the present invention, based on an exemplary configuration. Fig. 3 shows an equivalent circuit diagram of the ramp signal generating circuit in a first stage according to an embodiment of the present invention. Fig. 4 shows an equivalent circuit diagram of the ramp signal generating circuit in the second stage according to an embodiment of the present invention. Fig. 5 shows an equivalent circuit diagram of the ramp signal generating circuit in the third stage according to an embodiment of the present invention. Fig. 6 shows a waveform diagram of a ramp signal according to an embodiment of the present invention, based on an exemplary configuration.

As shown in fig. 1, the ramp signal generating circuit 100 includes: the first input terminal P1, the second input terminal P2, the initialization switch sw1, the first input switch sw3a, the second input switch sw3b, the first path switch sw2a, the second path switch sw2b, the first capacitor C1, the second capacitor C2 and the operational amplifier Opamp.

The first input terminal P1 receives the initial voltage Vstart, and the second input terminal P2 receives the termination voltage Vend. The first input terminal P1 is connected to the first terminal (i.e., the bottom plate) of the first capacitor C1 via the first input switch sw3a, and the second input terminal P2 is connected to the first terminal of the first capacitor C1 via the second input switch sw3 b.

The second end (i.e., upper plate) of the first capacitor C1 and the second end (i.e., upper plate) of the second capacitor C2 are connected to each other via the first path switch sw2a, and the first end of the second capacitor C2 (i.e., lower plate) is grounded.

The second end of the first capacitor C1 and the second end of the second capacitor C2 are also connected to each other via the second path switch sw2b and the voltage follower. Specifically, the first input terminal P1 is connected to a non-inverting input terminal of the operational amplifier Opamp via the initializing switch sw1, the second terminal of the second capacitor C2 is connected to the non-inverting input terminal of the operational amplifier Opamp, the inverting input terminal of the operational amplifier Opamp is directly connected to the output terminal thereof to form the voltage follower, and the output terminal of the operational amplifier Opamp is connected to the second terminal of the first capacitor C1 via the second path switch sw2 b.

The second terminal of the second capacitor C2 is used as the output terminal P3 of the ramp signal generating circuit 100 to output the ramp signal Vramp.

Under the clock control of the ramp signal generating circuit 100, the initializing switch sw1, the first input switch sw3a, the second input switch sw3b, the first path switch sw2a and the second path switch sw2b are respectively configured in different states, so that the lower electrode plate (i.e., the first end) of the first capacitor C1 is alternately connected to the set initial voltage Vstart and the end voltage Vend, and a step voltage is realized according to the size ratio of the first capacitor and the second capacitor by utilizing charge sharing, so as to generate a step ramp signal close to a full swing.

The operation of the ramp signal generating circuit 100 may be divided into an initialization stage in which the lower plate of the first capacitor C1 and the upper plate of the second capacitor C2 are connected to an initial voltage Vstart of a ramp signal to be generated; in the ramp signal generating stage, the lower plate of the first capacitor C1 is alternately connected to the initial voltage Vstart and the end voltage Vend of the ramp signal to be generated, so that the level of the upper plate of the second capacitor C2 is changed stepwise from the initial voltage Vstart to the end voltage Vend according to the proportional relationship between the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2.

Specifically, the ramp signal generating stage includes alternately performed precharge stages and step signal generating stages. That is, after the initialization phase is completed, the initialization switch sw1 is turned off, and the first input switch sw3a, the second input switch sw3b, the first path switch sw2a, and the second path switch sw2b are controlled by a clock signal having a period T and a duty ratio of 50%. When the first input switch sw3a and the second path switch sw2b are turned on, the second input switch sw3b and the first path switch sw2a are turned off; when the first input switch sw3a and the second path switch sw2b are turned off, the second input switch sw3b and the first path switch sw2a are turned on.

In the ramp signal generating stage, the on/off time of each switch is maintained at T/2, and an exemplary clock signal for controlling the initializing switch sw1, the first input switch sw3a, the second input switch sw3b, the first path switch sw2a and the second path switch sw2b can refer to fig. 2. It should be understood that the frequency and the duty cycle of the clock signal can be freely set according to actual needs, so that the ramp signal is different from the ramp signal shown in fig. 6, and the parameters such as the frequency and the duty cycle of the clock signal are not limited in the application. In the ramp signal generating circuit provided by the invention, the duty ratio of the clock signal does not influence the generation of the ramp signal, so that the clock signal with any duty ratio can be selected, and the application range of the ramp signal generating circuit is enlarged.

Optionally, clock signals respectively controlling the initialization switch, the first input switch, the second input switch, the first path switch, and the second path switch are generated by a timing controller (not shown). Specifically, referring to fig. 2, the timing controller is configured to generate a first clock sw1 that is active during an initialization phase, alternately active second clocks sw2a/sw3b and third clocks sw2b/sw3a during a precharge phase and a step signal generation phase, and transmit the first clocks to the initialization switch, the second clocks sw2a/sw3b to the second input switch and the first path switch, and the third clocks sw2b/sw3a to the first input switch and the second path switch.

In some embodiments, the second clock and the third clock have a period T and a duty cycle of 1/2.

In other embodiments, in the case that the number and frequency of the clocks of the second clock and the third clock are fixed values, the slope of the ramp signal is adjusted by adjusting the initial voltage and/or the termination voltage; and/or adjusting the slope of the ramp signal by adjusting the frequencies of the second clock and the third clock in the case where the initial voltage and the final voltage are both fixed values.

The specific operation principle of the ramp signal generating circuit according to the embodiment of the present application will be described in detail with reference to fig. 2 to 5.

In a first phase t1, the initialization phase: the clock signal shown in fig. 2 controls the initialization switch sw1, the first input switch sw3a and the second path switch sw2b to be turned on, and the second input switch sw3b and the first path switch sw2a to be turned off, and an equivalent circuit diagram of the ramp signal generating circuit in the first stage is shown in fig. 3. The initial voltage Vstart charges the ramp signal Vramp, the lower plate of the first capacitor C1, and the upper plate of the second capacitor C2 to the initial voltage Vstart, and the output voltage of the operational amplifier Opamp and the upper plate of the first capacitor C1 are also initialized to the initial voltage Vstart under the driving of the operational amplifier Opamp.

In a second phase t2, the precharge phase: in comparison with the first stage, the clock signal shown in fig. 2 turns off the initialization switch sw1, and at this time, the clock signal controls the first input switch sw3a and the second path switch sw2b to be turned on, and the second input switch sw3b, the first path switch sw2a and the initialization switch sw1 are turned off, so that an equivalent circuit diagram of the ramp signal generating circuit in the second stage is shown in fig. 4. The lower plate of the first capacitor C1 is still connected to the initial voltage Vstart, and the upper plate of the second capacitor C2 is in a hold state for a holding time of T/2, and the ramp signal is Vramp (n). According to the charge amount calculation formula q=c×u of the capacitor, the charge amount Q1 on the first capacitor C1 _C1 = (Vramp (n) -Vstart) C1, the amount of charge Q1 on the second capacitor C2 _C2 =vramp (n) ×c2, then the total charge on the first and second capacitances C1 and C2 is as shown in equation (1):

Q1＝Q1 _C1 +Q1 _C2 ＝(Vramp(n)-Vstart)*C1+Vramp(n)*C2 (1)

in a third phase t3, the step signal generation phase: compared with the second stage, the clock signal shown in fig. 2 controls the initializing switch sw1 to be kept off, and at this time, the clock signal controls the second input switch sw3b and the first path switch sw2a to be turned on, and the first input switch sw3a, the second path switch sw2b and the initializing switch sw1 are turned off, so that the ramp signal generating circuit is in the second stageThe equivalent circuit diagram is shown in fig. 5. The lower electrode plate of the first capacitor C1 is connected to the termination voltage Vend, and the upper electrode plate of the first capacitor C1 is electrically connected with the upper electrode plate of the second capacitor C2, and the holding time is T/2. At this time, the charge amount Q2 on the first capacitor C1 _C1 = (Vramp (n+1) -Vend) C1, the charge amount Q2 on the second capacitor C2 _C2 =vramp (n+1) ×c2, then the total charge on the first and second capacitances C1 and C2 is as shown in formula (2):

Q2＝Q2 _C1 +Q2 _C2 ＝(Vramp(n+1)-Vend)*C1+Vramp(n+1)*C2 (2)

in the fourth phase T4, i.e. the full ramp generation phase, the clock signal shown in fig. 2 is configured to repeat the second and third phases N-1 times with a fixed period T until the initialization switch sw1 is turned on again, i.e. enters the initialization phase again, and starts generating the next ramp signal.

A complete ramp signal is generated from the second stage to the fourth stage, and the voltage change of each step signal is shown in formula (3):

ΔVramp＝Vramp(n+1)-Vramp(n) (3)

the law of conservation of charge is known as:

Q1＝Q2 (4)

by combining the formulas (1) - (4), the voltage change delta of each step signal can be obtained

That is, every time the precharge phase and the step signal generation phase are performed, the voltage value of the ramp signal is changed +.>

Thus, the final voltage of the full ramp signal is:

if the capacitance ratio of the first capacitor to the second capacitor is set to be as follows

Vramp (end) =vend, and the resulting ramp signal is shown in the ramp signal waveform diagram shown in fig. 6. The ratio of the capacitance values of the first capacitor and the second capacitor and the number of steps N are in a specific ratio, and the ratio is 1:1 but is not limited to 1:1. it should be understood that the ratio of the first capacitor to the second capacitor and the number N of step signals of the ramp signal may be freely set according to actual needs, so as to generate a ramp signal different from that shown in fig. 6.

The present application also provides a gamma correction circuit (not shown), including a ramp signal generating circuit as shown in fig. 1 and a processing unit, where the processing unit uses the ramp signal provided by the ramp signal generating circuit as a gamma voltage to perform gamma correction on a display device, and the specific circuit structure of the gamma correction circuit is not limited.

The ramp signal generating circuit provided by the application has the following advantages:

1) The slope signal generating circuit can flexibly set the initial voltage Vstart and the termination voltage Vend of the slope signal under the condition that the size proportion of the first capacitor and the second capacitor is fixed, the unit step length of the slope signal can be automatically adapted to the initial voltage Vstart and the termination voltage Vend, namely the slope of the slope signal can be flexibly controlled, and the unit step length of the slope signal is fixed under the condition that the size proportion of the first capacitor and the second capacitor is fixed in the prior art, namely the slope is fixed and cannot be changed.

2) According to the ramp signal generating circuit, the unit step length of the ramp signal is self-adaptive, the ramp signal of the initial voltage Vstart and the end voltage Vend can be realized without complex calculation, the number of steps of the initial voltage Vstart and the ramp signal can only be set in the prior art, in order to realize different end voltages Vend, the complex calculation is required to be carried out by combining the initial voltage Vstart and the unit step length, the number of the step signals is controlled, in certain applications, the number of the step signals of the ramp signal is fixed, the step length change can only be realized by adding a plurality of groups of capacitors with different proportions, so that the area and the power consumption of a chip are definitely increased, the complexity of the chip is improved, and the mass production of the chip is not facilitated.

3) According to the ramp signal generating circuit, the initial voltage Vstart is controlled to be smaller than the end voltage Vend, so that a positive slope ramp signal, namely a ramp signal with gradually increased ramp signal along with time, can be realized, and the initial voltage Vstart is controlled to be larger than the end voltage Vend, so that a negative slope ramp signal, namely a ramp signal with gradually reduced ramp signal along with time, can be realized.

4) According to the ramp signal generating circuit, the unit step length of the ramp signal is self-adaptive, and when the capacitance values of the first capacitor and the second capacitor are fixed values and the voltage values of the initial voltage Vstart and the termination voltage Vend are determined values, the slope of the ramp signal can be adjusted by controlling the frequency, the duty ratio and other parameters of the clock signal, so that the ramp signal generating circuit can be flexibly applied to various scenes.

Some examples of the ramp signal generating circuit of the embodiment of the present invention are described above, however the embodiment of the present invention is not limited thereto, and other manners of expansion and modification are also possible.

For example, it should be appreciated that the reference ground potential in the foregoing embodiments may be replaced with other non-zero reference potentials (having positive or negative voltage magnitudes) or controlled varying reference signals in alternative embodiments.

For another example, the capacitor provided in the embodiments of the present application may be a lumped-parameter capacitor element, or a capacitor group added with the same or similar capacitor, or may be an equivalent element with a similar function to that of a capacitor, where the equivalent structure is, for example, but not limited to, a microstrip line, a varactor, a conductor structure with a certain pattern, or the like, which may provide capacitive impedance. For example, the voltage follower provided in the embodiment of the present application may be formed by an operational amplifier, or may be formed by components such as a transistor.

For another example, the ramp signal generating circuit may be a discrete device or may be a circuit unit. In other implementations, the ramp signal generating circuit described above may be packaged in a device.

Also, those of ordinary skill in the art will recognize that structures and methods of examples described in connection with the embodiments disclosed herein may be implemented using different configurations or adaptations of each structure or reasonable variations of that structure to achieve the described functionality, but such implementations should not be construed as outside the scope of the present application. Also, it should be understood that the connection relationship between the respective components of the amplifier of the foregoing drawings in the embodiments of the present application is illustrative and not limiting in any way.

It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A ramp signal generating circuit, comprising:

a second capacitor, a first end of which is grounded; and

2. The ramp generating circuit according to claim 1, further comprising:

3. The ramp generating circuit according to claim 2, further comprising:

4. A ramp generating circuit according to claim 3, wherein said timing controller is configured to generate a first clock active during said initialization phase, to alternate between a second clock active during said precharge phase and said step signal generation phase and a third clock active during said step signal generation phase, and to send said first clock to said initialization switch, said second clock to said second input switch and said first path switch, and said third clock to said first input switch and said second path switch.

5. The ramp generating circuit according to claim 4, wherein,

the period of the second clock and the third clock is T, and the duty ratio is 1/2.

6. The ramp generating circuit according to claim 4, wherein in the case where the number and frequency of clocks of the second clock and the third clock are fixed values, the slope of the ramp signal is adjusted by adjusting the initial voltage and/or the termination voltage; and/or

7. The ramp generating circuit according to claim 1, wherein the amount of change in the voltage on the second terminal of the second capacitor per each of the precharge phase and the step signal generating phase is:

8. The ramp generating circuit according to claim 7, wherein the number of times the precharge phase and the step signal generating phase are performed is N, respectively, and the capacitance values of the first capacitor and the second capacitor satisfy:

9. the ramp generating circuit according to claim 1, wherein,

when the voltage value of the initial voltage is larger than the voltage value of the termination voltage, the slope of the slope signal is a negative number;

10. A gamma correction circuit, comprising:

the ramp generating circuit according to any one of claims 1 to 9, providing a ramp signal; and a processing unit for performing gamma correction on the display device according to the ramp signal.