CN115172336A - Test structure - Google Patents
Test structure Download PDFInfo
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- CN115172336A CN115172336A CN202211081388.3A CN202211081388A CN115172336A CN 115172336 A CN115172336 A CN 115172336A CN 202211081388 A CN202211081388 A CN 202211081388A CN 115172336 A CN115172336 A CN 115172336A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Abstract
The invention provides a test structure which comprises an N-1 metal layer, an Nth metal layer, an N +1 metal layer, a first bonding pad to a fourth bonding pad, wherein dielectric layers are arranged between every two metal layers, the Nth metal layer comprises a plurality of first metal wires which are arranged in parallel at intervals, the first bonding pad and the second bonding pad are respectively connected to two ends of the first metal wires, the N-1 metal layer and the Nth metal layer are connected through metal through holes, the third bonding pad is connected with the N-1 metal layer, the fourth bonding pad is connected with the N +1 metal layer, N is more than or equal to 2 and is a positive integer; applying a current on the first pad and the second pad to perform an EM test on the first metal line; and applying voltage to the second pad and the fourth pad, or applying voltage to the second pad and the third pad to perform a TDDB test, so that the TDDB test and the EM test can be performed, the TDDB effect caused by the EM test can be considered, and the TDDB effect of the dielectric layer after the EM test can be comprehensively evaluated.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a test structure.
Background
As integrated circuit technology continues to advance, more devices will be integrated on a chip, and the chip will also adopt faster speeds. With these demands, the geometric size of the device will be reduced, and new materials, new technologies and new manufacturing processes are adopted in the chip manufacturing process. These improvements have a significant impact on the lifetime of the individual devices, potentially resulting in increased vulnerability of local areas, increased power density, increased complexity of the devices and the introduction of new failure mechanisms, while the smaller fault tolerance space means that lifetime issues must be accounted for at the beginning of the design and monitored and tested throughout the development and manufacturing of the devices until the end product is complete.
Currently, the process reliability is evaluated by a Stress Migration (SM) test, an Electromigration (EM) test, and a Time Dependent Dielectric Breakdown (TDDB) test for a back-end evaluation project, and particularly, the EM test and the TDDB test are used as evaluation key points. Electromigration is the migration of electrons to atoms of the metal layer, causing open circuit or short circuit of the metal layer; the TDDB test is that the voltage difference between the same layer of metal or different layers of metal causes the dielectric layer to break down, so that the dielectric layer loses the insulation effect. Currently, the test structure for evaluating the process reliability is designed only for a single item, and the chip necessarily generates multiple effects in practical use, which makes the evaluation on the lifetime of the chip too optimistic, for example, the EM test may cause the metal layer to generate voids (void) and extrusion (extrusion), the voids are generated at the cathode by electron-driven atomic motion, the extrusion is that atoms continuously move towards the anode, the anode metal extrudes into the dielectric layer, the generation of extrusion inevitably causes the effect of the TDDB test on the dielectric layer to deteriorate, and the test structure of the TDDB test and the EM test does not consider such a situation at present.
Disclosure of Invention
The invention aims to provide a test structure which can carry out TDDB test and EM test, so that the TDDB test considers the effect generated by EM test.
In order to solve the above problems, the present invention provides a test structure, which includes an N-1 th metal layer, an nth metal layer, an N +1 th metal layer, and first to fourth pads, wherein the N-1 th metal layer, the nth metal layer, and the N +1 th metal layer are sequentially stacked at intervals from bottom to top, and a dielectric layer is disposed between every two metal layers, the nth metal layer includes a plurality of first metal lines arranged in parallel and at intervals, the first pads and the second pads are respectively connected to two ends of all the first metal lines, the N-1 th metal layer and the nth metal layer are connected through metal vias, the third pad is connected to the N-1 th metal layer, and the fourth pad is connected to the N +1 th metal layer, wherein N is greater than or equal to 2 and is a positive integer;
applying a current on the first pad and the second pad to perform an EM test on the first metal line; and applying a voltage to the second pad and the fourth pad, or applying a voltage to the second pad and the third pad to perform a TDDB test.
Optionally, all the first metal wires have the same shape and the same size.
Optionally, the nth metal layer further includes a first parallel end and a second parallel end, one end of the first parallel end and one end of the second parallel end are respectively connected to two ends of the first metal line, the other end of the first parallel end is connected to the first pad, and the other end of the second parallel end is connected to the second pad.
Furthermore, the nth metal layer further comprises a plurality of second metal lines which are parallel to each other, have two ends aligned and are arranged at intervals, the first metal lines and the second metal lines are arranged in parallel, each of the second metal lines is arranged on two sides of each of the first metal lines, and all the first metal lines and the adjacent second metal lines are arranged at equal intervals.
Further, the first parallel end and the second parallel end are of two identical structures, and the first parallel end and the second parallel end are symmetrically connected to two sides of all the first metal wires.
Further, first parallelly connected tip and the parallelly connected tip of second all include the first part, second part and the third part that connect gradually, the first part includes a plurality of parallels, both ends align and the extraction portion that the interval set up, the extending direction of extraction portion with the extending direction of first metal wire is the same, just the one end of extraction portion is connected first metal wire, the other end of extraction portion is connected one side of second part, the opposite side of second part is connected the one end of third part, the other end of the third part of first parallelly connected tip is connected first pad, the other end of the third part of the parallelly connected tip of second is connected the second pad.
Furthermore, the N-1 metal layer includes a connection portion and a connection portion, the connection portion is disposed on one side of the connection portion, the connection portion is located below the first metal line and a second metal line of the N metal layer, and is also located right below the N +1 metal layer, the connection portion is located below the first parallel end portion, an overlapping region is formed between a projection of the second metal line on the N-1 metal layer and the connection portion, the connection portion and the second metal line are connected through the metal through hole, and the connection portion is further connected to the third pad.
Further, connecting portion include an end connection line and a plurality of through-hole connecting line, the through-hole connecting line is close to the connecting line portion sets up, all the through-hole connecting line is parallel, both ends are aligned and the interval sets up, all the one end of through-hole connecting line is all connected one side of end connection line, and all the through-hole connecting line is close to the one end setting of end connection line, every the second metal wire is in projection on the N-1 metal level all with one the through-hole connecting line has overlap region, every the through-hole connecting line all with one the second metal wire passes through one the metal through-hole is connected, the other end of end connection line is connected the third pad.
Furthermore, the connecting portion comprises a plurality of third metal wires and a third parallel end portion, all the third metal wires are parallel, the two ends of the third metal wires are aligned and arranged at intervals, the third metal wires are close to the through hole connecting lines, the third metal wires and the through hole connecting lines are arranged in parallel, each extending line of one end of each third metal wire is located at two adjacent through hole connecting lines, and the other end of each third metal wire is connected to one side of the third parallel end portion.
Further, the third parallel end includes a fourth portion and a fifth portion, all the third metal wires are connected to one side of the fourth portion, and the fifth portion is connected to the other side of the fourth portion.
Optionally, the (N + 1) th metal layer includes a plurality of fourth metal lines and a fourth parallel end, all the fourth metal lines are parallel, both ends of the fourth metal lines are aligned and spaced apart, and all one ends of the fourth metal lines are connected to one side of the fourth parallel end, and the fourth parallel end is further connected to the fourth pad.
Further, the fourth parallel end includes a sixth portion and a seventh portion, all the fourth metal lines are connected to one side of the sixth portion, one end of the seventh portion is connected to the other side of the sixth portion, and the other end of the seventh portion is connected to the fourth pad.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a test structure which comprises an N-1 metal layer, an Nth metal layer, an N +1 metal layer, a first bonding pad to a fourth bonding pad, wherein the N-1 metal layer, the Nth metal layer and the N +1 metal layer are sequentially stacked at intervals from bottom to top, a dielectric layer is arranged between every two metal layers, the N metal layer comprises a plurality of first metal wires which are parallel and arranged at intervals, the first bonding pad and the second bonding pad are respectively connected to two ends of all the first metal wires, the N-1 metal layer and the N metal layer are connected through metal through holes, the third bonding pad is connected with the N-1 metal layer, the fourth bonding pad is connected with the N +1 metal layer, N is more than or equal to 2 and is a positive integer; applying a current on the first pad and the second pad to perform an EM test on the first metal line; and applying a voltage to the second pad and the fourth pad, or applying a voltage to the second pad and the third pad to perform a TDDB test. The test structure can be used for performing both TDDB test and EM test, so that the TDDB effect caused by the EM test can be considered, the breakdown time of the dielectric medium in the actual use of the chip can be accurately simulated, the TDDB effect of the dielectric medium layer after the EM test can be comprehensively evaluated, and the service life of the chip in the actual work can be simulated.
Drawings
Fig. 1 is a schematic structural diagram of a test structure according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view along AA' of FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along line BB' of FIG. 1;
FIG. 4 is a schematic cross-sectional view taken along line CC' of FIG. 1;
fig. 5 is a schematic structural diagram of an nth metal layer according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of an N-1 th metal layer according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an N +1 th metal layer according to an embodiment of the invention.
Description of reference numerals:
1-nth-1 metal layer; 11-a connecting portion; 111-via connection lines; 112-end connection lines; 12-a wire connecting portion; 121-a third metal line; 122-fourth section; 123-a fifth part; 2-Nth metal layer; 21-a first metal line; 22-a second metal line; 23-a first parallel end; 231-a lead-out portion; 232-a second portion; 233-third part; 24-a second parallel end; 3-N +1 th metal layer; 31-a fourth metal line; 32-fourth parallel end; 321-a sixth portion; 322-seventh part; 4-metal vias.
Detailed Description
A more detailed description of a test structure of the present invention will now be given in conjunction with the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that a person skilled in the art may modify the invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
Fig. 1 is a schematic structural diagram of a test structure provided in this embodiment. FIG. 2 is a schematic cross-sectional view along AA' of FIG. 1. Fig. 3 is a schematic cross-sectional view along BB' in fig. 1. Fig. 4 is a schematic cross-sectional view taken along line CC of fig. 1. As shown in fig. 1-4, the present embodiment provides a test structure that can perform both EM (electro-migration) and TDDB (time dependent dielectric breakdown) tests.
The test structure comprises an N-1 metal layer 1, an N metal layer 2, an N +1 metal layer 3, a metal through hole 4 and four bonding pads (such as a first bonding Pad1, a second bonding Pad2, a third bonding Pad3 and a fourth bonding Pad 4), wherein the N-1 metal layer 1, the N metal layer 2 and the N +1 metal layer 3 are sequentially stacked at intervals from bottom to top, dielectric layers for insulation are arranged between every two bonding pads, the metal through hole 4 is arranged in the dielectric layer between the N-1 metal layer 1 and the N metal layer 2, the metal through hole 4 is connected with the N-1 metal layer 1 and the N metal layer 2, the four bonding pads are positioned above the N +1 metal layer 3, the first bonding Pad1 and the second bonding Pad2 are both connected with the N metal layer 2, the third bonding Pad3 is connected with the N-1 metal layer 1, and the fourth bonding Pad4 is connected with the N +1 metal layer 3, wherein N is not less than 2 and is a positive integer.
Fig. 5 is a schematic structural diagram of the nth metal layer provided in this embodiment. As shown in fig. 5, the nth metal layer 2 includes a plurality of first metal lines 21, a plurality of second metal lines 22, and a first parallel end 23 and a second parallel end which connect all the first metal lines 21 in parallel, wherein one end of the first parallel end 23 and one end of the second parallel end 24 are respectively connected to both ends of all the first metal lines 21, and the other end of the first parallel end 23 is connected to the first Pad1, and the other end of the second parallel end is connected to the second Pad2. One end of the second metal line 22 is connected to the metal via 4, so that the second metal line 22 is connected to the N-1 th metal layer 1.
All the first metal lines 21 are arranged in parallel and at intervals, further, all the first metal lines 21 are arranged in parallel and at equal intervals, and two ends of all the first metal lines 21 are aligned; all the second metal lines 22 are parallel, have two ends aligned and are arranged at intervals, further, all the second metal lines 22 are parallel, have two ends aligned and are arranged at equal intervals, and the two ends of all the second metal lines 22 are aligned, the first metal lines 21 and the second metal lines 22 are also arranged in parallel, two sides of each first metal line 21 are provided with one second metal line 22, and all the first metal lines 21 and the adjacent second metal lines 22 are arranged at equal intervals, that is, the intervals between all the first metal lines 21 and the adjacent second metal lines 22 are preset values. The distance between the first metal line 21 and the second metal line 22 adjacent to the first metal line must be greater than or equal to a design specification, and preferably, the value of the distance is a minimum value of the design specification.
One end of the first parallel end portion 23 is connected to one end of the first metal line 21, and one end of the second parallel end portion 24 is connected to the other end of the first metal line 21, so that an EM test is performed through a structure formed by the first parallel end portion 23, the second parallel end portion, and all the first metal lines 21.
The first metal wire 21 and the second metal wire 22 are both long. All the first metal lines 21 have the same shape (e.g., a long rectangle) and the same size (i.e., the same length and the same width), that is, all the first metal lines 21 are identical, so that each of the first metal lines 21 has the same resistance, and thus the current passing through each of the first metal lines 21 is the same during the EM test, thereby preventing the occurrence of non-uniform current distribution during the EM test.
In this embodiment, the shape of the second metal line 22 is the same as the shape of the first metal line 21 (for example, all are long rectangles), the length of the second metal line 22 is the same as the length of the first metal line 21, and the width of the second metal line 22 is the same as the width of the first metal line 21. In other embodiments, the length of the second metal line 22 may be different from the length of the first metal line 21, and the width of the second metal line 22 may be different from the width of the first metal line 21, which may be specifically designed according to actual requirements.
The first parallel end 23 and the second parallel end have the same shape, and preferably, the first parallel end 23 and the second parallel end have the same structure, and the first parallel end 23 and the second parallel end 24 are symmetrically connected to both sides of all the first wires 21.
Taking the first parallel end portion 23 as an example, the first parallel end portion 23 includes a first portion, a second portion 232 and a third portion 233 which are connected in sequence, the first portion includes a plurality of lead portions 231 which are parallel, have two aligned ends and are arranged at intervals, the number of the lead portions 231 is the same as that of the first metal wires 21, the lead portions 231 are long, the extending direction of the lead portions 231 is the same as that of the first metal wires 21, one end of each lead portion 231 is connected to one end of each first metal wire 21, the other end of each lead portion 231 is connected to one side of the second portion 232, the second portion 232 is long, the two ends of the second portion 232 are respectively connected to one lead portion 231, and the rest of the lead portions 231 are arranged between the two ends of the second portion 232.
In this embodiment, the width of the lead-out portion 231 is smallest at a side close to the first metal line 21 (i.e. has a minimum width at a side close to the first metal line 21), and gradually increases toward a direction away from the first metal line 21 and then remains unchanged, and the minimum width of the lead-out portion 231 is equal to the width of the first metal line 21. The width of the second portion 232 is greater than the maximum width of each of the lead-out portions 231.
One end of the third portion 233 is connected to the other side of the second portion 232, and the other end is connected to the first Pad1, and further, the other end of the third portion 233 and the first Pad1 are connected through a metal connection hole. The third portion 233 may be formed by connecting at least one strip-shaped metal line end to end in sequence, and the width of each metal line of the third portion 233 is greater than the maximum width of each lead-out portion 231, and preferably, the width of each metal line of the third portion 233 is equal to the width of the second portion 232.
One end of the lead-out portion of the second parallel end portion 24 is connected to the other end of one of the first metal lines, one side of the second portion of the second parallel end portion 24 is connected to all the lead-out portions, the other side of the second portion of the second parallel end portion 24 is connected to one end of the third portion of the second parallel end portion 24, and the other end of the third portion of the second parallel end portion 24 is connected to the second Pad2 through a metal connection hole.
Fig. 6 is a schematic structural diagram of the N-1 th metal layer provided in this embodiment. As shown in fig. 6, the N-1 th metal layer 1 includes a connection portion 11 and a connection portion 12, the connection portion 11 is disposed on one side of the connection portion 12, the connection portion 12 is located below the first metal line 21 and the second metal line 22, and is also located directly below the N +1 th metal layer, and the connection portion 11 is located below the first portion. The projection of the second metal line 22 on the N-1 metal layer 1 and the connection portion 11 have an overlapping region, and in the overlapping region, the connection portion 11 and the second metal line are connected through a metal via 4, and the connection portion 11 is further connected to the third pad.
Connecting portion 11 includes an end connection line 112 and a plurality of through-hole connection line 111, all through-hole connection line 111 is parallel, both ends are aligned and the interval sets up, all through-hole connection line 111's one end is all connected one side of end connection line 112, simultaneously, through-hole connection line 111 is close to line portion 12 sets up, and every second metal line 22 is in projection on the N-1 metal level 1 all with one through-hole connection line 111 has overlap region, every through-hole connection line 111 all with one the second metal line passes through one metal via 4 connects, end connection line 112 still connects third Pad3, and is detailed, end connection line 112 passes through the metal via connection hole and connects third Pad3.
The end connecting lines 112 and the through hole connecting lines 111 are both in a long strip structure, and all the through hole connecting lines 111 are close to one end of the end connecting lines 112, namely, one end of the end connecting lines 112 is connected to one end of the through hole connecting lines 111, the other end of the end connecting lines 111 is close to one end of the end connecting lines 112, the other end of the end connecting lines 112 is connected to the third Pad3, in detail, the other end of the end connecting lines 112 is connected to the third Pad3 through a metal connecting hole.
The number of the via connection lines 111 is the same as the number of the metal vias 4, i.e. the number of the via connection lines 111 is the same as the number of the first metal lines 21. The width of the via connection line 111 may be the same as the width of the end connection line 112, and the width of the via connection line 111 may not be the same as the width of the end connection line 112.
The connecting line part 12 includes a plurality of third metal lines 121 and a third parallel end part, all the third metal lines 121 are parallel, both ends of the third metal lines are aligned and spaced, the third metal lines 121 are close to the through hole connecting lines 111, the third metal lines 121 and the through hole connecting lines 111 are parallel, each extending line of one end of the third metal lines 121 is located in a gap between two adjacent through hole connecting lines 111, and the other end of the third metal line 121 is connected to one side of the third parallel end part. In this embodiment, the number of the third metal lines 121 may be the same as the number of the first metal lines 21, and the third metal lines 121 are located right below the first metal lines 21, so that one third metal line 121 is located below each first metal line 21.
The third parallel end portion includes a fourth portion 122 and a fifth portion 123, the fourth portion 122 and the third metal lines 121 are both long, all the third metal lines 121 are connected to one side of the fourth portion 122, further, the other end of each third metal line 121 is connected to one side of the fourth portion 122, two ends of the fourth portion 122 are respectively connected to one third metal line 121, and the rest of the third metal lines 121 are connected between two ends of the fourth portion 122. The fifth portion 123 is formed by sequentially connecting at least two metal wires end to end, and one end of the fifth portion 123 is connected to the other side of the fourth portion 122.
Fig. 7 is a schematic structural diagram of the N +1 th metal layer provided in this embodiment. As shown in fig. 7, the N +1 th metal layer 3 includes a plurality of fourth metal lines 31 and a fourth parallel end portion 32, all the fourth metal lines 31 are parallel, have two ends aligned and are spaced apart, and one end of all the fourth metal lines 31 is connected to one side of the fourth parallel end portion 32. The fourth metal line 31 is located above the first metal line 21 and the second metal line 22, the fourth parallel end 32 is located directly above the second parallel end, further, the fourth metal line 31 is located directly above the first metal line 21 and is disposed close to the second parallel end 24, the second parallel end 24 is located directly above the lead-out portion 231, and the fourth parallel end 32 is further connected to the fourth Pad4.
In this embodiment, the length of the fourth metal line 31 is smaller than the length of the first metal line 21, the width of the fourth metal line 31 is equal to the width of the first metal line 21, and the number of the fourth metal lines 31 is equal to the number of the first metal lines 21.
The fourth parallel end portion 32 includes a sixth portion 321 and a seventh portion 322, the sixth portion 321 and the fourth metal lines 31 are both long, all the fourth metal lines 31 are connected to one side of the sixth portion 321, two ends of the sixth portion 321 are respectively connected to one of the fourth metal lines 31, the remaining fourth metal lines 31 are connected between two ends of the sixth portion 321, the seventh portion 322 is formed by sequentially joining at least two metal lines end to end, one end of the seventh portion 322 is connected to the other side of the sixth portion 321, the other end of the seventh portion 322 is connected to the fourth Pad4, and further, the other end of the seventh portion 322 is connected to the fourth Pad4 through a metal connection hole.
Applying a current to the first Pad1 and the second Pad2 to perform an EM test, which may generate voids (void) and extrusions (extrusions) to the nth metal layer 2, wherein the extrusions may cause damage to the dielectric layer around the nth metal layer 2, i.e., cause deterioration of the TDDB test effect of the dielectric layer.
After a preset time, applying voltage to the second Pad2 and the fourth Pad4 to detect leakage to test the TDDB effect of different layers of dielectric layers, wherein the TDDB effect caused by EM test is considered; voltage is applied to the second bonding Pad2 and the third bonding Pad3 to detect electric leakage so as to detect the TDDB effect of the dielectric layer on the same layer, and the TDDB effect caused by the EM test is considered, so that the breakdown time of the dielectric layer in the actual use of the chip can be accurately simulated, the TDDB effect of the dielectric layer after the EM test can be comprehensively evaluated, and the service life of the chip in the actual work can be further simulated.
In summary, the present invention provides a test structure, including an N-1 th metal layer, an nth metal layer, an N +1 th metal layer, and first to fourth pads, where the N-1 th metal layer, the nth metal layer, and the N +1 th metal layer are sequentially stacked at intervals from bottom to top, and a dielectric layer is disposed between every two metal layers, the nth metal layer includes a plurality of first metal lines arranged in parallel and at intervals, the first pads and the second pads are respectively connected to two ends of all the first metal lines, the N-1 th metal layer and the nth metal layer are connected through metal vias, the third pad is connected to the N-1 th metal layer, and the fourth pad is connected to the N +1 th metal layer, where N is greater than or equal to 2 and is a positive integer; applying a current on the first pad and the second pad to perform an EM test on the first metal line; and applying a voltage to the second pad and the fourth pad, or applying a voltage to the second pad and the third pad to perform a TDDB test. The test structure can be used for performing both TDDB test and EM test, so that the TDDB effect caused by the EM test can be considered, the breakdown time of the dielectric medium in the actual use of the chip can be accurately simulated, the TDDB effect of the dielectric medium layer after the EM test can be comprehensively evaluated, and the service life of the chip in the actual work can be simulated.
Furthermore, unless otherwise specified or indicated, the descriptions of the terms "first," "second," "third," and the like in the specification are only used for distinguishing various components, elements, steps, and the like in the specification, and are not used for indicating logical relationships or sequential relationships among the various components, elements, steps, and the like.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are within the scope of the technical solution of the present invention, unless the technical essence of the present invention is not departed from the content of the technical solution of the present invention.
Claims (12)
1. A test structure is characterized by comprising an N-1 metal layer, an Nth metal layer, an N +1 metal layer, a first bonding pad and a fourth bonding pad, wherein the N-1 metal layer, the Nth metal layer and the N +1 metal layer are sequentially stacked at intervals from bottom to top, a dielectric layer is arranged between every two metal layers, the N metal layer comprises a plurality of first metal wires which are parallel and arranged at intervals, the first bonding pad and the second bonding pad are respectively connected to two ends of all the first metal wires, the N-1 metal layer and the N metal layer are connected through metal through holes, the third bonding pad is connected with the N-1 metal layer, the fourth bonding pad is connected with the N +1 metal layer, N is not less than 2 and is a positive integer;
applying a current on the first pad and the second pad to perform an EM test on the first metal line; and applying a voltage to the second pad and the fourth pad, or applying a voltage to the second pad and the third pad to perform a TDDB test.
2. The test structure of claim 1, wherein all of the first metal lines are the same shape and the same size.
3. The test structure of claim 1, wherein the nth metal layer further includes a first parallel end and a second parallel end, one end of the first parallel end and one end of the second parallel end are respectively connected to both ends of all the first metal lines, the other end of the first parallel end is connected to the first pad, and the other end of the second parallel end is connected to the second pad.
4. The test structure of claim 3, wherein the Nth metal layer further comprises a plurality of second metal lines arranged in parallel, aligned at two ends and spaced apart from each other, the first metal lines and the second metal lines are arranged in parallel, one second metal line is arranged on each of two sides of each first metal line, and all the first metal lines are arranged at equal intervals with the adjacent second metal lines.
5. The test structure of claim 3, wherein the first and second parallel ends are two identical structures, the first and second parallel ends being symmetrically connected on both sides of all of the first metal lines.
6. The test structure of claim 5, wherein the first parallel end and the second parallel end each include a first portion, a second portion and a third portion connected in sequence, the first portion includes a plurality of parallel lead-out portions with two ends aligned and spaced apart, the lead-out portions extend in the same direction as the first metal lines, one end of each lead-out portion is connected to the first metal lines, the other end of each lead-out portion is connected to one side of the second portion, the other side of the second portion is connected to one end of the third portion, the other end of the third portion of the first parallel end is connected to the first pad, and the other end of the third portion of the second parallel end is connected to the second pad.
7. The test structure of claim 4, wherein the N-1 metal layer comprises a connection portion and a connection portion, the connection portion is disposed at one side of the connection portion, the connection portion is located below the first metal line and a second metal line of the N metal layer and is also located right below the (N + 1) th metal layer, the connection portion is located below the first parallel end portion, a projection of the second metal line on the N-1 metal layer has an overlapping region with the connection portion, the connection portion and the second metal line are connected through the metal via in the overlapping region, and the connection portion is further connected to the third pad.
8. The test structure of claim 7, wherein the connection portion comprises an end connection line and a plurality of via connection lines, the via connection lines are disposed adjacent to the connection portion, all the via connection lines are disposed in parallel, aligned at two ends and spaced apart, one end of all the via connection lines is connected to one side of the end connection line, all the via connection lines are disposed adjacent to one end of the end connection line, a projection of each of the second metal lines on the N-1 metal layer has an overlapping region with one of the via connection lines, in the overlapping region, each of the via connection lines is connected to one of the second metal lines through one of the metal vias, and the other end of the end connection line is connected to the third pad.
9. The test structure of claim 8, wherein the wire portion comprises a plurality of third metal lines and a third parallel end portion, all of the third metal lines are parallel, aligned at both ends and spaced apart, the third metal lines are disposed adjacent to the via connecting lines, and the third metal lines and the via connecting lines are disposed in parallel, an extension line of one end of each of the third metal lines is located in a gap between two adjacent via connecting lines, and the other end of the third metal line is connected to one side of the third parallel end portion.
10. The test structure of claim 9, wherein the third parallel end portion comprises a fourth portion and a fifth portion, all of the third metal lines being connected on one side of the fourth portion, the fifth portion being connected on the other side of the fourth portion.
11. The test structure of claim 1, wherein the N +1 th metal layer comprises a plurality of fourth metal lines and a fourth parallel end, all of the fourth metal lines are parallel, aligned at two ends and spaced apart, and all of the fourth metal lines have one end connected to one side of the fourth parallel end, which is further connected to the fourth pad.
12. The test structure of claim 11, wherein the fourth parallel end includes a sixth portion and a seventh portion, all of the fourth metal lines are connected at one side of the sixth portion, one end of the seventh portion is connected to the other side of the sixth portion, and the other end of the seventh portion is connected to the fourth pad.
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