CN115172146A - Method for manufacturing compound semiconductor wafer - Google Patents
Method for manufacturing compound semiconductor wafer Download PDFInfo
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- CN115172146A CN115172146A CN202210910663.1A CN202210910663A CN115172146A CN 115172146 A CN115172146 A CN 115172146A CN 202210910663 A CN202210910663 A CN 202210910663A CN 115172146 A CN115172146 A CN 115172146A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Abstract
The invention provides a manufacturing method of a compound semiconductor wafer, which comprises the following steps: providing a substrate, and sequentially forming an epitaxial structure, a front device structure and a lead-out metal layer of a compound semiconductor wafer on the front surface of the substrate; covering the front device structure to form a passivation protection layer; temporarily bonding the front surface of the compound semiconductor wafer with a first support substrate; performing a back side process on the compound semiconductor wafer; debonding the wafer from the first support substrate and attaching the backside of the wafer to the second support substrate by a heat sensitive adhesive; forming a metal bump on the front surface of the wafer, wherein the metal bump is connected with the lead-out metal layer; the wafer is separated from the second support substrate. The invention executes the formation step of the front metal bump after the back process is finished, is convenient for the stacked welding package between the compound semiconductor wafer and another wafer, is beneficial to improving the integration level of the device, reduces the packaging bonding wires of the assembly and ensures the reliability of the packaged device at the same time.
Description
Technical Field
The invention belongs to the field of semiconductor device manufacturing, and particularly relates to a manufacturing method of a compound semiconductor wafer.
Background
With the need of functional integration, compound semiconductor devices are gradually developed into Wafer level packages (Wafer level packages), which are usually implemented by Wafer stack bonding, and circuit connections between chips of different wafers are generally implemented by stacking and interconnection wiring methods, so that space waste caused by conventional gold wire bonding can be avoided. The wafer level packaging technology has certain advantages in the aspects of realizing chip multifunctional integration, improving chip integration level, reducing signal transmission and power consumption, improving chip heat dissipation performance and the like.
A third-generation compound semiconductor device represented by gallium nitride (GaN) has high electron mobility and a wide operating frequency range compared to a silicon device, and is gradually replaced in the field of high-frequency power. However, due to the rf device, the substrate is usually required to be thinned in the back end of line process, and the thinned wafer or ultra-thin wafer has flexibility, fragility and easy warpage. Currently, a temporary bonding process is often used in compound semiconductor-based wafer or ultra-thin wafer processing to perform a back side process including thinning and back side metallization, and then debonding (Debond) the wafer from the carrier. When the wafer is thinned to a thin wafer with the thickness of less than 100 micrometers, even to an ultrathin wafer with the thickness of 25-75 micrometers, and then is subjected to a back through hole etching process and a back metallization process, the wafer becomes sensitive to stress in the bonding separation (Debond) process, so that the selection of the bonding glue and the process related to the temporary bonding technology is very critical to the yield of the wafer. In addition, the chip stacking structure requires a connection structure to realize circuit connection between the chips, such as a front metal bump. In the manufacturing of the wafer with the front metal bump, it is usually necessary to transfer the wafer with the back process to the second support substrate again, so that the front surface of the wafer faces upward, and then the front metal bump is manufactured.
Therefore, it is necessary to provide a method for fabricating a compound semiconductor wafer with front metal bumps.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for fabricating a compound semiconductor wafer, which is used to solve the problems of the prior art that metal bumps are fabricated on the front surface of a wafer with a back-side through hole, bonding paste/bonding wax residues in the through hole are easily generated during the separation process from a second supporting substrate, and the yield or yield is low due to micro-cracking or fracture of the wafer.
To achieve the above and other related objects, the present invention provides a method for manufacturing a compound semiconductor wafer, comprising:
providing a substrate, and sequentially forming an epitaxial structure, a front device structure and a lead-out metal layer of a compound semiconductor wafer on the front surface of the substrate;
forming a passivation protection layer on the front device structure covering the compound semiconductor wafer;
making the front surface of the compound semiconductor wafer face a first supporting substrate and temporarily bond with the first supporting substrate;
performing a backside process on the compound semiconductor wafer, comprising:
thinning the back surface of the compound semiconductor wafer to obtain a thin wafer;
carrying out back through hole etching on the wafer;
back metallization is carried out on the wafer;
the thin wafer and the first supporting substrate are bonded in a debonding mode, the thin wafer is transferred to a second supporting substrate, and the back face of the thin wafer is fixed on the second supporting substrate through a thermosensitive adhesive;
forming a metal bump on the front surface of the wafer, wherein the metal bump is connected with the lead-out metal layer;
separating the wafer from the second support substrate.
Optionally, the substrate includes one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a sapphire substrate, and the thickness of the wafer is in a range from 25 micrometers to 100 micrometers.
Optionally, the material of the metal bump is one metal material selected from copper, gold, indium and tin, or an alloy of two or more metals, and the height of the metal bump is not less than 50 μm.
Optionally, the step of forming the metal bump includes: forming an opening on the passivation protective layer through an etching process, wherein the opening exposes the electrode part of the lead-out metal layer; and sequentially forming an under bump metallization seed layer, an electroplated metal column and a welding metal layer which are electrically connected with the electrode part of the lead-out metal layer on the front surface of the wafer from bottom to top.
Optionally, performing a backside process on the compound semiconductor wafer further comprises: and defining a cutting channel area on the back surface of the thin wafer through a photoetching process, wherein the metal bump is arranged close to the cutting channel area of the thin wafer and positioned at the periphery of a single semiconductor device, the width of the metal bump is not less than 30 microns, and the distance between the metal bump and the cutting channel is not less than 10 microns.
Optionally, after the step of performing a back surface process on the compound semiconductor wafer, adhering the back surface of the wafer to the second support substrate by using a heat-sensitive adhesive; and then, forming metal bumps on the front surface of the wafer, wherein the heat-sensitive adhesive is a double-sided heat-sensitive adhesive tape.
Optionally, the double-sided thermal adhesive is debonded through a heating process, and the thin wafer is separated from the second support substrate, wherein the temperature resistance of the thermal adhesive is not lower than 120 ℃.
Optionally, the step of debonding the double-sided thermal tape comprises: and adjusting the heating temperature, and maintaining the temperature difference between the front surface and the back surface of the double-sided thermal sensitive adhesive tape to be not more than +/-2 ℃, so that the front surface and the back surface of the double-sided thermal sensitive adhesive tape are simultaneously debonded.
Optionally, the front surface of the compound semiconductor wafer is temporarily bonded to the first support substrate via a bonding paste or a bonding wax, and the bonding paste or the bonding wax is resistant to a temperature of 180 ℃ or higher.
Optionally, the manufacturing method further includes: and debonding the wafer from the first support substrate by heating treatment, and performing surface cleaning on the front surface of the wafer.
As described above, the present invention provides a method for manufacturing a compound semiconductor wafer, which has the following advantageous effects:
according to the invention, after the back face of the wafer is thinned and the back face is metalized, the wafer is transferred to the second supporting substrate by adopting the thermosensitive adhesive, so that the front face of the wafer faces upwards, and then the step of forming the metal bump on the front face of the wafer is executed, so that compared with the conventional temporary bonding process, the stress caused by the wafer transfer step can be reduced, and the damage or the fragmentation caused by the sensitivity of the wafer to the stress can be avoided; meanwhile, the defect that bonding glue or bonding wax cannot be completely removed when entering the back through hole in the conventional bonding process is avoided, the cleaning process is simplified, and the product yield is improved.
The invention forms the metal lug on the front of the chip while making the compound semiconductor wafer, facilitate the compound semiconductor wafer and another semiconductor wafer to weld and pack in the heap, reduce the packaging bonding wire of the assembly, guarantee the reliability of the encapsulated device, help improving the integration level of the device at the same time, realize the multi-functional integration of the chip.
Drawings
FIG. 1 is a flow chart of a method for fabricating a compound semiconductor wafer according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a method for manufacturing a compound semiconductor wafer, comprising the steps of:
first, step S100 is performed to provide a substrate, and an epitaxial structure, a front device structure, and a lead-out metal layer of a compound semiconductor wafer are sequentially formed on a front surface of the substrate.
The substrate may comprise one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate and a sapphire substrate, and accordingly, the material used to form the compound semiconductor wafer may be a group III-V compound semiconductor material, such as InP, gaAs, gaN.
Further, after the epitaxial process, a surface cleaning process may be performed on the compound semiconductor wafer to remove surface contamination and particles, thereby improving the quality of the semiconductor device.
As an example, step S100 may include a photolithography process, an evaporation process, an annealing process, or a similar front surface process of the wafer to form the front surface device structure, the metal electrode, and the extraction metal layer.
As an example, the compound semiconductor device unit may be a III-V compound based semiconductor device unit, such as an InP device, a GaAs device, a GaN device. In this embodiment, a GaN-based radio frequency device unit may be formed on the substrate.
As an example, the lead metal layer includes a source lead electrically connected to the source, a drain lead electrically connected to the drain, and a gate lead electrically connected to the gate electrode, and an electrode portion.
Next, step S110 is performed to form a passivation protection layer on the front device structure of the compound semiconductor wafer.
By way of example, the passivation layer may be formed on the surface of the front device structure by, for example, a physical vapor deposition or chemical vapor deposition process, for surface passivation, and also to mitigate damage to the device surface caused by stress non-uniformity in a subsequent backside process.
With continued reference to fig. 1, step S120 is performed to make the front surface of the compound semiconductor wafer face the first supporting substrate and perform temporary bonding with the first supporting substrate.
As an example, the material of the support substrate may be a quartz material, a glass material, a semiconductor material, or a metal material.
Specifically, step S120 includes: and coating bonding glue or bonding wax on the front surface of the compound semiconductor wafer, so that the front surface of the compound semiconductor wafer faces to the first supporting substrate and is bonded with the first supporting substrate to form a bonding piece. Since the temporary bonding system composed of the bonding paste or the bonding wax is subjected to high temperature of back surface processing in the subsequent back surface metallization process, the bonding paste or the bonding wax needs to have thermal stability. Specifically, the bonding glue or bonding wax can resist the temperature of more than 180 ℃.
Next, step S130 is performed to perform a back process on the compound semiconductor wafer. Specifically, step S130 includes: thinning the back of the substrate by using the bonding sheet obtained in the step S120 to obtain a sheet wafer; carrying out back through hole etching on the wafer; back side metallization is performed on the wafer.
As an example, step S130 further includes: the back of the substrate can be polished after the back of the substrate is thinned, so that the roughness and the uniformity of the processed surface are improved, and in the thinning and surface polishing processes, the supporting substrate provides the whole support for the substrate, so that the damage to a device is avoided.
As an example, the thinned substrate is polished to obtain a thin wafer bonded to the first supporting substrate, wherein the thin wafer has a thickness in a range of 25 micrometers to 100 micrometers. In the present embodiment, the thickness of the wafer is in a range from 25 micrometers to 100 micrometers, for example, 75 micrometers.
As an example, the back side via etching is performed on a wafer, and the method at least comprises the following steps: and forming a through hole penetrating from the back of the wafer to the contact metal layer by adopting an etching process, wherein the through hole is used for leading out the back of the device unit in the wafer.
As an example, the back side of the wafer is metallized, comprising at least the following steps: forming a metal seed layer on the back surface of the wafer; and forming a metal coating on the back surface of the wafer.
As an example, performing a backside process on the compound semiconductor wafer further comprises: and defining a cutting path area on the back surface of the thin wafer through a photoetching process.
As shown in fig. 1, a step S140 is performed to debond the sheet wafer from the first support substrate, and transfer the sheet wafer to a second support substrate and adhere the back surface of the sheet wafer to the second support substrate by using a heat-sensitive adhesive.
As an example, the bonding paste or the bonding wax is heat-treated with a hot plate, the thin wafer is debonded from the first support substrate, and the thin wafer is transferred to a second support substrate and the back surface of the thin wafer is attached to the second support substrate by a heat-sensitive adhesive.
As an example, the front side of the wafer after being debonded from the second support substrate is subjected to surface cleaning.
Specifically, the back side of the sheet wafer is adhered to the second support substrate to form a bonding sheet, wherein the heat-sensitive adhesive is a double-sided heat-sensitive adhesive tape. The back surface of the wafer is adhered to the second supporting substrate, and the through hole on the back surface of the wafer is not adhered with the heat-sensitive adhesive, so that the cleaning step of the surface of the wafer after separation is simplified. Preferably, the temperature resistance of the heat-sensitive adhesive is not lower than 120 ℃.
As an example, the second support substrate has a size slightly larger than or equal to a size of a thin sheet wafer to provide support for the thin sheet wafer.
As an example, the front side of the wafer is wet cleaned to remove the bonding glue/bonding wax remained on the front side of the wafer after the first supporting substrate is debonded from the wafer
Next, step S150 is performed to form metal bumps on the front surface of the wafer, where the metal bumps are connected to the metal lead-out layer and are electrically coupled to an integrated circuit or another chip, for example, by bonding with bonding portions of a silicon chip and/or a memory chip, so as to facilitate stack-type soldering packaging of the compound semiconductor wafer and another semiconductor wafer, which is beneficial to improving the integration level of the compound semiconductor device and multi-functional integration.
As an example, step S150 further includes: and forming an opening on the passivation protective layer through an etching process, wherein the opening exposes the electrode part of the lead-out metal layer. In this embodiment, a pattern of openings is defined on the passivation layer surface by a photolithography process.
As an example, the metal bump is made of one metal material selected from copper, gold, indium, and tin, or an alloy of two or more metals.
As an example, the metal bump may be formed on the front side of the sheet wafer, disposed close to the scribe line region of the sheet wafer and located at the periphery of the single semiconductor device unit, and the distance between the metal bump and the scribe line region is not less than 10 micrometers.
As an example, the height of the metal bump is not less than 50 micrometers, for example, 60 micrometers or more, and the width of the metal bump is not less than 30 micrometers.
Since the obtained wafer becomes fragile after the back process, the metal bumps positioned on the front surface of the chip are formed after the back process comprising thinning and back metallization, and the warping or damage of the wafer easily caused by stress sensitivity in the back process is avoided.
As an example, step S150 further includes: and after forming an opening on the passivation protective layer, sequentially forming an under bump metallization seed layer, an electroplated metal column and a welding metal layer which are electrically connected with the electrode part of the lead-out metal layer on the front surface of the wafer from bottom to top. In this embodiment, the photoresist remaining after the etching process forms a metal bump in the pattern region defined by the opening and the photoresist.
Step S160 is executed to separate the sheet wafer from the second support substrate.
In this embodiment, the bonding sheet formed by the sheet wafer and the second support substrate is placed on the hot plate, so that the double-sided thermal tape is debonded, and the double-sided thermal tape is melted or degraded by heat to reduce or eliminate the viscosity, so that the sheet wafer and the second support substrate are separated from each other. Because the adhesive is reduced or loses viscosity by adopting the heating treatment, compared with the conventional bonding glue or bonding wax, the stress caused by the wafer transfer technology is reduced, and the adhesive residue is reduced, so that the wafer warpage possibly caused by the residual adhesive before the surface of the wafer is cleaned is avoided. In this embodiment, the step of debonding the double-sided thermal tape includes: and adjusting the heating temperature, and maintaining the temperature difference between the front surface and the back surface of the double-sided thermal sensitive adhesive tape to be not more than +/-2 ℃, so that the front surface and the back surface of the double-sided thermal sensitive adhesive tape are simultaneously debonded, and the double-sided thermal sensitive adhesive tape can be peeled off at one time.
After step S160, the method for manufacturing a compound semiconductor wafer further includes: after the compound semiconductor wafer and another semiconductor wafer are stacked and bonded, a dicing process is performed based on the dicing street regions, which may be defined in the front and back side metallization process. For example, the wafer level dicing process may be performed using laser dicing and/or knife-wheel mechanical dicing.
As an example, the manufacturing method further comprises the steps of: before performing the dicing process based on the scribe line region, a surface cleaning may be performed on the package-on-package structure including the wafer.
As described above, the method for manufacturing a compound semiconductor wafer according to the present invention has the following advantageous effects:
according to the invention, after the back face of the wafer is thinned and the back face is metalized, the wafer is transferred to the second supporting substrate by adopting the thermosensitive adhesive, so that the front face of the wafer faces upwards, and then the step of forming the metal bump on the front face of the wafer is executed, so that compared with the conventional temporary bonding process, the stress caused by the wafer transfer step can be reduced, and the damage or the fragmentation caused by the sensitivity of the wafer to the stress can be avoided; meanwhile, the defect that bonding glue or bonding wax cannot be completely removed when entering the back through hole in the conventional bonding process is avoided, the cleaning process is simplified, and the product yield is improved.
The invention forms the metal lug on the front of the chip while making the compound semiconductor wafer, facilitate the compound semiconductor wafer and another semiconductor wafer to weld and pack in the heap, reduce the packaging bonding wire of the assembly, guarantee the reliability of the encapsulated device, help improving the integration level of the device at the same time, realize the multi-functional integration of the chip.
Therefore, the present invention effectively overcomes several disadvantages of the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method of fabricating a compound semiconductor wafer, the method comprising:
providing a substrate, and sequentially forming an epitaxial structure, a front device structure and a lead-out metal layer of a compound semiconductor wafer on the front surface of the substrate;
forming a passivation protection layer on the front device structure covering the compound semiconductor wafer;
making the front surface of the compound semiconductor wafer face a first supporting substrate and temporarily bond with the first supporting substrate;
performing a backside process on the compound semiconductor wafer, comprising:
thinning the back surface of the compound semiconductor wafer to obtain a thin wafer;
carrying out back through hole etching on the wafer;
back metallization is carried out on the wafer;
debonding the sheet wafer from the first support substrate, and transferring the sheet wafer to a second support substrate and attaching the backside of the sheet wafer to the second support substrate by a heat sensitive adhesive;
forming a metal bump on the front surface of the wafer, wherein the metal bump is connected with the lead-out metal layer;
separating the wafer from the second support substrate.
2. The method of claim 1, wherein the substrate comprises one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a sapphire substrate, and the wafer has a thickness in a range of 25-100 μm.
3. The method according to claim 1, wherein the metal bump is made of one or more metal materials selected from copper, gold, indium, and tin, and has a height of not less than 50 μm.
4. The method of claim 1, wherein the step of forming the metal bump comprises: forming an opening on the passivation protective layer through an etching process, wherein the opening exposes the electrode part of the lead-out metal layer; and sequentially forming an under bump metallization seed layer, an electroplated metal column and a welding metal layer which are electrically connected with the electrode part of the lead-out metal layer on the front surface of the wafer from bottom to top.
5. The manufacturing method according to claim 1, wherein a back surface process is performed on the compound semiconductor wafer, further comprising: and defining a cutting channel area on the back surface of the thin wafer through a photoetching process, wherein the metal bump is arranged close to the cutting channel area of the thin wafer and positioned at the periphery of a single semiconductor device, the width of the metal bump is not less than 30 microns, and the distance between the metal bump and the cutting channel is not less than 10 microns.
6. The production method according to claim 1, wherein after the step of performing a back surface process on the compound semiconductor wafer, the back surface of the sheet wafer is adhered to the second support substrate with a heat-sensitive adhesive; and then, forming metal bumps on the front surface of the wafer, wherein the heat-sensitive adhesive is a double-sided heat-sensitive adhesive tape.
7. The manufacturing method according to claim 6, wherein the double-sided thermal adhesive is debonded by a heating process to separate the sheet wafer from the second support substrate, wherein the thermal adhesive is resistant to a temperature of not less than 120 ℃.
8. The method of manufacturing according to claim 7, wherein the step of debonding the double-sided thermal tape comprises: and adjusting the heating temperature, and maintaining the temperature difference between the front surface and the back surface of the double-sided thermal sensitive adhesive tape to be not more than +/-2 ℃, so that the front surface and the back surface of the double-sided thermal sensitive adhesive tape are simultaneously debonded.
9. The method of claim 1, wherein the front surface of the compound semiconductor wafer is temporarily bonded to the first support substrate via a bonding paste or a bonding wax, and the bonding paste or the bonding wax is resistant to a temperature of 180 ℃ or higher.
10. The method of manufacturing of claim 9, further comprising: and debonding the wafer from the first support substrate by heating treatment, and performing surface cleaning on the front surface of the wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210910663.1A CN115172146A (en) | 2022-07-29 | 2022-07-29 | Method for manufacturing compound semiconductor wafer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210910663.1A CN115172146A (en) | 2022-07-29 | 2022-07-29 | Method for manufacturing compound semiconductor wafer |
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2022
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