JP2008187177A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily make a semiconductor chip of a thin film in high-density packaging. <P>SOLUTION: A semiconductor device is formed of: a passivation film on an element forming surface of the semiconductor chip of an SOI structure; an electrode on a predetermined position on the element forming surface; and a first resin layer to coat the element forming surface and to expose at least a part of the electrode surface, and coated with an insulating layer of the SOI structure with a second resin layer. The electrode is constituted of: an externally leading-out wiring formed on the element forming surface; and a bump formed right above the externally leading-out wiring. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor wafer or semiconductor chip formed into a thin film (layer) and a method for forming the same.

In recent years, ICs or LSIs have become more highly integrated and larger in capacity. As the CSP (Chip Size Package) of a semiconductor chip used for mounting on a portable device or the like, it is indispensable to reduce the mounting area and the height thereof with the downsizing and high performance of the device. ing. Furthermore, MCP (Multi-Chip Package) in which a plurality of semiconductor chips are mounted in one has been put into practical use.

In addition, with the rapid spread of information technology, the demand for systematization of semiconductor devices constituting information processing apparatuses is increasing. In addition, there is high expectation for mounting technology for electronic system integration that integrates and systematizes various functional blocks including multiple silicon semiconductor chips, semiconductor devices composed of optical devices and high-frequency devices using compound semiconductors, etc. It is coming.

For high-density mounting of the semiconductor chip as described above, it is essential to reduce the thickness of the semiconductor chip, and the thickness thereof has been required to be 50 μm or less.

The thinning of the semiconductor chip is usually performed by grinding or etching the back surface of the semiconductor chip at the semiconductor wafer stage. Such a technique is described in, for example, Japanese Patent Application Laid-Open Nos. 8-316194 and 2001-223202. The conventional technique will be briefly described below with reference to FIG.

As shown in FIG. 10A, a protective tape 102 is attached to the surface of the semiconductor wafer 101. Then, the protective tape 102 side is vacuum-fixed to the grinding suction stage 103, and while grinding the suction stage 103 is rotated, the back surface of the semiconductor wafer 101 is brought into contact with the rotating grindstone 104 to perform grinding. Then, the semiconductor wafer 101 is set to a predetermined thickness, for example, about 100 μm.

After doing so, the semiconductor wafer is removed from the grinding apparatus. Thus, as shown in FIG. 10B, the protective tape 102 is attached to the surface of the thinned semiconductor wafer 101a. Here, the thinned semiconductor wafer 101 a is warped by the protective tape 102.

Next, the protective tape 102 is peeled from the thinned semiconductor wafer 101 a, and the semiconductor wafer 101 a is diced to be separated into semiconductor chips 105. That is, as shown in FIG. 10C, the enlargement sheet 106 is pasted on the rear surface side and then mounted on a dicing apparatus, and the front surface side of the semiconductor wafer 101a is diced. Then, the expansion sheet 106 is stretched and separated into semiconductor chips 105.

JP-A-8-316194 JP 2001-223202 A

As described above, in high-density mounting of semiconductor devices, it is essential to reduce the thickness of a semiconductor chip, particularly in CSP. For example, the thickness of the semiconductor chip is required to be 50 μm or less.

However, in the conventional technique described with reference to FIG. 10, the warp generated in the thinned semiconductor wafer increases. When the warpage of the semiconductor wafer is increased, the semiconductor chip is frequently damaged in the dicing process, and the yield of the semiconductor device is significantly reduced. This is because the semiconductor wafer cannot be successfully mounted on the stage of the dicing apparatus due to the warp.

Furthermore, when the semiconductor wafer is thinned to about 20 μm, a wet etching process must be added after the grinding. In this case, if the warp as described above occurs, the wet etching process causes a large variation in the etching amount. For this reason, a large amount of non-standard semiconductor chips are generated in the thickness, and the yield of the semiconductor device is lowered.

The above-mentioned problem caused by the warpage of the semiconductor wafer becomes more apparent as the diameter of the semiconductor wafer increases (for example, 12-inch Φ).

SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor device and a method for manufacturing the same that facilitate the thinning of a semiconductor chip. Furthermore, another object of the present invention is to simplify a technique for high-density mounting of a semiconductor device and to facilitate its mass production application.

To this end, the method of manufacturing a semiconductor device according to the present invention includes a step of forming an electrode at a predetermined position on an element formation surface of a semiconductor wafer, a first resin layer covering the element formation surface, A step of exposing a part, a step of attaching a reinforcing plate to the first resin layer or the exposed electrode surface through an adhesive, and grinding or etching the back surface of the semiconductor wafer to thin the semiconductor wafer And a step of covering the back surface of the semiconductor wafer after the thinning with a second resin layer.

Alternatively, in the method of manufacturing a semiconductor device of the present invention, a step of forming an electrode at a predetermined position on an element formation surface of a semiconductor wafer and a groove extending inside the semiconductor wafer are formed in a predetermined region of the element formation surface. Forming a first resin layer filling the groove and covering the element forming surface to expose at least a part of the electrode surface; and adhering to the first resin layer or the exposed electrode surface A step of attaching a reinforcing plate through a material, a step of grinding or etching the back surface of the semiconductor wafer to thin the semiconductor wafer, and covering the back surface of the semiconductor wafer after the thinning with a second resin layer And a process.

Alternatively, the method of manufacturing a semiconductor device according to the present invention includes a step of forming an electrode at a predetermined position on an element formation surface of a semiconductor wafer, a step of attaching a reinforcing plate to the electrode surface via an adhesive, and the semiconductor wafer. Filling the first resin layer in the gap with the reinforcing plate, grinding or etching the back surface of the semiconductor wafer to thin the semiconductor wafer, and forming the back surface of the semiconductor wafer after thinning Coating with two resin layers. Here, the reinforcing plate is made of porous ceramics.

Alternatively, the method of manufacturing a semiconductor device of the present invention includes a step of forming an electrode at a predetermined position on an element formation surface of a semiconductor wafer having an SOI structure, a step of forming a first resin layer on the element formation surface, and the SOI A step of grinding or etching the back surface of the semiconductor wafer using an insulating layer having a structure as an etching stopper, and a step of covering the exposed insulating layer with a second resin layer.

Then, after forming the second resin layer, the reinforcing plate is immersed in an organic solution, the adhesive is melted through the holes, and the reinforcing plate is peeled off.

In addition, the semiconductor wafer sealed with the first resin layer and the second resin layer is cut into semiconductor chips. Alternatively, after forming the second resin layer, the semiconductor wafer sealed with the first resin layer and the second resin layer is cut into semiconductor chips, and the reinforcing plate is immersed in an organic solution. The adhesive is melted through the hole to peel off the reinforcing plate.

The semiconductor device of the present invention includes a semiconductor chip formed by laminating an insulating layer and a semiconductor layer, the silicon layer of the semiconductor chip has an element formation surface, and a passivation film is formed on the element formation surface. An electrode is formed at a predetermined position on the element forming surface, a first resin layer covering the element forming surface and exposing at least a part of the electrode surface is formed, and the insulating layer of the semiconductor chip is formed It is characterized by being covered with a second resin layer.

Alternatively, in the semiconductor device of the present invention, the electrode may be composed of an external extraction wiring formed on the element formation surface and a bump formed immediately above the external extraction wiring.

Alternatively, in the semiconductor device of the present invention, the semiconductor layer may be Si or SiGe.

Alternatively, in the semiconductor device of the present invention, the first resin layer and the second resin layer may be made of the same material. Alternatively, in the semiconductor device of the present invention, the first resin layer and the second resin layer may have the same thickness.

According to the present invention, there is no warping of the semiconductor wafer when the semiconductor wafer is thinned. In addition, the variation in the thickness of the semiconductor wafer after thinning is greatly reduced. Further, there is no damage to the wafer caused by the handling of the semiconductor wafer in the thinning process.

Further, the present invention facilitates high-density mounting of semiconductor chips. When the CSP is formed according to the present invention, the semiconductor chip can be easily and very thinned. Therefore, the solder ball connection portion which has occurred in the prior art due to the difference in thermal expansion coefficient from the mother board on which the CSP is mounted. Cracks can be greatly reduced, and mounting reliability can be greatly improved. In this way, reliability after mounting is greatly improved.

Furthermore, according to the present invention, the manufacturing process of the semiconductor device is simplified, and mass production application of high-density mounting of the semiconductor device is facilitated.

Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 and FIG. 2 are cross-sectional views in order of manufacturing steps for thinning a semiconductor wafer. The semiconductor device of the present invention is shown in the above description of the process.

As shown in FIG. 1A, for example, semiconductor elements and internal wiring (not shown) are formed on the surface of a semiconductor wafer 1 having a thickness of about 8 μm and a thickness of about 800 μm. As shown in FIG. 1B, a passivation film 2 is formed on the surface of the semiconductor wafer 1 and a wiring 3 for external extraction is formed. Then, bumps 4 are formed on the wiring 3. The bump 4 is made of gold, copper or solder by plating. These become the electrodes. After this, as shown in FIG. 1B, a surface sealing resin 5 as a first resin layer is formed on the entire surface by a known method. Here, the height of the bump 4 is about 20 μm, and the thickness of the surface sealing resin 5 is about the same as 20 μm. The surface sealing resin 5 is a thermosetting resin.

Next, as shown in FIG. 1C, the surface sealing resin 5 surface or the bump 4 surface is attached to the surface of the reinforcing plate 6 via an adhesive 7 by a thermocompression bonding method. Here, the reinforcing plate 6 is a porous alumina plate (ceramic substrate) having a thickness of 10 mm.

Next, as shown in FIG. 1 (d), the back side of the semiconductor wafer 1 is ground with a grindstone 8. After this, wet etching is added using a mixed chemical solution containing nitric acid (HNO3) and hydrofluoric acid (HF) to form an extremely thin semiconductor wafer 1a having a thickness of about 10 μm.

Next, as shown in FIG. 2A, a back surface sealing resin 9 as a second resin layer is formed on the entire back surface of the semiconductor wafer 1a by a known method. Here, the back surface sealing resin 9 is made of the same material as the surface sealing resin 5 described above, and the thickness thereof is preferably about 20 μm.

After doing so, the reinforcing plate 6 is cut off. This separation method is as follows. The structure in the state shown in FIG. 2A is immersed in a heated organic solution. Here, the organic solution is a chemical solution that selectively melts the adhesive 7. When immersed in the organic solution, the chemical solution reaches the adhesive 7 through the holes of the reinforcing plate 6 and melts the adhesive 7. The reinforcing plate 6 is separated by melting the adhesive material 7.

In this way, as shown in FIG. 2B, bumps 4 are formed on the surface of the semiconductor wafer 1a thinned to about 10 μm, and the space between the bumps 4 is sealed with a surface sealing resin 5 having a thickness of about 20 μm. Thus, a structure in which the back surface is sealed with the back surface sealing resin 9 having a thickness of about 20 μm is completed. The separation of the structure shown in FIG. 2B into semiconductor chips will be described later.

In the present invention, even when the semiconductor wafer 1a becomes extremely thin, no warping occurs. This is because, firstly, the reinforcing plate 6 has characteristics close to rigidity and has little bending. The semiconductor wafer 1 is supported by the reinforcing plate 6 from the previous stage of the grinding process. Secondly, in the process of thinning the semiconductor wafer 1, the front and back surfaces are sequentially sealed with resin. Moreover, the front / back surface sealing resins are made of the same material and are formed to have the same thickness.

Next, a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, the surface of the semiconductor wafer is half-cut in advance to form a groove. 3 and 4 are cross-sectional views in the order of manufacturing steps for thinning a semiconductor wafer. Here, the same components as those in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 3A, a passivation film 2 is formed on the surface of a semiconductor wafer 1 on which semiconductor elements and wirings are formed to form wirings 3. Then, bumps 4 are formed on the wiring 3. Here, the height of the bump 4 is about 30 μm. Thereafter, the surface of the semiconductor wafer 1 is half-cut using a dicing apparatus or the like to form the grooves 10. Here, the width and depth of the groove 20 are 50 μm.

Next, as shown in FIG. 3B, a surface sealing resin 5 is formed on the entire surface by a known method to seal between the bumps 4. At the same time, the groove 10 is filled with the surface sealing resin 5. Here, the thickness of the surface sealing resin 5 is also about 30 μm.

Next, as shown in FIG. 3C, the surface sealing resin 5 surface or the bump 4 surface is attached to the surface of the reinforcing plate 6 with an adhesive 7 by a thermocompression bonding method. Here, the reinforcing plate 6 is a porous alumina plate, and the thickness thereof is 10 mm.

Next, as shown in FIG. 3D, the back side of the semiconductor wafer 1 is ground with a grindstone 8. After this, wet etching is added using a mixed chemical solution containing nitric acid (HNO3) and hydrofluoric acid (HF) to form an extremely thin semiconductor chip 11 having a thickness of about 10 μm. In this grinding step, the surface sealing resin 5 is exposed from the groove 10 part.

Next, as shown in FIG. 4A, a back surface sealing resin 9 is formed on the entire back surface side of the semiconductor chip 11 by a known method. Here, the back surface sealing resin 9 is made of the same material as the surface sealing resin 5 described above, and the thickness thereof is preferably about 30 μm.

After doing so, the reinforcing plate 6 is cut off in the same manner as described in the first embodiment. That is, the structure in the state shown in FIG. 4A is immersed in a heated organic solution. The chemical solution reaches the adhesive 7 through the hole of the reinforcing plate 6 and melts the adhesive 7. The reinforcing plate 6 is separated by melting the adhesive material 7.

Thus, as shown in FIG. 4B, bumps 4 are formed on the surface of the semiconductor chip 11 thinned to about 10 μm, and the space between the bumps 4 is sealed with a surface sealing resin 5 having a thickness of about 30 μm. Thus, a structure in which the back surface is sealed with the back surface sealing resin 9 having a thickness of about 30 μm is completed.

In this embodiment, the semiconductor wafer 1 is separated into semiconductor chips 11 after the polishing. This facilitates the manufacture of the semiconductor device as will be described later. Unlike the first embodiment, after separation into semiconductor chips, all regions including the side portions of the semiconductor chip can be resin-sealed. Naturally, the same effect as described in the first embodiment is produced.

In the first (2) embodiment, in the formation of the surface sealing resin 5, the surface sealing resin 5 is deposited from the beginning in accordance with the height of the bumps 4. Alternatively, the surface sealing resin 5 may be coated on the entire surface, and then the surface may be ground to expose the surface of the bump 4.

Next, a third embodiment of the present invention will be described with reference to FIGS. 5 and 6 are cross-sectional views in the order of manufacturing steps for thinning a semiconductor wafer. Here, the same components as those in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 5A, a passivation film 2 is formed on the surface of a semiconductor wafer 1 having a thickness of, for example, 8 inches Φ and a thickness of about 800 μm to form a wiring 3. Then, bumps 4 are formed on the wiring 3 as shown in FIG. Here, the height of the bump 4 is about 30 μm.

Next, as shown in FIG. 5C, the back surface of the semiconductor wafer 1 is faced up, and the surface of the bump 4 is attached to the surface of the reinforcing plate 6 with an adhesive 7 by a thermocompression bonding method. Here, the reinforcing plate 6 is a porous alumina plate, and the thickness thereof is about 10 mm.

Next, as shown in FIG. 5D, the gap formed by the adhesive 4 on the bump 4 and the reinforcing plate 6 of the semiconductor wafer 1 is filled with resin. In this way, the surface sealing resin 5a is formed.

Next, as shown in FIG. 6A, the back surface side of the semiconductor wafer 1 is ground by the grindstone 8 as described in the first embodiment. After this, wet etching is added using a mixed chemical solution containing nitric acid (HNO3) and hydrofluoric acid (HF) to form an extremely thin semiconductor wafer 1a having a thickness of about 10 μm.

Next, as shown in FIG. 6B, a back surface sealing resin 9 is formed on the entire back surface side of the semiconductor wafer 1a by a known method. Here, the back surface sealing resin 9 is made of the same material as the surface sealing resin 5 described above, and the thickness thereof is preferably about 30 μm.

In this way, as shown in FIG. 6B, the surface on the semiconductor wafer 1a thinned to about 10 μm and the reinforcing plate 6 are sealed with a surface sealing resin 5a having a thickness of about 30 μm. A structure in which the back surface is also sealed with the back surface sealing resin 9 having a thickness of about 30 μm is completed.

Next, a method for separating such a structure into semiconductor chips will be described with reference to FIGS. FIG. 7 shows a case where the semiconductor wafer supported by the reinforcing plate 6 is diced together with the sealing resin to form a semiconductor chip. FIG. 8 shows the structure after the resin-sealed semiconductor wafer is separated from the reinforcing plate. In this case, the semiconductor chip is separated after the steps described with reference to FIGS.

As shown in FIG. 7A, the back surface sealing resin 9, the semiconductor wafer 1a, and the surface sealing resin 5a of the structure formed on the reinforcing plate 6 via the adhesive 7 are cut by dicing to form semiconductor chips. Separately, the resin-encapsulated chip 12 is formed. As shown in FIG. 7B, for example, ultraviolet rays are irradiated from the back surface of the transparent reinforcing plate 6, and the resin-encapsulated chip 12 is peeled from the adhesive material 7. This peeling may be performed by immersing in an organic solution.

As shown in FIG. 8 (a), the other method is similar to that described with reference to FIG. 2 (b), in which the adhesive 7 on the reinforcing plate 6 is eluted in the heated organic solution, and the resin sealing is performed. Separate the semiconductor wafer. In this way, the semiconductor wafer 1a that is sealed with the front surface sealing resin 5a and the back surface sealing resin 9, that is, the resin-sealed wafer 13 is formed. Then, as shown in FIG. 8B, a predetermined region of the resin-encapsulated wafer 13 is diced and separated into resin-encapsulated chips 12.

In this way, as shown in FIG. 8B, bumps 4 are formed on the surface of the semiconductor chip 11 thinned to about 10 μm, and the space between the bumps 4 is sealed with a surface sealing resin 5a having a thickness of about 20 μm. Thus, the resin-encapsulated chip 12 whose back surface is sealed with the back surface sealing resin 9 having a thickness of about 20 μm is completed.

In this embodiment, control of the thickness of the surface sealing resin 5a is simplified. The heights of the bumps 4 and the surface sealing resin 5a can be made exactly the same. For this reason, in the COC (Chip on Chip) technology or the like, it becomes easy to join a plurality of resin-encapsulated chips with the bumps 4. In addition, the effects described in the first embodiment are similarly generated.

Next, a fourth embodiment of the present invention will be described with reference to FIG. In this embodiment, a semiconductor wafer having an SOI structure is used. However, the SOI structure is not limited to a silicon layer formed on an insulating film. For example, a semiconductor layer such as a SiGe layer is formed on the insulating film. Also included. FIG. 9 is a cross-sectional view in order of the manufacturing process for thinning the semiconductor wafer. In this case, the reinforcing plate 6 described above may not be used. Here, the same components as those in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 9A, a buried insulating layer 15 and an SOI layer 16 are stacked on the semiconductor substrate 14. Here, the buried insulating layer 15 is a silicon oxide film having a thickness of about 0.5 μm, and the SOI layer 16 is a single crystal silicon film having a thickness of about 0.1 μm. These constitute the semiconductor wafer 1. Then, a passivation film 2 is formed on the surface of the semiconductor wafer 1 to form wiring 3, and bumps 4 are formed on the wiring 3. Here, the height of the bump 4 is about 40 μm.

Next, the surface sealing resin 5b is formed on the entire surface by a known method. Here, the film thickness of the surface sealing resin 5b is increased to about 100 μm.

Next, as described above, as shown in FIG. 9B, the semiconductor substrate 14 is removed by wet etching. In this case, since the buried insulating layer 15 functions as an etching stopper, there is no variation in the etching amount caused by the conventional technique.

Next, as shown in FIG. 9C, a back surface sealing resin 9b is formed on the back surface side of the buried insulating layer 15 by a known method. Here, the back surface sealing resin 9b is made of the same material as the surface sealing resin 5b described above, and the thickness thereof is preferably about 100 μm.

After doing so, the surface sealing resin 5b is ground. Then, as shown in FIG. 9D, the surface of the bump 4 is shaved until it is exposed to form a surface sealing resin 5a having a thickness of 40 μm. Similarly, the back surface sealing resin 9b is ground. And it is set as the back surface sealing resin 9 whose film thickness is 40 micrometers. In this way, a structure in which the ultrathin SOI layer 16 having the bumps 4 and the buried insulating layer 15 are sealed with the front surface sealing resin 5a and the back surface sealing resin 9 is completed. Separation of the structure shown in FIG. 9E into the semiconductor chip is the same as described with reference to FIG.

In the fourth embodiment, the case where the front surface sealing resin 5b or the rear surface sealing resin 9b is ground is described. However, the present invention does not grind the first (2) resin layer. It may be formed.

In this embodiment, since the reinforcing plate described in the first to third embodiments is not used, the manufacturing process of the semiconductor device is simplified. As described above, in the case of a substrate having an SOI structure, since the buried insulating layer 15 functions as an etching stopper for wet etching, even if the semiconductor wafer is slightly warped in the process of thinning the semiconductor wafer, There is no variation in the thickness of the semiconductor wafer.

However, even in this case, when the semiconductor substrate 14 is thinned by grinding as described in the first to third embodiments, it is necessary to use a reinforcing plate. Here, if the reinforcing plate is used in the same manner as described in the first to third embodiments, the warp of the semiconductor wafer is eliminated and the stability of mass production is further improved.

In the first to fourth embodiments, the surface sealing resins 5 and 5a that are the first resin layers are formed after the bumps 4 that are the electrodes are formed. However, the present invention is not limited to this. It is not something. Conversely, the electrode may be formed after forming the first resin layer. The electrode in such a case is not limited to the bump electrode described above, and may be another electrode. That is, the electrode may be a conductor that is connected to a substrate or the like outside the semiconductor chip.

According to the present invention, high-density mounting of semiconductor chips described in the prior art becomes very easy. In particular, in the CSP formed according to the present invention, the semiconductor chip can be easily and very thin. For example, the solder ball generated in the prior art due to the difference in thermal expansion coefficient from the mother board on which the CSP is mounted. It is possible to greatly reduce cracks in the connecting portion and greatly improve mounting reliability.

The present invention is not limited to the above-described embodiment, and the embodiment can be appropriately changed within the scope of the technical idea of the present invention.

As described above, in the present invention, an electrode is formed at a predetermined position on an element formation surface of a semiconductor wafer, covers the element formation surface, exposes at least a part of the electrode surface, and the first resin layer is formed. A reinforcing plate is affixed to the first resin layer or the exposed electrode surface formed through an adhesive, and the back surface of the semiconductor wafer is thinned by grinding or etching. And after thinning, the back surface of a semiconductor wafer is coat | covered with the 2nd resin layer.

The present invention facilitates thinning of a semiconductor wafer. In the process, the warp of the semiconductor wafer is completely eliminated, and the variation in the thickness of the semiconductor wafer after thinning is greatly reduced. Further, there is no damage to the wafer caused by the handling of the semiconductor wafer in the thinning process. Furthermore, the reliability of the semiconductor device after mounting is improved.

And the manufacturing process of a semiconductor device becomes simple, and the mass production application of the high-density mounting of a semiconductor device becomes easy.

It is sectional drawing of the order of the manufacturing process of thinning of the semiconductor wafer for demonstrating the 1st Embodiment of this invention. It is sectional drawing of the order of the said following manufacturing process. It is sectional drawing of the order of the manufacturing process of thinning of the semiconductor wafer for demonstrating the 2nd Embodiment of this invention. It is sectional drawing of the order of the said following manufacturing process. It is sectional drawing of the order of the manufacturing process of thinning of the semiconductor wafer for demonstrating the 3rd Embodiment of this invention. It is sectional drawing of the order of the said following manufacturing process. It is sectional drawing which shows the isolation | separation method to the semiconductor chip in this invention. It is sectional drawing which shows another isolation | separation method to the semiconductor chip in this invention. It is sectional drawing of the order of the manufacturing process of thinning of the semiconductor wafer for demonstrating the 4th Embodiment of this invention. It is a schematic sectional drawing of the order of the manufacturing process of thin film formation of the semiconductor wafer for demonstrating the prior art.

Explanation of symbols

1, 1a, 101, 101a Semiconductor wafer 2 Passivation film 3 Wiring 4 Bumps 5, 5a, 5b Surface sealing resin 6 Reinforcement plate 7 Adhesives 8, 104 Grinding stones 9, 9b Back surface sealing resin 10 Groove 11, 105 Semiconductor chip 12 Resin encapsulated chip 13 Resin encapsulated wafer 14 Semiconductor substrate 15 Embedded insulating layer 16 SOI layer 102 Protective tape 103 Suction stage 106 for grinding Enlarged sheet

Claims (5)

  A semiconductor chip formed by laminating an insulating layer and a semiconductor layer, the semiconductor layer of the semiconductor chip having an element formation surface, and a passivation film is formed on the element formation surface; An electrode is formed at a predetermined position, a first resin layer covering the element forming surface and exposing at least a part of the electrode surface is formed, and the insulating layer of the semiconductor chip is covered with a second resin layer A semiconductor device which is characterized by being made.   2. The semiconductor device according to claim 1, wherein the electrode includes an external extraction wiring formed on the element formation surface and a bump formed immediately above the external extraction wiring.   The semiconductor device according to claim 1, wherein the semiconductor layer is Si or SiGe.   4. The semiconductor device according to claim 1, wherein the first resin layer and the second resin layer are made of the same material.   The semiconductor device according to claim 1, wherein the first resin layer and the second resin layer have the same thickness.

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