CN115169279A - Bus wiring method based on GoldenBit and Hanan grid updating - Google Patents
Bus wiring method based on GoldenBit and Hanan grid updating Download PDFInfo
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Abstract
The invention discloses a bus wiring method based on golden bit and Hanan grid updating. Then, before each routing, dynamic Hanan mesh update is performed. For each edge of the Hanan mesh, it is classified into different priorities depending on whether it is generated for segments and lines that the components extend from. And finally, adjusting the routing path according to different priorities, finding the shortest path and ensuring that the topological path is the same as the previous path as much as possible, thereby finishing bus wiring.
Description
Technical Field
The invention relates to the technical field of Very Large Scale Integration (VLSI) physical design automation, in particular to a bus wiring method based on golden bit and Hanan grid updating.
Background
As semiconductor technology enters the nanometer era and the scale of electronic systems increases, the difficulty of PCB bus wiring is increasing, because the same optimal topological path wiring is realized for bits on the bus while avoiding the obstacle route, and fig. 1 illustrates a bus with the same topological structure. Meanwhile, bus routing is one of the most time-consuming and difficult steps in PCB design, and congestion of components on a board, limitation of length range, and the like must be considered in the routing process.
Due to new challenges in bus routing, current bus automation routing technology may not be sufficient to meet the requirements of today's PCB design, and currently relies heavily on manual routing. The Hanan mesh is a patterning means that can better describe the adjacency of wiring regions in VLSI automated design. However, in the prior art, the Hanan mesh is generated once according to the position of the component, and then the routing selection is carried out, and the characteristics of PCB routing, such as the routing sequence, the topological structure of a bus and the like, are not considered. The wiring result can not meet the requirement of the industry, and the wiring rate is lower and needs to be improved. Therefore, further improvement on the Hanan mesh is expected, and a bus wiring method capable of optimizing the wiring sequence and the topology structure is developed, so that the requirement of automatic wiring in the current industry can be met.
Disclosure of Invention
Aiming at the defects and shortcomings in the prior art, the invention provides a bus wiring method based on golden bit and Hanan mesh updating, which improves the Hanan mesh and introduces the Hanan mesh updating method, so that the wiring path can be used for finding the shortest path to a target pin while meeting the condition of having the same topological path as far as possible through the priority information of the Hanan mesh edge.
Firstly, generating a golden bit topological path of each component, and then routing other pin pins. Then, before each routing, a dynamic Hanan mesh update is performed. For each edge of the Hanan mesh, the segments and the lines from which the components extend are classified into different priorities based on whether they are generated. And finally, adjusting the routing path according to different priorities, finding the shortest path and ensuring that the topological path is the same as the previous path as much as possible, thereby finishing bus wiring.
The technical scheme is as follows: (1) Determining a golden bit according to the intersection points of connecting lines generated by the middle points of the PCB and the assembly; (2) Dynamic Hanan grid updating, storing the section of the route finished by wiring, adding the section into a new Hanan grid diagram, and setting each edge of the generated Hanan grid into different priorities according to different edge compositions; (3) And selecting the path to be taken according to the priority by adopting an A-star algorithm, so that the optimal wiring path is found while the topology of the current path is as same as the previous path as possible.
Experimental results show that the algorithm can optimize the wiring sequence and the topological structure, and greatly improve the wiring rate.
In order to achieve the purpose, the invention adopts the following technical scheme:
a bus wiring method based on GoldenBit and Hanan grid updating is characterized by comprising the following steps:
s1, constructing an initial Hanan grid, and generating a golden bit path of each component according to the middle point of a PCB and the middle points of the components;
s2, adjusting the golden bit path generated in the S1;
and step S3: adding the bit path with successful wiring into the next Hanan grid generation, and setting the priority of the edges of the Hanan grid unit;
and step S4: firstly, searching the grid where the segment of the previous path is located by using breadth first, and then selecting the path according to the priority of the grid edge by using an A-x algorithm;
step S5: the wiring path generated in step S4 is adjusted.
Further, step S1 specifically includes the following steps:
step S11: constructing an initial Hanan grid by the boundaries of the components and the PCB, and finding out the midpoint coordinates of the PCB and the current component;
step S12: under the guidance of step S11, connecting the two midpoints to obtain a line segment;
step S13: performing a straddle experiment and a fast repulsion experiment on each edge of the current assembly and the line segment to determine which edge is intersected with the line segment, skipping the assembly if the edges of the assemblies are not intersected with the line segment, and selecting the next assembly according to the priority of the assembly to return to the step S11;
step S14: under the guidance of the step S13, if the edge intersects with the line segment, solving the coordinate of the intersection point by using a vector method, and then finding out the pin closest to the intersection point;
step S15: under the guidance of step S14, a shortest path is found for this pin using the a-x algorithm; specifically, the midpoint of each Hanan mesh unit is set as a walkable node in the A-algorithm process, so that a shortest path is found to serve as the golden bit of the current component.
Further, step S2 specifically includes the following steps:
s21, adjusting the first section and the last section of the alignment path; firstly, adding two sections, namely a section from a starting pin to the middle point of a grid where the starting pin is located and a section from an ending pin to the middle point of the grid where the ending pin is located; then, according to the edge of the component where the pin is located, judging whether the directions of the first section and the last section are horizontal or vertical, and adjusting the coordinates of the first section and the last section;
step S22: counting the number of pins passing through the boundary process from the initial pin of the golden bit to the edge of the assembly according to the segment 2 direction of the golden bit;
step S23: under the direction of step S22, the reserved distance W is calculated as the length of segment 1:
W(N p )＝N p ·CW+U (1)
in the formula, N p Representing the number of pins counted; CW represents the sum of the pitch and the line width specified by the layer; u represents a user added spacing requirement;
step S24: judging whether the golden bit consists of three or more sections; if so, judging whether a rectangle can be formed or not; if the rectangle can be formed, counting the number of pins on the boundary of the component in the rectangle;
step S25: under the guidance of step S24, calculating a reserved distance as a reserved distance from the third section to the current component;
step S26: and adjusting the golden bit wiring path according to the node information of the path and the guidance of the step S23 and the step S25.
Further, step S3 specifically includes the following steps:
step S31: recording a segment of a bit which is successfully wired currently as a set S = (V, H), wherein V represents a segment in a vertical direction, and H represents a segment in a horizontal direction;
step S32: extending the segments in the set S as edges until other components are encountered or the segments in the set S are encountered;
step S33: according to different grid edge compositions, the grid edge compositions are divided into 5 cases, and the priorities of the cases are set from high to low, namely: a segment, an edge from which the segment extends, a boundary of the component, an edge from which the boundary of the component extends, and an edge of the PCB board.
Further, step S4 specifically includes the following steps:
step S41: for the current pin, firstly using breadth-first search to find out that a certain edge of a Hanan grid is formed by a segment of a previous path and then stopping;
step S42: the next grid to be walked is selected according to the composition of the grid using the a-algorithm.
Further, step S5 specifically includes the following:
traversing four edges of the current grid, moving the line segments in the current grid to the corresponding edges according to the priority of the grid edges and keeping the specified interval according to the guidance of the step S33, if the highest priority of the current grid edges is the boundary of the component, further judging whether pins on the boundary of the component need to be wired, and if so, skipping and recursing to the next priority.
The invention and the preferred scheme thereof provide a golden bit generation scheme and a Hanan mesh updating scheme, the shortest path can be found under the condition of keeping the same topological path to the maximum extent, and the adopted test example shows that the algorithm provided by the invention can quickly obtain a better result.
Drawings
FIG. 1 is a drawing in the background of the invention, showing a bus with the same topology, consisting of 3 bits.
FIG. 2 is a flow chart of a method according to an embodiment of the present invention.
Fig. 3 shows two cases when golden bit is constructed according to the embodiment of the present invention, wherein (a) is the case when the middle point of the PCB board and the middle point of the assembly are both in the current assembly, and (b) is the case when the line segment connecting the middle points successfully intersects with the boundary of the assembly.
Fig. 4 is an exemplary diagram of reserved space according to an embodiment of the present invention.
Fig. 5 is an exemplary diagram of segments used in constructing a new Hanan mesh in accordance with an embodiment of the present invention, wherein solid lines indicate segments to be added to the next Hanan mesh construction and dashed lines indicate previously deleted segments.
Fig. 6 is a diagram illustrating an example of a Hanan mesh configuration according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating an exemplary layout path without trimming according to an embodiment of the present invention.
Detailed Description
In order to make the features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail as follows:
it should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
As shown in fig. 2, the present embodiment provides a bus wiring method based on golden bit and Hanan mesh update, which includes the following steps:
s1, constructing an initial Hanan grid, and generating a golden bit path of each component according to the midpoint of a PCB and the midpoints of the components;
s2, adjusting the golden bit path generated in the S1;
and step S3: adding the bit path with successful wiring into the next Hanan grid generation, and setting the priority of the edges of the Hanan grid unit;
and step S4: firstly, searching the grid where the segment of the previous path is located by using breadth first, and then selecting the path according to the priority of the grid edge by using an A-x algorithm;
step S5: the wiring path generated in step S4 is adjusted.
In the present embodiment, step S1, namely the "construct initial Hanan diagram" and "construct of golden bit" sections in fig. 2, specifically includes the following steps:
step S11: and constructing an initial Hanan grid by the boundaries of the components and the PCB, and finding the midpoint coordinates of the PCB and the current components.
In this embodiment, the PCB and the component are rectangular in shape, and the midpoint coordinate is obtained according to the lower left corner coordinate and the upper right corner coordinate information of the PCB and the component.
Step S12: under the direction of step S11, two midpoints are connected to obtain a line segment.
Step S13: the step experiment and the fast repulsion experiment are performed on each edge of the current assembly and the line segment to determine which edge intersects the line segment, and if none of the edges of the assembly intersects the line segment, as shown in fig. 3 (a), the midpoint of the PCB board and the midpoint of the assembly 1 are in the assembly, and the midpoint cannot be generated with the assembly boundary. When this occurs, the one component is skipped and the next component is selected based on its priority to continue the above steps. In this embodiment, the priority of a component is determined by how many pins are on the component or by a user-specified priority, with more pins being the higher the priority.
Step S14: under the guidance of step S13, if the edge intersects with the line segment, as shown in fig. 3 (b), there is an intersection between the line segment formed by the midpoint of the PCB and the midpoint of the component and the boundary of the component, the coordinates of the intersection are solved by using a vector method, and then the nearest pin to the intersection is found.
Step S15: under the guidance of step S14, a shortest path is found for this pin by using the a-algorithm, and the midpoint of each Hanan mesh cell is set as a node that can be moved in the a-algorithm process, so as to find a shortest path as the golden bit of the current component.
In this embodiment, the step S2, i.e. the "golden bit adjustment" part in fig. 2, specifically includes the following steps:
and S21, adjusting the first stage, namely adjusting the first stage and the last stage of the alignment path. First add two segments, the segment starting the pin to the midpoint of its grid and the segment ending the pin to the midpoint of its grid. Then, according to the edge of the component where the pin is located, whether the direction of the first section and the last section is horizontal or vertical is judged, so that the coordinates of the first section and the last section are adjusted. For example, if the pin is at the left or right boundary of the component, then its first segment direction must be horizontal, and vice versa, it is vertical.
Step S22: the second stage of adjustment, according to the segment 2 direction of golden bit, counts the number of pins passing from the start pin of golden bit to the edge boundary of the device, as shown in fig. 4, the segment 2 direction is from right to left, then the number of pins passing from the current pin to the left boundary of the device is counted.
Step S23: under the direction of step S22, the reserved distance W is calculated as the length of segment 1, as shown by reserved distance a in fig. 4; the reserved distance W is calculated as follows:
W(N p )＝N p ·CW+U (1)
in the formula, N p Representing the number of pins counted; CW represents the sum of the pitch and the line width specified by the layer; u represents the spacing requirement added by the user.
Step S24: it is determined whether the golden bit is comprised of three or more segments. If so, judging whether the rectangle can be formed or not. As shown in fig. 4, the first three segments may form a rectangle, and the rectangle surrounds several segment boundaries of the component, so the number of pins on the component boundary in the rectangle is counted.
Step S25: under the direction of step S24, the reserved distance is calculated as the reserved distance from the third segment to the current component, as shown by the reserved distance b in fig. 4.
Step S26: the golden bit wiring path is adjusted based on the node information of the path and the guidance of step S23 and step S25.
In this embodiment, the step S3, i.e. the part of "construct new Hanan diagram" in fig. 2, specifically includes the following steps:
step S31: the segment of the currently successfully routed bit is denoted as set S = (V, H), where V denotes a segment in the vertical direction and H denotes a segment in the horizontal direction.
In this embodiment, if the topology path of the current successfully wired bit is the same as the topology path of the previous bit, and the component where the start pin is located and the component where the end pin is located are the same, the segment in the set S related to the previous bit path is deleted, as shown in fig. 5, the dotted path represents the segment deleted from the set S in this process, the solid line represents the segment in the set S, and it needs to be added to the next process of constructing a new Hanan graph.
Step S32: similar to a component, the segments in set S are also extended as edges until other components are encountered or the segments in set S are encountered.
Step S33: as shown in fig. 6, the mesh edges are classified into 5 cases according to their composition, and their priorities are set from high to low: a segment, an edge from which the segment extends, a boundary of the component, an edge from which the boundary of the component extends, and an edge of the PCB board.
In this embodiment, the step S4, that is, the "use extent priority algorithm and a × algorithm" part in fig. 2, specifically includes the following parts:
step S41: and for the current pin, firstly using breadth-first search to find out that a certain edge of a Hanan grid is formed by the segment of the previous path and then stopping.
Step S42: the next grid to be walked is selected according to the composition of the grid using the a-algorithm. The definition of a algorithm is as follows:
f(H)＝P(H)+β(g(H)+h(H)) (2)
wherein f (H) represents an evaluation function from the initial grid to the end grid via grid H, and g (H) represents a cost from the initial grid to grid H; h (H) represents the estimated cost from grid H to the end point grid; p (H) is the priority of mesh H, defined in this step as follows:
wherein the content of the first and second substances,
is the number of edges of trellis H formed by segments of the last bit path;
the number of the edges of the grid H is formed by the edges extending from the section of the previous bit path; alpha is alpha s And alpha ds Then represents the corresponding weight, alpha s Is much greater than alpha ds And, when
Or
When not zero, the value of beta is 0; when in use
And
when both values are 0, P (H) is 0 and β is 1.
As shown in fig. 7, for the current pin, first, using breadth-first search to find out a certain edge of a Hanan mesh, which is formed by a segment of a previous bit path, and then using an a-algorithm with the mesh as a starting point, if the certain edge of the Hanan mesh encountered in the process is formed by the segment of the previous bit path or an edge extended from the segment of the previous bit path, the value of β is equal to 0. For the inflection point, since the inflection point has more edges extending from the segment of the previous bit path than other grids, the inflection point can be obtained by the calculation formula of P (H), and the value of f (H) is smaller, so that the inflection point can be guaranteed to be the node to be taken next. After it reaches trellis z, none of the walkable trellis will have an edge formed by a segment or extension of a segment of the previous bit path, with β having a value of 1 and p (H) having a value of 0. The a-algorithm continues to be used so that the shortest path is found while ensuring that the topologies are as similar as possible.
In this embodiment, step S5, i.e. the "routing path adjustment" part in fig. 2, specifically includes the following steps:
step S51: the first stage adjustment is completed as directed by step S21.
Step S52: and a second stage of adjustment, namely traversing four edges of the current grid, moving the line segments in the current grid to the corresponding sides according to the priority of the grid edges and keeping a specified distance, if the highest priority of the current grid edges is the boundary of the component, judging whether pins on the boundary of the component need to be wired, and if so, skipping and recursing to the next priority.
The foregoing is directed to preferred embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. However, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present invention will still fall within the protection scope of the technical solution of the present invention.
The present invention is not limited to the above preferred embodiments, and other various bus routing methods based on golden bit and Hanan mesh update can be derived by anyone based on the teaching of the present invention.
Claims (6)
1. A bus wiring method based on GoldenBit and Hanan grid updating is characterized by comprising the following steps:
s1, constructing an initial Hanan grid, and generating a golden bit path of each component according to the middle point of a PCB and the middle points of the components;
s2, adjusting the golden bit path generated in the S1;
and step S3: adding the successfully wired bit path into next Hanan mesh generation, and setting priority on the edges of Hanan mesh units;
and step S4: firstly, searching the grid where the segment of the previous path is located by using breadth first, and then selecting the path according to the priority of the grid edge by using an A-x algorithm;
step S5: the wiring path generated in step S4 is adjusted.
2. The golden bit and Hanan mesh update based bus routing method of claim 1, wherein: the step S1 specifically includes the following steps:
step S11: constructing an initial Hanan grid by the boundaries of the components and the PCB, and finding out the midpoint coordinates of the PCB and the current components;
step S12: under the guidance of step S11, connecting the two midpoints to obtain a line segment;
step S13: performing a straddle experiment and a fast repulsion experiment on each edge of the current assembly and the line segment to determine which edge intersects the line segment, skipping the assembly if the edges of the assembly do not intersect the line segment, and selecting the next assembly according to the priority of the assembly to return to the step S11;
step S14: under the guidance of step S13, if the edge intersects with the line segment, the vector method is used for solving the coordinates of the intersection point, and then the pin closest to the intersection point is found out;
step S15: under the guidance of step S14, a shortest path is found for this pin using the a-x algorithm; specifically, the midpoint of each Hanan mesh unit is set as a walkable node in the A-algorithm process, so that a shortest path is found to serve as the golden bit of the current component.
3. The golden bit and Hanan mesh update based bus routing method of claim 1, wherein: the step S2 specifically includes the following steps:
s21, adjusting the first section and the last section of the alignment path; firstly, adding two sections, namely a section from a starting pin to the middle point of a grid where the starting pin is located and a section from an ending pin to the middle point of the grid where the ending pin is located; then, according to the edge of the component where the pin is located, judging whether the directions of the first section and the last section are horizontal or vertical, and adjusting the coordinates of the first section and the last section;
step S22: counting the number of pins passing through from the initial pin of the golden bit to the boundary of the edge of the assembly according to the direction of the segment 2 of the golden bit;
step S23: under the direction of step S22, the reserved distance W is calculated as the length of segment 1:
W(N p )＝N p ·CW+U (1)
in the formula, N p Representing the number of pins counted; CW denotes the sum of the pitch and the line width specified by the layer; u represents a user added spacing requirement;
step S24: judging whether the golden bit consists of three or more sections; if so, judging whether a rectangle can be formed or not; if the rectangle can be formed, counting the number of pins on the boundary of the component in the rectangle;
step S25: under the guidance of step S24, calculating a reserved distance as a reserved distance from the third section to the current component;
step S26: and adjusting the golden bit wiring path according to the node information of the path and the guidance of the step S23 and the step S25.
4. The golden bit and Hanan mesh update based bus routing method of claim 1, wherein: the step S3 specifically includes the following steps:
step S31: recording a segment of a bit with successful current wiring as a set S = (V, H), wherein V represents a segment in a vertical direction, and H represents a segment in a horizontal direction;
step S32: extending the segments in the set S as edges until other components are encountered or the segments in the set S are encountered;
step S33: according to different compositions of grid edges, the grid edges are divided into 5 cases, and the priorities of the cases are set from high to low and respectively comprise: a segment, an edge from which the segment extends, a boundary of the component, an edge from which the boundary of the component extends, and an edge of the PCB board.
5. The method for bus routing based on golden bit and Hanan mesh update of claim 1, wherein: the step S4 specifically includes the following steps:
step S41: for the current pin, firstly using breadth-first search to find out that a certain edge of a Hanan grid is formed by a segment of the previous path and then stopping;
step S42: the next grid to be walked is selected according to the composition of the grid using the a-algorithm.
6. The method for bus routing based on golden bit and Hanan mesh update of claim 4, wherein: step S5 specifically includes the following:
traversing four edges of the current grid, moving the line segments in the current grid to the corresponding edges according to the priority of the grid edges and keeping the specified interval according to the guidance of the step S33, if the highest priority of the current grid edges is the boundary of the component, further judging whether pins on the boundary of the component need to be wired, and if so, skipping and recursing to the next priority.
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| CN116341478A (en) * | 2023-02-16 | 2023-06-27 | 北京百度网讯科技有限公司 | Quantum chip wiring method, device, equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116341478A (en) * | 2023-02-16 | 2023-06-27 | 北京百度网讯科技有限公司 | Quantum chip wiring method, device, equipment and storage medium |
| CN116341478B (en) * | 2023-02-16 | 2023-12-05 | 北京百度网讯科技有限公司 | Quantum chip wiring method, device, equipment and storage medium |
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