CN115168266A - Extensible NVMe solid-state disk-based satellite-borne high-speed universal memory - Google Patents
Extensible NVMe solid-state disk-based satellite-borne high-speed universal memory Download PDFInfo
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- CN115168266A CN115168266A CN202210718032.XA CN202210718032A CN115168266A CN 115168266 A CN115168266 A CN 115168266A CN 202210718032 A CN202210718032 A CN 202210718032A CN 115168266 A CN115168266 A CN 115168266A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The invention relates to an extensible NVMe solid-state disk-based satellite-borne high-speed universal memory, which comprises a controller, a high-speed bus driver, a high-speed bus multiplexer and an NVMe solid-state disk; the controller has 1 and 2 n+1 2 bits GPIO interface and 2 PCIeGEN3x4 interface, 2 PCIeGEN3x4 interface can mount 2 at most after n-level extension through high speed bus driver and high speed bus multiplexer n+1 Block NVMe solid State disk, through 2 n+1 And the 2-bit GPIO interface can control the data channel selection bits of each high-speed bus multiplexer and high-speed bus driver to select the corresponding NVMe solid-state disk to perform data read-write operation. The invention improves the storage capacity, reliability and service life of the memory, has low additional power consumption, supports multi-stage expansion, and can adapt to various kinds of storage media by adjusting the balance parametersDifferent use requirements.
Description
Technical Field
The invention belongs to the technical field of satellite-borne high-speed universal memories, and particularly relates to an extensible NVMe solid-state disk-based satellite-borne high-speed universal memory.
Background
The NVMe solid-state disk is a nonvolatile memory accessed through a PCIe interface, is a new generation of high-speed solid-state storage medium, and has a read-write speed far exceeding that of storage media such as SATA solid-state disks. Controllers such as FPGAs and socs are often used for onboard high-speed general-purpose memory controllers because of their extremely high data throughput capability. In summary, a memory using an FPGA or an SoC as a controller and an NVMe solid-state disk as a storage medium is one of the ideal choices for a high-performance commercial satellite high-speed universal memory.
However, controllers such as FPGAs or socs have only a limited number of PCIe GEN3x4 interfaces, and most controllers even have only 1 to 2 PCIe GEN3x4 interfaces. Therefore, the main problems of the on-board high-speed universal memory of the present architecture are: 1. the storage capacity of the space-borne high-speed universal memory of the architecture cannot be further improved due to the limitation of two factors, namely the PCIe GEN3x4 interface number of the controller and the current NVMe solid-state disk capacity; 2. because the space environment is very harsh, factors such as temperature, vibration, radiation and the like may affect electronic products, the space-borne high-speed universal memory has higher reliability requirements, and a storage architecture based on most controllers generally only supports mounting two NVMe solid-state disks, so that the system reliability is affected to a certain degree.
Disclosure of Invention
In order to solve the problems of the satellite-borne high-speed general memory in the prior art, the invention provides an extensible NVMe solid-state disk-based satellite-borne high-speed general memory.
An extensible NVMe solid-state disk-based satellite-borne high-speed universal memory comprises a controller, a high-speed bus driver, a high-speed bus multiplexer and an NVMe solid-state disk, wherein the controller is an FPGA or an SoC, the high-speed bus driver is provided with models of DS160PR412 and DS160PR421, and the high-speed bus multiplexer is provided with a model of TMUXHS4412;
the controller has 1 and 2 n+1 -2 bits GPIO interface and 2 PCIe GEN3x4 interfaces, 2 PCIe GEN3x4 interfaces can mount 2 at most after n-level expansion through the high speed bus driver and the high speed bus multiplexer n+1 Block NVMe solid-state disk, and by said 2 n+1 The 2-bit GPIO interface can control the data channel selection bits of each high-speed bus multiplexer and the high-speed bus driver, and one NVMe solid-state disk is selected for each of the 2 PCIe GEN3x4 interfaces to perform data read-write operation.
The invention realizes the extended function of the NVMe solid-state disk-based satellite-borne high-speed universal memory, solves two main defects of the prior architecture satellite-borne high-speed universal memory, and has the following beneficial effects: 1. by expanding the NVMe solid-state disk, the storage capacity of the satellite-borne high-speed general memory based on the storage architecture is greatly improved, so that the storage capacity is improved by at least more than 4 times; 2. by expanding the NVMe solid-state disk, more NVMe solid-state disks can be used for backup, so that the reliability and the service life of the satellite-borne high-speed universal memory of the architecture are greatly improved; 3. the expandable satellite-borne high-speed universal memory realized by combining the TMUXHS4412 high-speed bus multiplexer and the DS160PR412/DS160PR421 high-speed bus driver has the advantages of lower additional power consumption, support of multi-level expansion and the like, and can adapt to various different use requirements by adjusting the balance parameters; 4. the expansion method has extremely strong applicability, and is widely applicable to various satellite-borne high-speed universal memories based on the FPGA and the SoC controller.
Drawings
FIG. 1 is an architecture diagram of an extensible NVMe solid-state disk-based on-board high-speed universal memory according to the present invention;
FIG. 2 is a flowchart illustrating the operation of the expandable NVMe solid-state disk-based on-board high-speed universal memory according to the present invention.
Detailed Description
The technical solution of the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.
The invention provides an extensible spaceborne high-speed universal memory based on an NVMe solid-state disk, which mainly comprises a controller, a high-speed bus driver, a high-speed bus multiplexer and the NVMe solid-state disk, wherein the controller is an FPGA (field programmable gate array) or SoC (system on chip) controller, the types of the high-speed bus driver are DS160PR412 and DS160PR421, and the type of the high-speed bus multiplexer is TMUXHS4412. The DS160PR412/DS160PR421 high speed bus driver is a four channel Linear driver with a Linear equalizer (CTLE) inside to compensate the high frequency components of the signal. The TMUXHS4412 high-speed bus multiplexer of TI company is an analog differential passive four-channel multiplexer or demultiplexer, supports the data rate of up to 20Gbps, and is suitable for a plurality of high-speed differential interfaces including a PCIe3.0 interface.
The system architecture diagram of the satellite-borne high-speed general memory is shown in FIG. 1. It adopts a controller with 1 and 2 n+1 2 bits GPIO interface and 2 PCIe GEN3x4 interface, 2 PCIe GEN3x4 interface can mount 2 at most after n-stage expansion through TMUXHS4412 high-speed bus multiplexer and DS160PR412/DS160PR421 high-speed bus driver n+1 Block NVMe solid State disk (NVMe SSD), and may be by 2 of the controller n+1 The-2-bit GPIO interface controls the data channel selection bits of each TMUXHS4412 high-speed bus multiplexer and the DS160PR412/DS160PR421 high-speed bus driver, so that one NVMe solid-state disk is selected for each of the 2 PCIe GEN3x4 interfaces of the controller to perform data read-write operation.
The TMUXHS4412 high-speed bus multiplexer used by the invention is used as a passive switch multiplexer and has the power consumption as low as 0.1mW, so that the system has scalable storage function in exchange for extremely low additional power consumption.
High frequency signals are greatly attenuated in the process of transmitting PCIe signals, and further, the integrity of the signals is greatly influenced. The DS160PR412/DS160PR421 high-speed bus driver used in the invention has 16-gear adjustable high-frequency signal balancing capacity, parameters can be adjusted according to factors such as the expansion stage number of a storage expansion system, the length of a PCIe signal link and the like, the compensation amount of signals under the frequency of 4GHz can reach 13dB at most, and high-frequency attenuation in the signal transmission process can be effectively compensated.
The invention combines the TMUXHS4412 high-speed bus multiplexer and the DS160PR412/DS160PR421 high-speed bus driver to realize a storage expansion system which has lower additional power consumption, can be expanded in multiple stages and has high adaptability.
Further, the extensible NVMe solid-state disk-based satellite-borne high-speed general memory work flow diagram of the invention is shown in fig. 2, and the specific process comprises the following steps:
(1) Determining the number of NVMe solid-state disks needing to be mounted according to the actual application condition, and further determining the expansion stage number n of the satellite-borne high-speed universal memory;
(2) Configuring signal equalization parameters of the DS160PR412/DS160PR421 high-speed bus driver according to factors such as the expansion stage number n of the satellite-borne high-speed general memory, the length of a PCIe signal link and the like;
(3) Powering on the memory and completing initialization;
(4) According to the solid-state disk switching instruction sent by the upper computer, the data is switched through the controller 2 n+1 The 2-bit GPIO interface configures data channel selection bits of each TMUXHS4412 high-speed bus multiplexer and the DS160PR412/DS160PR421 high-speed bus driver, so that each PCIe GEN3x4 interface of the controller is respectively associated with 1 NVMe solid-state disk;
(5) The controller resets PCIe GEN3x4 and establishes a link with the currently connected NVMe solid-state disk;
(6) Normal read-write operation is carried out according to a read-write instruction sent by an upper computer;
(7) After the read-write operation is finished, judging whether a new read-write task is executed, if so, executing a step (8), otherwise, executing a step (9);
(8) Judging whether the currently connected NVMe solid-state disk is still subjected to read-write operation, if so, returning to the step (6); otherwise, returning to the step (4), reconfiguring the data channel selection bit and selecting other NVMe solid-state disks for read-write operation in a state that read-write operation is not performed (in a system idle state);
(9) And the task is completed, and the memory is shut down.
The invention realizes the extended function of the NVMe solid-state disk-based satellite-borne high-speed general memory, solves two main defects of the structure satellite-borne high-speed general memory and has the following beneficial effects: 1. by expanding the NVMe solid-state disk, the storage capacity of the satellite-borne high-speed general memory based on the storage architecture is greatly improved, so that the storage capacity is improved by at least more than 4 times; 2. by expanding the NVMe solid-state disk, more NVMe solid-state disks can be used for backup, so that the reliability and the service life of the satellite-borne high-speed universal memory of the architecture are greatly improved; 3. the expandable satellite-borne high-speed universal memory realized by combining the TMUXHS4412 high-speed bus multiplexer and the DS160PR412/DS160PR421 high-speed bus driver has the advantages of lower additional power consumption, support of multi-level expansion and the like, and can adapt to various different use requirements by adjusting the balance parameters; 4. the expansion method has extremely strong applicability, and is widely applicable to various satellite-borne high-speed universal memories based on the FPGA and the SoC controller.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (2)
1. The expandable NVMe solid-state disk-based satellite-borne high-speed universal memory is characterized by comprising a controller, a high-speed bus driver, a high-speed bus multiplexer and an NVMe solid-state disk, wherein the controller is an FPGA or an SoC, the high-speed bus drivers are DS160PR412 and DS160PR421, and the high-speed bus multiplexer is TMUXHS4412;
the controller has 1 and 2 n+1 2 bits GPIO interface and 2 PCIe GEN3x4 interfaces, 2 PCIe GEN3x4 interfaces can mount 2 at most after n-level expansion is carried out by the high-speed bus driver and the high-speed bus multiplexer n+1 Block NVMe solid-state disk, and through said 2 n+1 The 2-bit GPIO interface can control the data channel selection bits of each high-speed bus multiplexer and the high-speed bus driver, and one NVMe solid-state disk is selected for each of 2 PCIe GEN3x4 interfaces to perform data reading and writing operations.
2. The scalable NVMe solid-state disk-based on-board universal express memory according to claim 1, wherein the working process of the on-board universal express memory comprises the following steps:
(1) Determining the number of NVMe solid-state disks needing to be mounted, and further determining the expansion stage number n of the satellite-borne high-speed universal memory;
(2) Configuring signal equalization parameters of the high-speed bus driver according to the expansion stage number n and the length of a PCIe signal link;
(3) Powering on the memory and completing initialization;
(4) According to the solid-state disk switching instruction sent by the upper computer, the controller 2 n+1 -a 2-bit GPIO interface configures the data channel select bits of each of the high-speed bus multiplexers and the high-speed bus drivers such that each of the PCIe GEN3x4 interfaces of the controller is associated with a respective 1 block NVMe solid state disk;
(5) The controller resets the PCIe GEN3x4 interface and establishes a link with the currently connected NVMe solid-state disk;
(6) Normal read-write operation is carried out according to a read-write instruction sent by an upper computer;
(7) After the read-write operation is finished, judging whether to execute new read-write operation, if so, executing a step (8), otherwise, executing a step (9);
(8) Judging whether the currently connected NVMe solid-state disk is still subjected to read-write operation, and if so, returning to the step (6); otherwise, returning to the step (4), reconfiguring the data channel selection bit, and selecting other NVMe solid-state disks for read-write operation;
(9) And completing the task and shutting down the memory.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104331133A (en) * | 2014-11-07 | 2015-02-04 | 浪潮(北京)电子信息产业有限公司 | Hard disk backboard and hard disk storage system |
| CN106776387A (en) * | 2016-11-24 | 2017-05-31 | 大唐高鸿信安（浙江）信息科技有限公司 | Hard disk access expanding unit |
| CN108121672A (en) * | 2017-08-08 | 2018-06-05 | 鸿秦（北京）科技有限公司 | A kind of storage array control method and device based on Nand Flash memorizer multichannel |
| US20180246833A1 (en) * | 2017-02-28 | 2018-08-30 | Cisco Technology, Inc. | DYNAMIC PARTITION OF PCIe DISK ARRAYS BASED ON SOFTWARE CONFIGURATION / POLICY DISTRIBUTION |
| CN109933554A (en) * | 2019-03-20 | 2019-06-25 | 浪潮商用机器有限公司 | A kind of NVMe hard disk expansion apparatus based on GPU server |
| CN110647292A (en) * | 2019-08-16 | 2020-01-03 | 苏州浪潮智能科技有限公司 | Method and system for expanding storage capacity in server system |
| CN110989921A (en) * | 2019-10-24 | 2020-04-10 | 西安艾可萨科技有限公司 | Configurable storage array system, control method thereof and communication equipment |
-
2022
- 2022-06-22 CN CN202210718032.XA patent/CN115168266B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104331133A (en) * | 2014-11-07 | 2015-02-04 | 浪潮(北京)电子信息产业有限公司 | Hard disk backboard and hard disk storage system |
| CN106776387A (en) * | 2016-11-24 | 2017-05-31 | 大唐高鸿信安（浙江）信息科技有限公司 | Hard disk access expanding unit |
| US20180246833A1 (en) * | 2017-02-28 | 2018-08-30 | Cisco Technology, Inc. | DYNAMIC PARTITION OF PCIe DISK ARRAYS BASED ON SOFTWARE CONFIGURATION / POLICY DISTRIBUTION |
| CN110312999A (en) * | 2017-02-28 | 2019-10-08 | 思科技术公司 | Dynamic based on software configuration/strategy distribution PCIe disk array divides |
| CN108121672A (en) * | 2017-08-08 | 2018-06-05 | 鸿秦（北京）科技有限公司 | A kind of storage array control method and device based on Nand Flash memorizer multichannel |
| CN109933554A (en) * | 2019-03-20 | 2019-06-25 | 浪潮商用机器有限公司 | A kind of NVMe hard disk expansion apparatus based on GPU server |
| CN110647292A (en) * | 2019-08-16 | 2020-01-03 | 苏州浪潮智能科技有限公司 | Method and system for expanding storage capacity in server system |
| CN110989921A (en) * | 2019-10-24 | 2020-04-10 | 西安艾可萨科技有限公司 | Configurable storage array system, control method thereof and communication equipment |
Non-Patent Citations (1)
| Title |
|---|
| 郝嘉;候梦清;: "NVMe存储协议浅论" * |
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