CN111309646A - Storage device and data writing, reading, backup and recovery method thereof - Google Patents
Storage device and data writing, reading, backup and recovery method thereof Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1448—Management of the data involved in backup or backup restore
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0871—Allocation or management of cache space
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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Abstract
The present invention relates to a storage device comprising: a host interface; a controller; a data buffer; a clock driver; a first storage area for storing data having an access frequency within a first access frequency range; and a second storage area for storing data having an access frequency within a second access frequency range. The access frequency in the first access frequency range is higher than the access frequency in the second access frequency range. The invention also relates to data writing, reading, backing up and restoring methods.
Description
Technical Field
The present invention relates to the field of memories. More particularly, the present invention relates to a storage device and data writing, reading, backing up and restoring methods thereof.
Background
A non-volatile dual in-line memory module (NVDIMM) is a memory module that integrates a Dynamic Random Access Memory (DRAM) and a non-volatile memory (NVM). Generally, when a host (host)/Central Processing Unit (CPU) is abnormal or powered down, the NVDIMM will backup the data in the DRAM therein to the NVM; then, when the host is powered up again, the data backed up in the NVM is restored to the DRAM. Therefore, the NVDIMM can avoid data loss when the host computer is abnormal or in power failure, and the reliability of the host computer is improved. NVDIMMs are powered by supercapacitors during data backup, but supercapacitors have limited power and suffer from large attenuation with service time and operating temperature. For NVDIMMs, power consumption for data backup and data backup/restore time are two important performance criteria, which determine the capacity of the super capacitor, the reliability of the system and the cost of the product. The increase of data backup power consumption inevitably needs to improve the capacity of the super capacitor, and the increase of the capacity of the super capacitor can bring about the increase of cost and the reduction of reliability; the time of data backup/restore determines the power consumption and user experience during the data backup process. Currently, NVDIMM has different implementation modes, wherein P type NVDIMM (NVDIMM-P) can be visited by the host computer when configuring NVM to normal work, has promoted NVM's utilization ratio greatly, and then can realize the super capacity. However, the data backup and restore mechanism of NVDIMM-P is not explicit.
Fig. 1 shows a signal flow and interface diagram of an NVDIMM-P in the prior art, in which a Data Buffer (DB) connects a Data (DQ) signal to a Controller (Controller), and the Controller drives a Command/Address (CA) signal and a DQ signal to access a memory. However, the structure shown in fig. 1 has the following problems: the data signal can be enhanced in driving capability through the data buffer, but the signal enhanced in driving is difficult to hold and transmit to the memory after entering the controller, and the accessible number and the access rate of the memory module are limited by the driving capability of the controller.
In addition, while the non-volatile memory in NVDIMM-P can be read and written during normal operation, the non-volatile memory in NVDIMM is typically read and written at a slower speed than DRAM.
Disclosure of Invention
Embodiments of the present invention relate to a storage device, a writing method of writing data into the storage device, a reading method of reading data from the storage device, and a data backup method and a data recovery method of the storage device.
According to a first aspect of the present invention, there is provided a storage apparatus, wherein the storage apparatus comprises:
a host interface;
a controller;
a data buffer;
a clock driver;
a first storage area for storing data having an access frequency within a first access frequency range; and
a second storage area for storing data having an access frequency within a second access frequency range;
wherein the access frequency in the first access frequency range is higher than the access frequency in the second access frequency range.
According to a second aspect of the present invention, there is provided a writing method of writing data into a storage apparatus, wherein the storage apparatus includes a first storage area and a second storage area;
the writing method comprises the following steps:
storing data having an access frequency within a first access frequency range in the first storage area; and
storing data having an access frequency within a second access frequency range in the second storage area;
wherein an access frequency in the first access frequency range is higher than an access frequency in the second access frequency range.
According to a third aspect of the present invention, there is provided a writing method of writing data into a storage apparatus, wherein the storage apparatus includes a controller, a data buffer, a first storing area, and a second storing area, the writing method including:
in response to receiving a first command including a write command and an address signal and a write address associated with the write command being on the second memory region, writing data into the first memory region;
reading the data written into the first storage area to the controller; and
and writing the data into different sub-storage areas of the second storage area according to the access frequency of the data read to the controller.
According to a fourth aspect of the present invention, there is provided a reading method of reading data from a memory apparatus, wherein the memory apparatus includes a first memory area and a second memory area, the reading method including reading out data in the second memory area via the first memory area.
According to a fifth aspect of the present invention, there is provided a data backup method of a storage apparatus, wherein the storage apparatus includes a controller, a first storage area, and a second storage area, the second storage area including a first sub storage area, a second sub storage area, and a third sub storage area;
the data backup method comprises the following steps:
receiving data to be backed up and storing the data to be backed up in the first storage area and the first and second sub storage areas;
reading the data in the first storage area to the controller in response to receiving a data backup signal, and simultaneously storing the data in the first sub storage area and the second sub storage area to the third sub storage area; and
and storing the data read from the first storage area to the controller into the third sub-storage area.
According to a sixth aspect of the present invention, there is provided a data recovery method of a storage apparatus, wherein the storage apparatus includes a first storage area and a second storage area, and the second storage area includes a first sub storage area, a second sub storage area, and a third sub storage area;
wherein the data restoring method includes restoring data in the first storage area stored during data backup from the third sub-storage area into the first storage area in response to receiving a restore data command.
It will be appreciated by those skilled in the art that the technical effects as set forth in relation to the first aspect of the invention can be achieved according to the second to sixth aspects of the invention. The storage device and the data writing, reading, backing up and recovering method thereof can improve the speed performance and reliability of the system and reduce the data backing up time and the requirement on the capacitor.
Drawings
Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the accompanying drawings. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. In the drawings, there is shown in the drawings,
FIG. 1 is a schematic diagram of a signal flow and interface of an NVDIMM-P of a prior art NVDIMM-P;
fig. 2 is a memory space distribution diagram in NVDIMM-P in accordance with one embodiment of the present invention.
Fig. 3 is an exemplary block diagram of an NVDIMM-P in accordance with one embodiment of the present invention.
Detailed Description
While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail one or more specific embodiments; it is to be understood that this disclosure is to be considered as illustrative of the principles of the invention and is not intended to limit the invention to the specific embodiments shown and described. Thus, processes, elements, and techniques not necessary to fully understand aspects and features of the invention may not be described by those of ordinary skill in the art.
It will be understood that, although the terms "first," "second," "third," etc. may be used in this disclosure to describe various elements, components, signals and/or frequencies, these elements, components, signals and/or frequency ranges should not be limited by these terms. These terms are used to distinguish one element, component, signal, or frequency range from another element, component, signal, or frequency range. Thus, a first element, component, signal, or frequency range described below could be termed a second element, component, signal, or frequency range without departing from the spirit and scope of the present invention.
The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this disclosure, the singular is intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Embodiments of the present invention relate to a storage device for storing data and data writing, reading, backing up, and restoring methods thereof. For example, the memory device in embodiments of the invention may be a non-volatile dual in-line memory module (NVDIMM) device, such as a P-type NVDIMM (NVDIMM-P) device.
According to a first aspect of the present invention, there is provided a storage apparatus, wherein the storage apparatus comprises: a host interface; a controller; a data buffer; a clock driver; a first storage area for storing data having an access frequency within a first access frequency range; and a second storage area for storing data having an access frequency within a second access frequency range; wherein the access frequency in the first access frequency range is higher than the access frequency in the second access frequency range.
According to a preferred embodiment of the first aspect of the present invention, wherein the first storage area comprises a plurality of volatile memories.
According to a preferred embodiment of the first aspect of the present invention, the data buffer is a plurality of buffers, and is connected to the plurality of volatile memories and the data channel of the host interface in a one-to-one correspondence manner. Since the data buffer is directly connected to a volatile memory such as a Random Access Memory (RAM), e.g., a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a Static Random Access Memory (SRAM), etc., the host can access the volatile memory through the data channel and the data buffer, making full use of the driving capability of the data buffer. Therefore, compared with the scheme of driving the volatile memory through the controller, the storage device of the embodiment of the invention can drive more volatile memory modules, increase the storage space of the storage device and simultaneously increase the access rate of the volatile memory.
According to a preferred embodiment of the first aspect of the present invention, wherein the data buffer is connected to the controller via a local data bus.
According to a preferred embodiment of the first aspect of the present invention, wherein the controller is connected to command and address channels of the host interface.
According to a preferred embodiment of the first aspect of the present invention, wherein the controller is connected with the clock driver via a command and data bus, a local command bus, respectively.
According to a preferred embodiment of the first aspect of the present invention, wherein the clock driver is connected to the first storage area and the data buffer, respectively.
According to a preferred implementation of the first aspect of the invention, the clock driver is connected with the data buffer via a data buffer command bus to configure the data buffer.
According to a preferred embodiment of the first aspect of the present invention, the second memory area comprises a plurality of sub memory areas, the second access frequency range comprises a plurality of sub access frequency ranges, and the plurality of sub memory areas are respectively used for storing data having access frequencies in different sub access frequency ranges.
According to a preferred embodiment of the first aspect of the present invention, wherein the second memory area comprises a first sub memory area, a second sub memory area and a third sub memory area;
the second access frequency range comprises a first sub-access frequency range with access frequency from high to low, a second sub-access frequency range and a third sub-access frequency range;
wherein the first sub memory area is for storing data having an access frequency within the first sub access frequency range, the second sub memory area is for storing data having an access frequency within the second sub access frequency range, and the third sub memory area is for storing data having an access frequency within the third sub access frequency range.
According to a preferred embodiment of the first aspect of the present invention, wherein the first sub-memory area is located in the controller.
According to a preferred embodiment of the first aspect of the present invention, wherein said first sub-memory area is a cache memory, preferably a static random access memory.
According to a preferred embodiment of the first aspect of the present invention, wherein the second sub-memory area is a local dynamic random access memory.
According to a preferred embodiment of the first aspect of the present invention, wherein the third sub-storage area is a non-volatile memory. Preferably, wherein the nonvolatile memory is a Flash, a phase change memory or a resistive random access memory.
According to a preferred embodiment of the first aspect of the present invention, wherein the controller is connected to the second sub memory area and the third sub memory area, respectively.
In writing data, the host divides the data into frequently accessed data (hot data) and infrequently accessed data (cold data) by the driver thereon, and writes the "hot data" to the address space of the volatile memory and writes the "cold data" to the address space of the cold data storage area. As described above, nonvolatile memory has some disadvantages relative to volatile memory. To reduce these disadvantages, the memory device of the embodiment of the present invention writes data having a relatively high access frequency among "cold data" into a buffer memory (such as SRAM, local DRAM, or the like) of the memory device, and writes data having a relatively low access frequency among "cold data" into the nonvolatile memory. In this way, the rate performance of the storage device is further improved, avoiding frequent accesses to non-volatile memory. According to the embodiment of the present invention, data having a higher access frequency is stored in a buffer memory having a higher access speed according to the access speed of each buffer memory in the storage device, so that the rate performance of the storage device is optimized.
According to a preferred embodiment of the first aspect of the present invention, wherein data having an access frequency within the second access frequency range is stored into the second memory area via the first memory area.
According to a preferred embodiment of the first aspect of the present invention, wherein the controller is configured to: in response to receiving a first command including a write command and an address signal and a write address associated with the write command being on the second storage region, writing data on a data channel of the host interface into a first storage region; reading the data written into the first storage area to the controller; and writing the data into different sub-storage areas of the second storage area according to the access frequency of the data read to the controller.
Therefore, in normal operation, the host can write data into a nonvolatile memory, such as a Flash (e.g., NAND Flash), a Phase-change memory (PCM, e.g., X-Point), a Resistive Random Access Memory (RRAM), or the like, through the host interface, thereby increasing the storage space of the storage device.
According to a preferred implementation of the first aspect of the invention, the controller receives the first command and address signals from a command and address channel of the host interface.
According to a preferred embodiment of the first aspect of the present invention, wherein the first storage area comprises a plurality of volatile memories; the controller is configured to:
encoding the write address such that the encoded write address is on the first memory region and resulting in encoded first command and address signals;
sending the encoded first command and address signals to the clock driver via a command and data bus between the controller and the clock driver; and is
The clock driver is configured to forward the encoded first command and address signals to the plurality of volatile memories to write data on the data channel to the encoded write addresses of the plurality of volatile memories.
According to a preferred embodiment of the first aspect of the present invention, wherein the data buffer is connected to the controller via a local data bus;
the controller is configured to send a second command and address signal including a read command and the encoded write address to the clock driver via a local command bus after writing data on the data channel to the encoded write address; and is
The clock driver is configured to, in response to receiving the second command and address signals, configure the data buffer and forward the second command and address signals to the plurality of volatile memories to read data in the encoded write addresses to the controller via the data buffer and the local data bus.
In an embodiment of the present invention, since the clock driver is disposed at a rear end of the controller, such as a non-volatile controller (NVC), the controller directly receives command and address signals issued by a host, and may encode addresses in the command and address signals so that addresses for accessing the nonvolatile memory are on the volatile memory, so that the volatile memory may serve as a buffer of the nonvolatile memory. In addition, by means of controller caching, the speed difference between the volatile memory and the nonvolatile memory is balanced, so that the host can stably access the nonvolatile memory with low overhead.
According to a preferred embodiment of the first aspect of the present invention, wherein data in the second storage area is read out via the first storage area.
According to a preferred embodiment of the first aspect of the present invention, wherein the controller is configured to:
in response to receiving a third command containing an internal write command and an address signal, and an access address associated with the internal write command is on the second memory area, reading data from an actual memory address corresponding to the access address in a data write phase;
writing the read data from the controller into the first storage area; and
in response to receiving a fourth command including a read command and an address signal and a read address associated with the read command is the same as the access address, the data is read out of the first storage area.
Therefore, in normal operation, the host can read out the data in the nonvolatile memory through the host interface.
According to a preferred implementation of the first aspect of the invention, the controller receives the third command and address signals and the fourth command and address signals from a command and address channel of the host interface.
According to a preferred embodiment of the first aspect of the present invention, wherein the first storage area comprises a plurality of volatile memories, the data buffer being connected to the controller via a local data bus;
the controller is configured to send fifth command and address signals to the clock driver via a local command bus, the fifth command and address signals including a write command and a write address on the plurality of volatile memories;
the clock driver is configured to, in response to receiving the fifth command and address signals, configure the data buffer and forward the fifth command and address signals to the plurality of volatile memories; and is
The controller is further configured to write data read from the real memory address to the write address via the local data bus and the data buffer.
According to a preferred embodiment of the first aspect of the present invention, wherein the controller is configured to: encoding the read address such that the encoded read address is the same as the write address and resulting in an encoded fourth command and address signal; and sending the encoded fourth command and address signals to the clock driver via a command and address bus between the controller and the clock driver; and is
The clock driver is configured to, in response to receiving the encoded fourth command and address signals, configure the data buffer and forward the encoded fourth command and address signals to the plurality of volatile memories to read out data in the write address via the data channel.
In the embodiment of the present invention, since the clock driver is disposed at the rear end of the controller, the controller directly receives a command and an address signal issued by a host, and writes data in the nonvolatile memory into the volatile memory, so that the volatile memory is used as a buffer of the nonvolatile memory. In addition, by means of controller caching, the speed difference between the volatile memory and the nonvolatile memory is balanced, so that the host can stably access the nonvolatile memory with low overhead.
According to a preferred embodiment of the first aspect of the present invention, wherein the storage device is configured to receive data to be backed up and store the data to be backed up in the first storing area and the first and second sub storing areas;
the controller is configured to:
reading the data in the first storage area to the controller in response to receiving a data backup signal, and simultaneously storing the data in the first sub storage area and the second sub storage area to the third sub storage area; and is
Storing the data read from the first storage area to the controller in the non-volatile memory.
The storage device according to the embodiment of the invention can back up the data in the nonvolatile memory when the host computer is abnormal or loses power.
According to a preferred embodiment of the first aspect of the present invention, wherein the first storage area comprises a plurality of volatile memories, the data buffer being connected to the controller via a local data bus;
the controller is configured to, in response to receiving the data backup signal, send a sixth command and address signal containing a backup command and a backup address to the clock driver via the local command bus;
the clock driver is configured to, in response to receiving the sixth command and address signals, configure the data buffer and forward the sixth command and address signals to the plurality of volatile memories to read data in the plurality of volatile memories to the controller via the data buffer and the local data bus.
The storage device reads the data in the volatile memory on one side, and backups the data in the cache memory of the storage device to the nonvolatile memory on the other side, so that the data backup speed is improved, and the requirement on the super capacitor is further reduced.
According to a preferred embodiment of the first aspect of the present invention, wherein the controller comprises a processing unit and is configured to, in response to receiving the data backup signal, sequentially perform the following steps during reading of the data in the plurality of volatile memories into the controller:
-storing data in the space of the first sub-memory area occupied by the processing unit to the second sub-memory area;
-storing data in the space of the first sub-memory area not occupied by the processing unit to the third sub-memory area; and
-storing the data in the second sub memory area to the third sub memory area.
According to a preferred embodiment of the first aspect of the present invention, an emergency power interface for connecting a backup power source is further included, and the controller is configured to switch the storage device to be powered through the emergency power interface in response to receiving the data backup signal. Alternatively or additionally, a backup power supply may be provided in the storage device to supply power in case of an abnormality or power failure of the host. Furthermore, it will be appreciated by those skilled in the art that the backup power source may be a battery, a capacitor (preferably a super capacitor), and/or any other suitable mechanism and/or device for power storage.
According to a preferred embodiment of the first aspect of the present invention, the controller is configured to perform power down of the storage device after storing the data read from the first memory area to the third sub memory area.
According to a preferred embodiment of the first aspect of the present invention, the storage apparatus is configured to restore the data in the first storage area stored during data backup from the third child storage area into the first storage area in response to receiving a restore data command.
According to a preferred embodiment of the first aspect of the present invention, wherein the controller is configured to, in response to receiving the restore data command, send the restore data command to the clock driver while reading the data in the first storing area stored during data backup from the third sub-storing area;
the clock driver is configured to, in response to receiving the resume data command, configure the data buffer and forward the resume data command to the first memory area; and is
The controller is further configured to write back data read from the third sub-storage area to the first storage area after the clock driver configures the data buffer and forwards the resume data command to the first storage area.
Therefore, the storage device can read the data backed up in the nonvolatile memory when the host computer is abnormal or loses power into the volatile memory for the host computer to read.
According to a preferred embodiment of the first aspect of the present invention, wherein the controller is configured to receive the resume data command via a system management bus of the host interface, send the resume data command to the clock driver via a local command bus, and write back data read from the third sub-storage area to the first storage area via a local data bus and the data buffer.
According to a second aspect of the present invention, there is provided a writing method of writing data into a storage apparatus, wherein the storage apparatus includes a first storage area and a second storage area; the writing method comprises the following steps:
storing data having an access frequency within a first access frequency range in the first storage area; and
storing data having an access frequency within a second access frequency range in the second storage area;
wherein the access frequency in the first access frequency range is higher than the access frequency in the second access frequency range.
According to a preferred embodiment of the second aspect of the present invention, wherein the writing method comprises: storing data having an access frequency within the second access frequency range into the second memory area via the first memory area.
According to a preferred embodiment of the second aspect of the present invention, wherein the first storage area comprises a plurality of volatile memories.
According to a preferred embodiment of the second aspect of the present invention, wherein the second memory area comprises a plurality of sub memory areas; the writing method comprises the following steps:
dividing the second access frequency range into a plurality of sub-access frequency ranges; and
and respectively storing the data with the access frequencies in different sub-access frequencies into corresponding sub-storage areas in the plurality of sub-storage areas.
According to a preferred embodiment of the second aspect of the present invention, wherein the second memory area includes a first sub memory area, a second sub memory area, and a third sub memory area; the writing method comprises the following steps:
dividing the second access frequency range into a first sub-access frequency range, a second sub-access frequency range and a third sub-access frequency range, wherein the access frequencies of the first sub-access frequency range, the second sub-access frequency range and the third sub-access frequency range are from high to low;
storing data having an access frequency within the first sub-access frequency range in the first sub-storage area;
storing data having an access frequency within the second sub-access frequency range in the second sub-storage area; and
storing data having an access frequency within the third sub-access frequency range in the third sub-storage area.
According to a preferred embodiment of the second aspect of the present invention, wherein the storage device comprises a controller, the first sub-storage area is located in the controller.
According to a preferred embodiment of the second aspect of the present invention, wherein said first sub-memory area is a cache memory, preferably a static random access memory.
According to a preferred embodiment of the second aspect of the present invention, wherein the second sub-memory area is a local dynamic random access memory.
According to a preferred embodiment of the second aspect of the present invention, wherein the third sub-storage area is a non-volatile memory. Preferably, the nonvolatile memory is a Flash, a phase change memory or a resistive random access memory.
According to a third aspect of the present invention, there is provided a writing method of writing data into a storage apparatus, wherein the storage apparatus includes a controller, a data buffer, a first storing area, and a second storing area, the writing method including:
in response to receiving a first command including a write command and an address signal and a write address associated with the write command being on the second memory region, writing data into the first memory region;
reading the data written into the first storage area to the controller; and
and writing the data into different sub-storage areas of the second storage area according to the access frequency of the data read to the controller.
According to a preferred embodiment of the third aspect of the present invention, wherein the first storage area includes a plurality of volatile memories, the storage apparatus further includes a clock driver, the writing method includes:
encoding the write address such that the encoded write address is on the plurality of volatile memories and resulting in encoded first command and address signals;
sending the encoded first command and address signals to the clock driver; and
forwarding the encoded first command and address signals to the plurality of volatile memories to write the data to the encoded write addresses of the plurality of volatile memories.
According to a preferred embodiment of the third aspect of the present invention, wherein the data buffer is connected with the plurality of volatile memories and with the controller via a local data bus, the writing method comprises:
after writing the data to the encoded write address, sending a second command and address signal including a read command and the encoded write address to the clock driver;
configuring the data buffer and forwarding the second command and address signals to the plurality of volatile memories; and
reading data in the encoded write address to the controller via the data buffer and the local data bus.
According to a preferred embodiment of the third aspect of the present invention, wherein the writing method comprises:
storing data having an access frequency within a first access frequency range in the first storage area; and
storing data having an access frequency within a second access frequency range in the second storage area;
wherein the access frequency in the first access frequency range is higher than the access frequency in the second access frequency range.
According to a preferred embodiment of the third aspect of the present invention, wherein the second memory area includes a first sub memory area, a second sub memory area, and a third sub memory area; the writing method comprises the following steps:
dividing the second access frequency range into a first sub-access frequency range, a second sub-access frequency range and a third sub-access frequency range, wherein the access frequencies of the first sub-access frequency range, the second sub-access frequency range and the third sub-access frequency range are from high to low;
storing data having an access frequency within the first sub-access frequency range in the first sub-storage area;
storing data having an access frequency within the second sub-access frequency range in the second sub-storage area; and
storing data having an access frequency within the third sub-access frequency range in the third sub-storage area.
According to a fourth aspect of the present invention, there is provided a reading method of reading data from a memory apparatus, wherein the memory apparatus includes a first memory area and a second memory area, the reading method including reading out data in the second memory area via the first memory area.
According to a preferred embodiment of the fourth aspect of the present invention, wherein the storage device includes a controller, the reading method includes:
in response to receiving a third command containing an internal write command and an address signal, and an access address associated with the internal write command is on the second memory area, reading data from an actual memory address corresponding to the access address in a data write phase;
writing the data from the controller into the first storage area; and
in response to receiving a fourth command including a read command and an address signal and a read address associated with the read command is the same as the access address, the data is read out of the first storage area.
According to a preferred embodiment of the fourth aspect of the present invention, wherein the storage device comprises a data buffer, the first storage area comprises a plurality of volatile memories, the reading method comprises:
sending fifth command and address signals to the clock driver, the fifth command and address signals containing a write command and a write address on the plurality of volatile memories;
configuring the data buffer and forwarding the fifth command and address signals to the plurality of volatile memories; and
writing the data to a write address on the plurality of volatile memories.
According to a preferred embodiment of the fourth aspect of the present invention, wherein the reading method comprises:
encoding the read address such that the encoded read address is the same as the write address and resulting in an encoded fourth command and address signal;
sending the encoded fourth command and address signals to the clock driver;
configuring the data buffer and forwarding the encoded fourth command and address signals to the plurality of volatile memories; and
reading the data from the write addresses of the plurality of volatile memories.
According to a fifth aspect of the present invention, there is provided a data backup method of a storage apparatus, wherein the storage apparatus includes a controller, a first storage area, and a second storage area, the second storage area including a first sub storage area, a second sub storage area, and a third sub storage area; the data backup method comprises the following steps:
receiving data to be backed up and storing the data to be backed up in the first storage area and the first and second sub storage areas;
reading the data in the first storage area to the controller in response to receiving a data backup signal, and simultaneously storing the data in the first sub storage area and the second sub storage area to the third sub storage area; and
and storing the data read from the first storage area to the controller into the third sub-storage area.
According to a preferred embodiment of the fifth aspect of the present invention, wherein the storage means comprises a clock driver and a data buffer, the first storage area comprises a plurality of volatile memories; the data backup method comprises the following steps:
in response to receiving the data backup signal, sending a sixth command and address signal containing a backup command and a backup address to the clock driver;
configuring the data buffer and forwarding the sixth command and address signals to the plurality of volatile memories; and
reading data in the plurality of volatile memories to the controller.
According to a preferred embodiment of the fifth aspect of the present invention, wherein the controller comprises a processing unit, the data backup method comprises:
sequentially performing the following steps during the reading of the data in the plurality of volatile memories to the controller:
-storing data in the space of the first sub-memory area occupied by the processing unit to the second sub-memory area;
-storing data in the space of the first sub-memory area not occupied by the processing unit to the third sub-memory area; and
-storing the data in the second sub memory area to the third sub memory area.
According to a preferred embodiment of the fifth aspect of the present invention, wherein the storage means comprises an emergency power interface for connecting a backup power source, preferably a super capacitor; the data backup method comprises the following steps: switching the storage device to supply power through the emergency power interface in response to receiving the data backup signal.
According to a preferred embodiment of the fifth aspect of the present invention, wherein the data backup method comprises: performing power down of the storage apparatus after storing the data read from the first storing area into the third sub-storing area.
According to a sixth aspect of the present invention, there is provided a data recovery method of a storage apparatus, wherein the storage apparatus includes a first storage area and a second storage area, and the second storage area includes a first sub storage area, a second sub storage area, and a third sub storage area;
wherein the data restoring method includes restoring data in the first storage area stored during data backup from the third sub-storage area into the first storage area in response to receiving a restore data command.
According to a preferred embodiment of the sixth aspect of the present invention, wherein the storage device includes a clock driver and a data buffer, the data recovery method includes:
sending the restore data command to the clock driver while reading data in the first storage area stored during data backup from the third sub-storage area;
configuring the data buffer and forwarding the resume data command to the first memory area; and
and writing back the data read from the third sub-storage area to the first storage area.
According to a preferred embodiment of the sixth aspect of the present invention, wherein the storage device includes a host interface, the data recovery method includes:
receiving the resume data command via a system management bus of the host interface;
sending the resume data command to the clock driver via a local command bus; and
writing back data read from the third sub-storage area to the first storage area via a local data bus and the data buffer.
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Fig. 2 is a memory space distribution diagram in NVDIMM-P in accordance with one embodiment of the present invention. As shown in fig. 2, the memory space of the non-volatile dual in-line memory module NVDIMM 20 generally includes a first memory region ("hot region") 21 and a second memory region ("cold region") 22.
In embodiments of the present invention, "hot zone" refers to an area that is frequently read and written by a host or central processing unit (i.e., storing data that is frequently accessed by the host or central processing unit), and "cold zone" refers to an area that is not frequently read and written by a host or central processing unit (i.e., storing data that is not frequently accessed by the host or central processing unit). Here, whether to read and write frequently is defined according to a specific situation.
The second storage area ("cold area") 22 is divided into a first sub-storage area 221, a second sub-storage area 222 … …, an nth sub-storage area 22n according to the access frequency of the host or the central processing unit, and the host or the central processing unit has different read and write frequencies to the sub-storage areas 221, 222 … 22n, respectively, that is, the sub-storage areas store data of the host access frequency having different access frequency ranges.
Fig. 3 is an exemplary block diagram of an NVDIMM-P in accordance with one embodiment of the present invention. As shown in fig. 3, the non-volatile dual in-line memory module NVDIMM300 of this embodiment includes a plurality of dynamic random access memory DRAMs 301, a NAND Flash302, a local DRAM 303, a controller 304, a clock driver RCD 305, and a plurality of data buffer DBs 306. The controller 304 is connected to the NAND Flash302, the local DRAM 303, the clock driver 305 through the local command bus LCOM and the command and address bus CA2, and the plurality of data buffers 306 through the local data bus LDQ. The clock driver 305 is connected to the plurality of dynamic random access memories 301, and configures the data buffer 306 through the data buffer command bus BCOM. NVDIMM300 also includes a host interface through which NVDIMM300 connects with a host or central processing unit, the host interface including command and address pin CA1, a SAVE _ n pin, system management bus pin SMBus, and data pin DQ.
In addition, the plurality of data buffers 306 are connected to the plurality of dynamic random access memories 301 and the DQ pins, respectively, in one-to-one correspondence. In contrast to the solution of fig. 1, in an embodiment of the present invention, the host can directly access the dynamic random access memory 301 through the data buffer 306, instead of accessing the dynamic random access memory through the controller. Thus, the driving capability of the data buffer 306 is fully utilized, the access speed of the memory module is increased, and the memory module can be configured with more dynamic random access memories 301.
In an embodiment of the present invention, dynamic random access memory is ultimately used to store "hot data" and non-volatile memory is ultimately used to store "cold data". In the present invention, "hot data" refers to data that is frequently accessed by the host or the central processing unit, and "cold data" refers to data that is infrequently accessed by the host or the central processing unit. As described above, the dynamic random access memory belongs to the "hot zone", and the nonvolatile memory belongs to the "cold zone". When writing data, the drive on the host will distinguish between "hot data" (having an access frequency in a first access frequency range) and "cold data" (having an access frequency in a second access frequency range), while the drive also knows the address space of the dynamic random access memory and the non-volatile memory on the memory module. It should be understood that, in the present invention, the nonvolatile memory may be Flash (e.g., nand Flash), Phase-change memory (PCM, e.g., X-Point), or Resistive Random Access Memory (RRAM), etc.
In NVDIMM300 of fig. 3, the host can access the dynamic random access memory 301 and NAND Flash302 in the "cold zone" during normal operation, thereby increasing the memory space of the system. Thus, in an embodiment of the invention, NVDIMM300 implements the functionality of a P-type NVDIMM (NVDIMM-P).
The configuration of NVDIMM300 in fig. 3 is further described below in connection with the process of the host writing "cold data" to and reading "cold data" from "cold regions" of the storage device of the present invention (i.e., the host writing "cold data" and reading "cold data").
The host writing 'cold data' comprises two steps:
in a first step, cold data is written from the "host" into the "dynamic random access memory":
when a driver on the host determines that the data to be stored on NVDIMM300 is "cold data," the host sends the "cold data" to NVDIMM300 through the host interface of NVDIMM300 along with the write address of the write command and the cold data (i.e., the host issues the cold data and its command and address signals). The controller 304 receives command and address signals through the command and address pins CA1 and re-encodes the command and address signals to obtain encoded command and address signals, wherein the write address (i.e., the encoded write address) in the encoded command and address signals falls on the dynamic random access memory 301. Controller 304 then sends the encoded command and address signals to clock driver 305 over command and address bus CA2 between controller 304 and clock driver 305. The clock driver 305, in response to the encoded command and address signals, configures the data buffer 306 and sends the encoded command and address signals to the dynamic random access memory 301 so that the host has operational control of the dynamic random access memory 301 whereby the host can write the "cold data" from the host into one or more of the plurality of dynamic random access memories 301.
Second, cold data is written from the "dynamic random access memory" into the "cold data storage area" (i.e., "cold zone" 22):
the controller 304 sends command and address signals containing read command and address (address of said "cold data" in the dynamic random access memory 301) to the clock driver 305 via the local command bus LCOM, and the clock driver 305 configures the data buffer 306 via the data buffer command bus BCOM and sends the command and address signals to the dynamic random access memory 301 so that the operation control authority of the dynamic random access memory 301 is switched to the controller 304, whereby the controller 304 can read the "cold data" in the dynamic random access memory 301 to the buffer space in the controller 304 via the data buffer 306 and the local data bus LDQ.
As can be seen, the dynamic random access memory 301 serves to cache data.
In an embodiment of the present invention, each of the plurality of dynamic random access memories 301 reserves a buffer having a fixed space size for buffering cold data. Preferably, the spatial sizes of these buffers are each greater than 64 KB. Factors to be considered when opening up the size of these buffers are the rate at which the host accesses the dynamic random access memory, the rate at which the controller accesses the dynamic random access memory, and the rate at which the controller accesses the non-volatile memory.
In an embodiment of the present invention, the controller 304 has a cache memory (such as an SRAM) and a processing unit. Here, the cache memory of the controller 304 is the cache space in the controller 304.
It should be noted that in the embodiment of the present invention, if there is an abnormal event such as power failure, the "cold data" is finally stored in the non-volatile memory (i.e. the NAND Flash302 shown in fig. 3) of the storage device; on the contrary, if no abnormality such as power failure occurs, the "cold data" is not required to be stored in the nonvolatile memory of the storage device.
To further improve the rate performance of the memory module and avoid frequent accesses to the non-volatile memory, thereby avoiding damage to the non-volatile memory, in an embodiment of the present invention, the controller 304 will sequentially write these "cold data" into the cache memory of the controller 304, the local DRAM 303, or the NAND Flash302 according to a caching algorithm.
The general idea of the cache algorithm is as follows: dividing a cold data storage area of a storage device into different sub-storage areas; the "cold data" is stored in the different sub-storage areas accordingly, depending on the sub-access frequency ranges to which the access frequency belongs.
More specifically, the second access frequency range includes a first sub-range, a second sub-range and a third sub-range from high access frequency to low access frequency; the "cold data" having an access frequency within the first sub-range is cached in a cache memory (such as SRAM) of the controller 304, the "cold data" having an access frequency within the second sub-range is cached in the local DRAM 303, and the "cold data" having an access frequency within the third range (i.e., the relatively lowest access frequency) is stored in the nand flash 302.
When writing the "cold data", the controller 304 allocates a mapping table to one-to-one correspond the write address of the "cold data" input by the host to the actual storage address of the "cold data".
The host reading "cold data" from the "cold zone" includes two steps:
in the first step, cold data is read from the "cold area" into the "dynamic random access memory":
when the host needs to read "cold data" from the "cold region," the host first sends an internal write command and the theoretical memory address of the "cold data" to NVDIMM300 (i.e., the host issues command and address signals that write the "cold data" into the DRAM). The theoretical memory address is the address that the slave host wishes to write and read. Specifically, the controller 304 receives the command and address signals through the command and address pin CA1, and obtains an actual storage address in the NAND Flash302, the local DRAM 303, or the SRAM of the controller 304 corresponding to the theoretical storage address of the "cold data" according to the mapping table stored in the write phase, so as to read the "cold data" in the actual storage address to the controller 304. After reading out these "cold data", the controller 304 sends command and address signals, which internally write commands and addresses on the dynamic random access memory 301, to the clock driver 305 via the local command bus LCOM, and the clock driver 305 configures the data buffer 306 via the data buffer command bus BCOM and sends the command and address signals to the dynamic random access memory 301, so that the controller 304 has the operation control of the dynamic random access memory 301, whereby the controller 304 can store the "cold data" into the dynamic random access memory 301 via the local data bus LDQ and the data buffer 306.
Second, read cold data from "dynamic random access memory" into "host":
after storing these "cold data" in the dram301, the host sends a read command and the theoretical memory address of the "cold data" (i.e., command and address signals for reading the "cold data"). The controller 304 receives the command and address signals via the command and address pins CA1 and re-encodes the theoretical memory address of "cold data" to obtain encoded command and address signals, wherein the encoded read address falls on the address of the dynamic random access memory 301 where the "cold data" is stored. Controller 304 then sends the encoded command and address signals to clock driver 305 over command and address bus CA2 between controller 304 and clock driver 305. The clock driver 305 configures the data buffer 306 and transmits the encoded command and address signals to the dynamic random access memory 301 in response to the encoded command and address signals, so that the host has an operation control of the dynamic random access memory 301, whereby the host can read out the above-mentioned "cold data".
The nonvolatile dual in-line storage module can store and backup data in the host computer to a nonvolatile memory in the storage module when the host computer is abnormal or loses power, thereby realizing nonvolatile property. In the system provided with the nonvolatile dual in-line storage module, after the system is powered on, the host can acquire the information whether the power failure is abnormal last time: if the last time is normal shutdown, the host computer is normally started; otherwise the host enters a data recovery state. The construction of NVDIMM300 in fig. 3 is further described below in connection with the process of backing up data into NVDIMM300 and recovering data from NVDIMM300 upon an abnormal power loss to the host.
When a Board Management Controller (BMC) or a module with similar functions of the host detects an ac drop, the host ADR refreshes the cache data into the dynamic random access memory DRAM301 or the cache memory of the nonvolatile dual in-line memory module (such as the SRAM, the local DRAM 303, etc. of the Controller 304). Then, the host pulls the SAVE _ n pin low and then high to inform the nonvolatile dual in-line memory module to perform data backup. Upon receiving the data backup signal, controller 304 switches NVDIMM300 to be powered by its connected super capacitor 400. Then, the controller 304 transmits command and address signals for backing up data in the DRAM301, which include an address at which data in the DRAM301 is to be stored in the NAND Flash302, to the clock driver 305 via the local command bus LCOM. The clock driver 305 configures the data buffer 306 via the data buffer command bus BCOM and transmits the command and address signals to the DRAM301 in response to the command and address signals, so that the controller 304 obtains control of the DRAM301, whereby the controller 304 can read data in the DRAM301 into the controller 304 via the data buffer 306 and the local data bus LDQ. While reading the data in the DRAM301, the controller 304 first refreshes the data in the cache memory occupied by its processing unit into the local DRAM 303, then stores the data in the SRAM of the controller 304 into the NAND Flash302, and finally stores the data in the local DRAM 303 into the NAND Flash 302. Since a certain period of time is required to read the data in the DRAM301, the cache memory occupied by the parallel backup processing unit, the SRAM of the controller 304, and the data in the local DRAM 303 shorten the overall backup time, thereby reducing the requirement for the super capacitor 400.
After the controller 304 reads the data in the DRAM301, the controller 304 stores the data in the aforementioned address in the nand flash 302. Subsequently, controller 304 performs a power down of NVDIMM300, i.e., supercapacitor 400 is no longer powered.
If the host detects that the system is powered on and the last time is abnormal power failure and correct data backup exists in the NVDIMM300, the host issues a data recovery command through a system management bus pin SMBus. The controller 304, upon receiving the restore data command, sends the restore data command to the clock driver 305 via the local command bus LCOM while reading the data in the DRAM301 stored during the data backup from the NAND Flash 302. The clock driver 305 configures the data buffer 306 via the data buffer command bus BCOM and transmits the recovery data command to the DRAM301 in response to the recovery data command, so that the controller 304 has an operation control of the DRAM 301. Thus, after reading data from the NAND Flash302, the controller 304 can write back the data into the DRAM301 via the local data bus LDQ and the data buffer 306. Subsequently, the host can read out the data written back into the DRAM 301.
As will be clear to a person skilled in the art, many different ways of performing the method are possible. For example, the order of the steps may be varied or some steps may be performed in parallel. In addition, other method steps may be inserted between the steps. The inserted steps may represent modifications of the method, such as those described herein, or may be unrelated to the method. Furthermore, a given step may not have been completely completed before the next step is initiated.
In one or more embodiments, systems and/or modules and/or units and/or circuits and/or blocks may be provided in whole or in part in hardware and/or firmware, including but not limited to: one or more Application Specific Integrated Circuits (ASICs), digital signal processors, discrete circuitry, logic gates, standard integrated circuits, state machines, look-up tables, controllers (e.g., by executing appropriate instructions and including microcontrollers and/or embedded controllers), Field Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), and the like, as well as various combinations thereof. In particular, in one or more embodiments, controllers, processing units, clock drivers, volatile memory, non-volatile memory, data buffers, caches, and the like may be implemented, in whole or in part, as so-called Application Specific Integrated Circuits (ASICs), i.e., Integrated Circuits (ICs) tailored to their particular use. Furthermore, in one or more embodiments, methods according to the present invention may be performed using software that may have been downloaded and/or stored in a corresponding memory, e.g., volatile memory (such as RAM, DRAM, SRAM, etc.) or non-volatile memory (such as CD-ROM, flash memory devices, etc.). Alternatively, the device may be implemented in whole or in part with programmable logic, e.g., as a Field Programmable Gate Array (FPGA). For example, the circuit may be implemented in CMOS, for example using a hardware description language (such as Verilog, VHDL, etc.).
While various preferred embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined in the appended claims.
Claims (10)
1. A memory device, comprising:
a host interface;
a controller;
a data buffer;
a clock driver;
a first storage area for storing data having an access frequency within a first access frequency range; and
a second storage area for storing data having an access frequency within a second access frequency range;
wherein the access frequency in the first access frequency range is higher than the access frequency in the second access frequency range.
2. The storage device of claim 1, wherein the first storage area comprises a plurality of volatile memories.
3. The memory device according to claim 2, wherein the data buffer is a plurality of buffers, and is connected to the plurality of volatile memories and the data channel of the host interface in a one-to-one correspondence.
4. A storage device according to any of claims 1 to 3, wherein the data buffer is connected to the controller via a local data bus.
5. The storage device of any of claims 1 to 4, wherein the controller interfaces with command and address channels of the host interface.
6. A writing method of writing data into a storage apparatus, characterized in that the storage apparatus includes a first storage area and a second storage area;
the writing method comprises the following steps:
storing data having an access frequency within a first access frequency range in the first storage area; and
storing data having an access frequency within a second access frequency range in the second storage area;
wherein the access frequency in the first access frequency range is higher than the access frequency in the second access frequency range.
7. A writing method of writing data into a storage apparatus, the storage apparatus including a controller, a data buffer, a first storing area, and a second storing area, the writing method comprising:
in response to receiving a first command including a write command and an address signal and a write address associated with the write command being on the second memory region, writing data into the first memory region;
reading the data written into the first storage area to the controller; and
and writing the data into different sub-storage areas of the second storage area according to the access frequency of the data read to the controller.
8. A reading method of reading data from a memory apparatus, wherein the memory apparatus includes a first memory area and a second memory area, the reading method comprising reading out data in the second memory area via the first memory area.
9. The data backup method of the storage device is characterized in that the storage device comprises a controller, a first storage area and a second storage area, wherein the second storage area comprises a first sub storage area, a second sub storage area and a third sub storage area;
the data backup method comprises the following steps:
receiving data to be backed up and storing the data to be backed up in the first storage area and the first and second sub storage areas;
reading the data in the first storage area to the controller in response to receiving a data backup signal, and simultaneously storing the data in the first sub storage area and the second sub storage area to the third sub storage area; and
and storing the data read from the first storage area to the controller into the third sub-storage area.
10. A data recovery method of a storage device is characterized in that the storage device comprises a first storage area and a second storage area, wherein the second storage area comprises a first sub storage area, a second sub storage area and a third sub storage area;
wherein the data restoring method includes restoring data in the first storage area stored during data backup from the third sub-storage area into the first storage area in response to receiving a restore data command.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022132481A1 (en) * | 2020-12-18 | 2022-06-23 | Micron Technology, Inc. | Object management in tiered memory systems |
| CN115586869A (en) * | 2022-09-28 | 2023-01-10 | 中国兵器工业计算机应用技术研究所 | Ad hoc network system and stream data processing method thereof |
| CN117711458A (en) * | 2024-02-06 | 2024-03-15 | 浙江力积存储科技有限公司 | Semiconductor memory device, method for reducing write recovery time of semiconductor memory device, and memory array |
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2020
- 2020-03-27 CN CN202010228971.7A patent/CN111309646A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022132481A1 (en) * | 2020-12-18 | 2022-06-23 | Micron Technology, Inc. | Object management in tiered memory systems |
| CN115586869A (en) * | 2022-09-28 | 2023-01-10 | 中国兵器工业计算机应用技术研究所 | Ad hoc network system and stream data processing method thereof |
| CN115586869B (en) * | 2022-09-28 | 2023-06-06 | 中国兵器工业计算机应用技术研究所 | Ad hoc network system and stream data processing method thereof |
| CN117711458A (en) * | 2024-02-06 | 2024-03-15 | 浙江力积存储科技有限公司 | Semiconductor memory device, method for reducing write recovery time of semiconductor memory device, and memory array |
| CN117711458B (en) * | 2024-02-06 | 2024-05-03 | 浙江力积存储科技有限公司 | Semiconductor memory device, method for reducing write recovery time of semiconductor memory device, and memory array |
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