CN115148716A - Semiconductor packaging structure and manufacturing method thereof - Google Patents
Semiconductor packaging structure and manufacturing method thereof Download PDFInfo
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- CN115148716A CN115148716A CN202110336530.3A CN202110336530A CN115148716A CN 115148716 A CN115148716 A CN 115148716A CN 202110336530 A CN202110336530 A CN 202110336530A CN 115148716 A CN115148716 A CN 115148716A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor packaging structure and a manufacturing method thereof, wherein the semiconductor packaging structure comprises: the semiconductor device comprises a first bare chip, a pre-wiring substrate, a plastic package layer, a plurality of conductive plugs, a first conductive trace, a first conductive bump, a first dielectric layer and a passive device. The pre-wiring substrate can transfer a wiring layer required to be formed on the active surface of the die into the pre-wiring substrate, and the pre-wiring substrate comprises complex multiple circuits which are embedded into the packaging structure through being electrically connected with the bonding pads on the active surface of the die, so that the performance of the whole semiconductor packaging structure can be improved, and the passive device can be incorporated into the packaging structure. The pre-wiring substrate can be tested prior to packaging, avoiding the use of known poor pre-wiring substrates. The pre-wiring substrate is a prefabricated substrate, the manufacturing process is independent of the packaging process, and the packaging time of the whole packaging process can be saved.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a semiconductor packaging structure and a manufacturing method thereof.
Background
With the miniaturization and light weight of electronic devices, semiconductor package structures with compact structures and small volumes are gaining increasing market favor.
As the integration of chips is higher and the functions realized are more complex, the packaging of chips has recently presented more and more complex rewiring requirements, which can result in wiring difficulties because the chip surface area is too small. In addition, the fine wiring is easy to generate short circuit due to the fact that the wiring is too dense, so that the yield of products is affected, and meanwhile, the service life of the chip is also short; especially in the case of forming a plurality of wiring layers, the process is difficult to manage due to the complexity of the process.
Disclosure of Invention
The present invention is directed to a semiconductor package and a method for fabricating the same, which solves the problems of the related art.
To achieve the above object, a first aspect of the present invention provides a semiconductor package structure, comprising:
a first die comprising a number of first bonding pads, the first bonding pads located on an active side of the first die;
the pre-wiring substrate is internally provided with a pre-wiring circuit, the pre-wiring circuit comprises a front side electric connection point and a back side electric connection point, the front side electric connection point is exposed on the front side of the pre-wiring substrate, and the back side electric connection point is exposed on the back side of the pre-wiring substrate; the back surface of the pre-wiring substrate faces the back surface of the first die;
the plastic package layer covers the first bare chip and the pre-wiring substrate, the back surface of the plastic package layer exposes the front surface of the pre-wiring substrate, and the front surface of the plastic package layer exposes the active surface of the first bare chip;
the conductive plugs are positioned in the plastic package layer and positioned on the side edge of the first bare chip, each conductive plug comprises a first end and a second end which are opposite, the first ends are connected to the back surface electric connection points, and the second ends are exposed to the front surface of the plastic package layer;
a first conductive trace on the first pad, the second end of the conductive plug, and the front side of the molding layer for electrically connecting the first die with the pre-routing line;
a first conductive bump connected to the first conductive trace;
a first dielectric layer embedding the first conductive trace and the first conductive bump, the first conductive bump being exposed outside the first dielectric layer; and
and the passive device is electrically connected to the front side electric connection point of the pre-wiring substrate.
Optionally, the active side of the first die is covered with a first protective layer that exposes the first pad; the front surface of the plastic packaging layer exposes the first protective layer and the first bonding pad; the first conductive trace is also on the first protective layer.
Optionally, the method further comprises: a second die comprising a number of second bonding pads, the second bonding pads located on an active side of the second die; an active side of the second die is covered with a second protective layer that exposes the second pad; the back surface of the second bare chip faces the back surface of the pre-wiring substrate; the plastic packaging layer also covers the second bare chip; the conductive patch is also located on a side of the second die; the first conductive trace is also located at the second pad for electrically connecting the first die, the second die, and the pre-routing line.
Optionally, the method further comprises: a third dielectric layer on the active surface of the first die, the second end of the conductive plug, and the front surface of the molding layer; the third dielectric layer exposes the first pad and a second end of the conductive plug; the first conductive trace is located at the first pad a second end of the conductive plug and on the third dielectric layer.
Optionally, the method further comprises: a second conductive trace on the first conductive bump and the first dielectric layer;
a second conductive bump connected to the second conductive trace;
a second dielectric layer embedding the second conductive trace and the second conductive bump, the second conductive bump being exposed outside the second dielectric layer.
A second aspect of the present invention provides a method for manufacturing a semiconductor package structure, including:
providing a plurality of groups of parts to be molded, wherein each group of parts to be molded comprises: a first die comprising a number of first bonding pads, the first bonding pads located on an active side of the first die; the pre-wiring substrate is internally provided with a pre-wiring circuit, the pre-wiring circuit comprises a front side electric connection point and a back side electric connection point, the front side electric connection point is exposed on the front side of the pre-wiring substrate, and the back side electric connection point is exposed on the back side of the pre-wiring substrate; the back surface of the pre-wiring substrate faces the back surface of the first die;
forming a plastic packaging layer, wherein the plastic packaging layer coats the multiple groups of pieces to be molded, the back surface of the plastic packaging layer exposes the front surface of each pre-wiring substrate, and the front surface of the plastic packaging layer exposes the active surface of each first bare chip;
forming a plurality of conductive plugs in the molding layer, wherein the conductive plugs are located on the side of the first bare chip and comprise a first end and a second end which are opposite, the first end is connected to the back side electric connection point, and the second end is exposed on the front side of the molding layer; forming first conductive traces on the first pads, second ends of the conductive plugs, and a front side of the molding layer to electrically connect the first dies within a group with the pre-routing lines;
forming a first conductive bump on the first conductive trace and a first dielectric layer embedding the first conductive trace and the first conductive bump, the first conductive bump being exposed outside the first dielectric layer;
electrically connecting a passive device to the front electrical connection points of the pre-wiring substrate;
and cutting to form a plurality of semiconductor packaging structures, wherein each semiconductor packaging structure comprises a group of to-be-molded parts.
Optionally, the forming the plastic package intermediate includes:
multiple groups of to-be-molded components are carried on a carrier plate, and the active surface of each first bare chip faces the carrier plate;
the forming of the plastic package layer comprises:
forming a plastic package layer for embedding each group of the parts to be plastic-packaged on the surface of the carrier plate;
removing the carrier plate to expose the active surface of each first bare chip and the front surface of the plastic packaging layer; and thinning the plastic packaging layer until the front surface of each pre-wiring substrate is exposed before removing the carrier plate or after forming the first dielectric layer.
Optionally, the active side of the first die is covered with a first protective layer having a first opening exposing the first pad; the first openings serve as alignment pattern features to arrange the first bare chips on the carrier board according to a preset arrangement position.
Optionally, the back side of the first die has alignment marks to apply the pre-wiring substrate to the back side of the first die.
Optionally, the multiple groups of to-be-molded components are carried on a carrier plate, and the front surface of each pre-wiring substrate faces the carrier plate;
the forming of the plastic package layer comprises:
forming a plastic package layer for embedding each group of the parts to be plastic-packaged on the surface of the carrier plate; thinning the plastic packaging layer until the active surface of each first bare chip is exposed;
and removing the carrier plate, and exposing the front surface of each pre-wiring substrate and the back surface of the plastic packaging layer.
Optionally, the active side of the first die is covered with a first protective layer; thinning the plastic packaging layer until the first protective layer is exposed; forming a first opening in the first protective layer exposing the first pad before forming the first conductive trace; or
An active side of the first die is covered with a first protective layer having a first opening exposing the first pad; and thinning the plastic packaging layer until the first protective layer and the first bonding pad are exposed.
Optionally, each group of the to-be-molded parts further includes: a second die comprising a number of second bonding pads, the second bonding pads located on an active side of the second die; the active surface of the second bare chip is covered with a second protective layer; the back surface of the second bare chip faces the back surface of the pre-wiring substrate.
Optionally, the pre-wiring substrates of the to-be-molded parts of each group are connected together, and the step of cutting to form a plurality of semiconductor packaging structures is performed by cutting.
Compared with the prior art, the invention has the beneficial effects that:
first, the pre-wiring substrate can transfer wiring layers required to be formed on the active surface of the die into the pre-wiring substrate, which includes complex multiple circuits embedded in the package structure by being electrically connected to pads on the active surface of the die, can improve the performance of the entire semiconductor package structure, and also enables passive devices to be incorporated into the semiconductor package structure. And secondly, fine wiring in the rewiring layer is transferred to the pre-wiring substrate, so that the probability of short circuit is reduced, the product yield is increased, the number of layers of conductive traces can be reduced, and the process complexity is reduced. Third, a pre-formed pre-wiring substrate is provided that allows testing of the pre-wiring substrate prior to packaging, avoiding the use of known poor pre-wiring substrates. Fourthly, the pre-wiring substrate is a prefabricated substrate, the manufacturing process is independent of the packaging process, and the packaging time of the whole packaging process can be saved.
In addition, the semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor package structure according to a first embodiment of the invention;
FIG. 2 is a flow chart of a method of fabricating the semiconductor package structure of FIG. 1;
FIGS. 3-11 are intermediate schematic diagrams corresponding to the flow chart of FIG. 2;
fig. 12 is a schematic cross-sectional view of a semiconductor package structure according to a second embodiment of the present invention;
fig. 13 is a schematic cross-sectional view of a semiconductor package structure according to a third embodiment of the invention;
fig. 14 is a schematic cross-sectional view of a semiconductor package structure according to a fourth embodiment of the invention.
To facilitate an understanding of the invention, all reference numerals appearing in the invention are listed below:
First protective layer 110 first pad 111
Pre-wiring substrate 12 pre-wiring line 120
Front electrical connection point 121 and back electrical connection point 122
Plastic-sealing layer 13 front surface 13a of plastic-sealing layer
Back 13b conductive plug 14 of plastic packaging layer
First end of conductive plug 14a second end of conductive plug 14b
First conductive trace 15 first conductive bump 16
First dielectric layer 17 passive device 18
Second conductive trace 19 second conductive bump 20
First opening 110a second opening 230a
A carrier plate 3 of the part 2 to be plastic-sealed
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic cross-sectional view of a semiconductor package structure according to a first embodiment of the invention.
Referring to fig. 1, a semiconductor package 1 includes:
a first die 11, the first die 11 including a plurality of first bonding pads 111, the first bonding pads 111 being located on an active surface 11a of the first die 11;
a pre-wiring substrate 12, a pre-wiring line 120 is arranged in the pre-wiring substrate 12, the pre-wiring line 120 comprises a front surface electrical connection point 121 and a back surface electrical connection point 122, the front surface electrical connection point 121 is exposed on the front surface 12a of the pre-wiring substrate 12, and the back surface electrical connection point 122 is exposed on the back surface 12b of the pre-wiring substrate 12; the back surface 12b of the pre-wiring substrate 12 faces the back surface 11b of the first die 11;
a molding layer 13 for covering the first die 11 and the pre-wiring substrate 12, wherein the back surface 13b of the molding layer 13 exposes the front surface 12a of the pre-wiring substrate 12, and the front surface 13a of the molding layer 13 exposes the active surface 11a of the first die 11;
a plurality of conductive plugs 14 located in the molding compound layer 13 and at a side of the first die 11, wherein the conductive plugs 14 include a first end 14a and a second end 14b opposite to each other, the first end 14a is connected to the back electrical connection point 122, and the second end 14b is exposed at the front surface 13a of the molding compound layer 13;
first conductive traces 15 on the first pads 111, the second ends 14b of the conductive plugs 14, and the front surface 13a of the molding layer 13 for electrically connecting the first dies 11 and the pre-wiring lines 120;
a first conductive bump 16 connected to the first conductive trace 15;
a first dielectric layer 17 embedding the first conductive trace 15 and the first conductive bump 16, the first conductive bump 16 being exposed outside the first dielectric layer 17; and
and a passive component 18 electrically connected to the front surface electrical connection point 121 of the pre-wiring substrate 12.
The first DIE 11 may be a POWER DIE (POWER DIE), a MEMORY DIE (MEMORY DIE), a sensing DIE (SENSOR DIE), a RADIO frequency DIE (RADIO frequency DIE), or the like.
Referring to fig. 1, the first die 11 includes an active surface 11a and a back surface 11b opposite to each other. The first pad 111 is exposed to the active surface 11a. The first die 11 may contain a variety of devices formed on a semiconductor substrate, as well as electrical interconnect structures electrically connecting the various devices. The first pads 111 are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices.
In the present invention, "/" denotes "or".
In this embodiment, the active surface 11a of the first die 11 is provided with a first protective layer 110. In other embodiments, the active surface 11a of the first die 11 may omit the first protection layer 110.
The first protection layer 110 is an insulating material, which may be an organic high molecular polymer insulating material, an inorganic insulating material, or a composite material. The organic high molecular polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto build film), PBO (Polybenzoxazole), an organic polymer film, or other organic materials having similar insulating properties. The inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride. The composite material is inorganic-organic composite material, and can be inorganic-organic polymer composite material, such as SiO 2 Resin polymer composite material.
The pre-wiring substrate 12 includes pre-wiring lines 120 and an insulating material layer filled between the pre-wiring lines 120. The pre-wiring substrate 12 may include opposing front and back surfaces 12a and 12b, with the front electrical connection points 121 exposed at the front surface 12a of the pre-wiring substrate 12 and the back electrical connection points 122 exposed at the back surface 12b of the pre-wiring substrate 12. There may be a plurality of front surface electrical connection points 121 exposed to the front surface 12a of the pre-wiring substrate, and a plurality of rear surface electrical connection points 122 exposed to the rear surface 12b of the pre-wiring substrate.
Referring to fig. 1, in the present embodiment, the first bare chip 11 and the pre-wiring substrate 12 are disposed back-to-back, and may be fixed by an adhesive layer therebetween. The area of the first die 11 is smaller than that of the pre-wiring substrate 12 to expose the back side electrical connection points 122.
The material of the molding layer 13 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. The material of the molding layer 13 may also be various polymers or a composite material of resin and polymer.
The molding layer 13 includes a front surface 13a and a back surface 13b opposite to each other. In this embodiment, the front surface 13a of the molding layer 13 exposes the first protection layer 110 and the first pad 111, and the back surface 13b of the molding layer 13 exposes the back surface 12b of the pre-wiring substrate 12.
The material of the conductive plug 14 may be a metal having excellent conductivity, such as copper.
The number and location of the conductive plugs 14 may be determined according to a predetermined circuit layout.
In the embodiment shown in fig. 1, the first conductive trace 15 comprises a plurality of metal pattern blocks 15a, having one layer. A partial number of the metal pattern blocks 15a selectively electrically connect the second ends 14b of the conductive plugs 14 with the first pads 111 to electrically connect the conductive plugs 14 with the first die 11. In addition, there may be a partial number of metal pattern blocks 15a selectively electrically connected to the plurality of first pads 111 to realize circuit layout or electrical conduction of the first pads 111.
The layout of the first conductive traces 15 may be determined according to a preset circuit layout.
Referring to fig. 1, in the present embodiment, the first conductive bump 16 on the first conductive trace 15 serves as an external connection terminal of the semiconductor package structure 1.
In other embodiments, the first conductive bump 16 may further have an oxidation resistant layer thereon.
The oxidation resistant layer may include: b1 A tin layer, or b 2) a nickel layer and a gold layer stacked from bottom to top, or b 3) a nickel layer, a palladium layer and a gold layer stacked from bottom to top. The material of the first conductive bump 16 may be copper, and the anti-oxidation layer can prevent oxidation of copper, thereby preventing the electrical connection performance from being deteriorated due to the oxidation of copper.
The material of the first dielectric layer 17 may be an organic high molecular polymer insulating material or an inorganic insulating material or a composite material. The organic high molecular polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto build film), PBO (Polybenzoxazole), an organic polymer film, or other organic materials having similar insulating properties. The inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride. The composite material is an inorganic-organic composite material, and can be an inorganic-organic polymer composite material, such as SiO 2 A resin polymer composite. Compared with an inorganic insulating material, the organic high-molecular polymer insulating material and the composite material have smaller tensile stress, and the surface of the semiconductor packaging structure 1 can be prevented from warping.
Compared with the scheme of manufacturing the rewiring layer on the plastic package body of the first bare chip 11, the scheme has the advantages that the pre-wiring substrate 12 is adopted: first, the fine wiring in the rewiring layer is transferred to the pre-wiring substrate 12, so that the probability of short circuit is reduced, the product yield is increased, the number of layers of conductive traces can be reduced, and the process complexity is reduced. Second, providing a pre-formed pre-wiring substrate 12 allows testing of the pre-wiring substrate 12 prior to packaging, avoiding the use of known poor pre-wiring substrates 12. Thirdly, the pre-wiring substrate 12 is a pre-fabricated substrate, and the manufacturing process is independent of the packaging process, so that the packaging time of the whole packaging process can be saved.
Furthermore, transferring the wiring layer that needs to be formed on the die active surface 11a into the pre-wiring substrate 12, the pre-wiring substrate 12 including complex multiple circuits embedded in the package structure 1 by electrically connecting the conductive plugs 14 with the first conductive traces 15 and the pads 111 on the die active surface 11a, can improve the performance of the entire package structure 1. By means of the pre-wiring substrate 12, not only passive components 18 are incorporated into the semiconductor package 1, enriching the functionality of the semiconductor package 1, but also a complex wiring between the passive components 18 and the first die 11 is achieved, since the pre-wiring substrate 12 comprises complex multiple circuits.
The number and types of the first dies 11 and the passive devices 18 are not limited in this embodiment.
An embodiment of the invention provides a method for manufacturing the semiconductor package 1 shown in fig. 1. Fig. 2 is a flow chart of a method of fabrication. Fig. 3 to 11 are intermediate schematic diagrams corresponding to the flow chart in fig. 2.
First, referring to step S1, fig. 3 and fig. 4 in fig. 2, a plurality of sets of to-be-molded parts 2 are provided, where each set of to-be-molded parts 2 includes: a first die 11, the first die 11 including a plurality of first bonding pads 111, the first bonding pads 111 being located on an active surface 11a of the first die 11; a pre-wiring substrate 12, wherein a pre-wiring line 120 is arranged in the pre-wiring substrate 12, the pre-wiring line 120 comprises a front surface electrical connection point 121 and a back surface electrical connection point 122, the front surface electrical connection point 121 is exposed on the front surface 12a of the pre-wiring substrate 12, and the back surface electrical connection point 122 is exposed on the back surface 12b of the pre-wiring substrate 12; the back surface 12b of the pre-wiring substrate 12 faces the back surface 11b of the first die 11. Wherein, fig. 3 is a top view of the carrier plate and a plurality of groups of members to be molded; fig. 4 is a sectional view taken along the AA line in fig. 3.
Specifically, the method comprises the following steps: referring to fig. 3 and 4, a carrier 3 and a plurality of sets of to-be-molded parts 2 carried on the carrier 3 are provided, where each set of to-be-molded parts 2 includes: a first die 11, the first die 11 including a plurality of first bonding pads 111, the first bonding pads 111 being located on an active surface 11a of the first die 11; a pre-wiring substrate 12, a pre-wiring line 120 is arranged in the pre-wiring substrate 12, the pre-wiring line 120 comprises a front surface electrical connection point 121 and a back surface electrical connection point 122, the front surface electrical connection point 121 is exposed on the front surface 12a of the pre-wiring substrate 12, and the back surface electrical connection point 122 is exposed on the back surface 12b of the pre-wiring substrate 12; the back surface 12b of the pre-wiring substrate 12 faces the back surface 11b of the first die 11; the active face 11a of each first die 11 faces the carrier plate 3.
The first DIE 11 may be a POWER DIE (POWER DIE), a MEMORY DIE (MEMORY DIE), a SENSOR DIE (SENSOR DIE), a RADIO frequency DIE (RADIO frequency DIE), or the like.
Referring to fig. 4, the first die 11 includes an active surface 11a and a back surface 11b opposite to each other. The first die 11 may include a variety of devices formed on a semiconductor substrate, and electrical interconnect structures electrically connected to the various devices. The first pads 111 exposed to the active surface 11a of the first die 11 are connected to an electrical interconnect structure for inputting/outputting electrical signals of the respective devices.
In this embodiment, the active surface 11a of the first die 11 is provided with a first protection layer 110 to perform stress buffering on the first pad 111 when the molding layer 13 is thinned. In other embodiments, the active surface 11a of the first die 11 may omit the first protection layer 110.
The first die 11 is formed for dicing a wafer. The wafer includes a wafer active side and a wafer backside, the wafer active side exposing the first pads 111 and an insulating layer (not shown) protecting the first pads 111. The wafer is diced to form a first die 11, and accordingly, the first die 11 includes an active surface 11a and a back surface 11b, and the first bonding pad 111 and an insulating layer electrically insulating the adjacent first bonding pad 111 are exposed on the die active surface 11a.
Applying the first protective layer 110 on the active surface 11a of the first die 11, the applying process of the first protective layer 110 may be: before the wafer is cut into the first dies 11, the first protection layer 110 is applied on the active surface of the wafer, and the wafer with the first protection layer 110 is cut to form the first dies 11 with the first protection layer 110, which may also be: after the wafer is diced into the first dies 11, the first protection layer 110 is applied on the active surface 11a of the first dies 11.
The first protection layer 110 is an insulating material, which may be an organic high molecular polymer insulating material, an inorganic insulating material, or a composite material. The organic high molecular polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto build film), PBO (Polybenzoxazole), an organic polymer film, or other organic materials having similar insulating properties. The composite material is inorganic-organic composite material, and can be inorganic-organic polymer composite material, such as SiO 2 A resin polymer composite.
The organic high molecular polymer insulating material may be a) laminated on the first pad 111 and the insulating layer between the adjacent first pads 111 through a lamination process, or b) coated or printed on the first pad 111 and the insulating layer between the adjacent first pads 111 and then cured, or c) cured on the first pad 111 and the insulating layer between the adjacent first pads 111 through an injection molding process.
When the material of the first protection layer 110 is an inorganic material such as silicon dioxide or silicon nitride, the first protection layer may be formed on the first pad 111 and the insulating layer between adjacent first pads 111 by a deposition process.
The first protective layer 110 may include one or more layers.
In this embodiment, referring to fig. 4, a first opening 110a exposing the first pad 111 is further formed in the first protection layer 110. The first opening 110a may be implemented by dry etching or wet etching.
The wafer may be thinned from the back side before dicing to reduce the thickness of the first die 11.
The pre-wiring substrate 12 includes pre-wiring lines 120 and an insulating material layer filled between the pre-wiring lines 120. The pre-wiring substrate 12 may include opposing front and back surfaces 12a and 12b, with the front electrical connection points 121 exposed at the front surface 12a of the pre-wiring substrate 12 and the back electrical connection points 122 exposed at the back surface 12b of the pre-wiring substrate 12. There may be a plurality of front surface electrical connection points 121 exposed to the front surface 12a of the pre-wiring substrate, and a plurality of rear surface electrical connection points 122 exposed to the rear surface 12b of the pre-wiring substrate.
The pre-wiring substrates 12 of the sets of parts to be molded 2 may be connected together or may be separated from each other.
Referring to fig. 4, in the present embodiment, the first die 11 and the pre-wiring substrate 12 are disposed back to back, and may be fixed by an adhesive layer therebetween. The area of the first die 11 is smaller than that of the pre-wiring substrate 12 to expose the back side electrical connection points 122.
The carrier plate 3 is a rigid plate and may comprise a plastic plate, a glass plate, a ceramic plate, a metal plate, or the like.
When the multiple sets of to-be-molded parts 2 are arranged on the surface of the carrier plate 3, the method may include:
a) The first protection layer 110 faces the carrier 3, and the plurality of first dies 11 are arranged on the carrier 3. Specifically, the surface of the carrier 3 is provided with a plurality of mounting areas, each mounting area is provided with an alignment mark, and the first opening 110a can be used as an alignment pattern feature to arrange the first dies 11 on the carrier 3 according to a predetermined arrangement position. The surface of the carrier 3 may be coated with a full-surface adhesive layer to fix the plurality of first dies 11;
the adhesive layer may be a material that is easily peelable to peel the plurality of first dies 11 from the carrier 3, such as a thermal release material that can be tack-free by heating or a UV release material that can be tack-free by UV irradiation;
b) Next, each pre-wiring substrate 12 is applied to the back surface 11b of the corresponding first die 11. The back side 11b of the first die 11 may have alignment marks to achieve alignment of the pre-wiring substrate 12 with the first die 11 during application.
A group of parts to be molded 2 are positioned in an area of the surface of the carrier plate 3, so that subsequent cutting is facilitated. The surface of the carrier plate 3 is fixed with a plurality of groups of pieces to be molded 2 so as to manufacture a plurality of semiconductor packaging structures 1 at the same time, thereby being beneficial to batch production and cost reduction.
Next, referring to step S2 in fig. 2 and fig. 5 to 7, a molding layer 13 is formed, the molding layer 13 covers a plurality of sets of pieces to be molded 2, a back surface 13b of the molding layer 13 exposes a front surface 12a of each pre-wiring substrate 12, and a front surface 13a of the molding layer 13 exposes an active surface 11a of each first bare chip 11.
In this embodiment, step S2 specifically includes steps S21 to S22.
Step S21: referring to fig. 5, a plastic package layer 13 for embedding each group of pieces to be plastic-packaged 2 is formed on the surface of the carrier plate 3; referring to fig. 6, the molding layer 13 is thinned until the front surface 12a of each of the pre-wiring substrates 12 is exposed.
The material of the molding layer 13 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. The material of the molding layer 13 may also be various polymers or a composite material of resin and polymer. Correspondingly, the packaging may be performed by filling a liquid molding compound between each first bare chip 11 and the stacked structure of the pre-wiring substrate 12, and then curing the liquid molding compound at a high temperature by using a molding die. In some embodiments, the molding layer 13 may also be formed by plastic material molding such as hot press molding and transfer molding.
The molding layer 13 may include a front surface 13a and a back surface 13b opposite to each other.
Referring to fig. 6, the plastic sealing layer 13 is thinned from the back surface 13b by mechanical grinding, for example, grinding using a grinding wheel, to expose the back surface 12b of the pre-wiring substrate 12.
The first protection layer 110 may buffer the stress of the first pad 111 during the formation of the molding layer 13 and the polishing of the molding layer 13.
Step S22: referring to fig. 7, the carrier board 3 is removed to expose the first protective layer 110, the first pad 111 and the front surface 13a of the molding layer 13.
The removal method of the carrier 3 may be laser lift-off, UV irradiation, or other conventional removal methods.
After removing the carrier plate 3, the first support plate 4 may be disposed on the front surface 12a of the pre-wiring substrate 12 and the back surface 13b of the molding layer 13. The first support plate 4 is a hard plate member and may include a glass plate, a ceramic plate, a metal plate, and the like. The first support plate 4 may be used for supporting in the subsequent steps of forming the first conductive traces 15, and/or forming the first conductive bumps 16, and/or forming the first dielectric layer 17.
In other embodiments, steps S1', S21' to S22' may also be included.
Step S1' is substantially the same as step S1, except that: in each set of the to-be-molded articles 2, the front surface 12a of each pre-wiring substrate 12 faces the carrier 3.
Step S21' is substantially the same as step S21, except that: the molding layer 13 is thinned until the active surface 11a of each first die 11 is exposed. When the active surface 11a has the first protective layer 110, the first protective layer 110 is exposed. The first protective layer 110 protects the first pad 111 when thinning the molding layer 13.
Step S22' is substantially the same as step S22, except that: after removing the carrier board 3, the front surface 12a of each pre-wiring substrate 12 and the back surface 13b of the molding layer 13 are exposed.
Next, referring to step S3, fig. 8 and fig. 9 in fig. 2, forming a plurality of conductive plugs 14 in the molding layer 13, where the conductive plugs 14 are located at the side of the first die 11, the conductive plugs 14 include a first end 14a and a second end 14b opposite to each other, the first end 14a is connected to the back electrical connection point 122, and the second end 14b is exposed on the front surface 13a of the molding layer 13; first conductive traces 15 are formed on the first pads 111, the second ends 14b of the conductive plugs 14, and the front surface 13a of the molding layer 13 to electrically connect the first dies 11 in the group with the pre-wiring lines 120.
In this embodiment, referring to fig. 8, a plurality of through holes 141 may be formed in the molding compound layer 13, and the bottom of the through holes 141 exposes the back electrical connection points 122.
The via 141 may be formed by dry etching, wet etching, or laser opening.
In other embodiments, in the first die 11, if the first bonding pad 111 is covered with the first protection layer 110, before the first conductive trace 15 is formed, the first opening 110a is formed in the first protection layer 110 to expose the first bonding pad 111.
The first protective layer 110 is made of a laser-reactive material, such as epoxy resin, and the first opening 110a can be formed by laser irradiation to be modified. The first opening 110a can be formed by exposing and then developing the first protection layer 110, which is made of a photosensitive material, such as polyimide. For the material of the first protection layer 110 being a dry-etchable or wet-etchable material, such as silicon dioxide, silicon nitride, etc., the first opening 110a may be formed by dry-etchable or wet-etchable.
In the present embodiment, forming the first conductive trace 15 includes the following steps S311 to S314.
Step S311: a photoresist layer is formed on the first protective layer 110 of each first die 11, the first pad 111 exposed by the first protective layer 110, the front surface 13a of the molding layer 13, and each through hole 141.
In this step S311, in an alternative, the formed photoresist layer may be a photosensitive film. The photosensitive film may be peeled off from the adhesive tape and applied on the first protective layer 110 of each first die 11, each first pad 111, the front surface 13a of the molding layer 13, and the opening of each through hole 141. In other alternatives, the photoresist layer may be formed by first applying a liquid photoresist and then curing the liquid photoresist by heating.
Step S312: the photoresist layer is exposed and developed, leaving a first predetermined area of the photoresist layer that is complementary to the area where the metal pattern piece 15a of the first conductive trace 15 is to be formed.
Step S313: the complementary area of the first predetermined area is filled with a metal layer to form the conductive plug 14 and the metal pattern block 15a of the first conductive trace 15.
In other embodiments, the first conductive trace 15 may be formed after the conductive plug 14 is formed by filling a metal layer in the via 141.
A partial number of the metal pattern blocks 15a selectively electrically connect the second ends 14b of the conductive plugs 14 with the first pads 111 to achieve electrical connection of the pre-wiring lines 120 with the first die 11. In addition, there may be a partial number of metal pattern blocks 15a selectively electrically connected to the plurality of first pads 111 to realize circuit layout or electrical conduction of the first pads 111.
The step S313 may be performed by an electroplating process. The process of electroplating copper or aluminum is relatively mature.
Specifically, before forming the photoresist Layer in step S311, a Seed Layer (Seed Layer) may be formed on the first protection Layer 110 of each first die 11, the first bonding pad 111 exposed by the first protection Layer 110, the front surface 13a of the molding Layer 13, and each through hole 141 by using a physical vapor deposition method or a chemical vapor deposition method. The seed layer may serve as a power supply layer for electroplating copper or aluminum.
The plating may include electrolytic plating or electroless plating. In the electrolytic plating, a piece to be plated is used as a cathode, and an electrolyte is electrolyzed, so that a layer of metal is formed on the piece to be plated. Electroless plating is a method of forming a metal layer by reducing and precipitating metal ions in a solution on an article to be plated. In some embodiments, the conductive plug 14 and the metal pattern block 15a may be formed by a sputtering-first method and an etching-second method.
Step S314: and ashing to remove the residual photoresist layer in the first preset area.
And after ashing, removing the seed crystal layer in the first preset area by dry etching or wet etching.
The metal pattern block 15a of the first conductive trace 15 may be planarized at its upper surface by a polishing process, such as a chemical mechanical polishing method.
It should be noted that, the metal pattern blocks 15a of the first conductive traces 15 in the step S3 are arranged according to design requirements, and the distribution of the first conductive traces 15 on different groups of the to-be-molded parts 2 may be the same or different.
Thereafter, referring to step S4 and fig. 9 in fig. 2, a first conductive bump 16 is formed on the first conductive trace 15 and a first dielectric layer 17 is formed to embed the first conductive trace 15 and the first conductive bump 16, wherein the first conductive bump 16 is exposed outside the first dielectric layer 17.
Forming the first conductive bump 16 and the first dielectric layer 17 may include steps S411 to S415.
Step S411: a photoresist layer is formed on the metal pattern block 15a, the first protective layer 110 exposed by the metal pattern block 15a, and the front surface 13a of the molding layer 13.
In this step S411, in an alternative embodiment, the formed photoresist layer may be a photosensitive film. The photosensitive film may be peeled off from the adhesive tape and applied on the metal pattern block 15a, the first protective layer 110 exposed by the metal pattern block 15a, and the front surface 13a of the molding layer 13. In other alternatives, the photoresist layer may be formed by first coating a liquid photoresist and then curing the liquid photoresist by heating.
Step S412: and exposing and developing the photoresist layer, and reserving the photoresist in the second preset area. The second predetermined area is complementary to the area where the first conductive bump 16 is to be formed.
This step S412 patterns the photoresist layer. In other alternatives, other sacrificial materials that are easily removable may be used in place of the photoresist layer.
Step S413: the complementary region of the second predetermined region is filled with a metal layer to form the first conductive bump 16.
This step S413 may be performed by an electroplating process. The process of electroplating copper or aluminum is mature. Before electroplating copper or aluminum, a Seed Layer (Seed Layer) can be physically or chemically vapor deposited as a power supply Layer.
Step S414: and ashing to remove the residual photoresist layer in the second preset area.
The first conductive bump 16 may be planarized by a polishing process, such as chemical mechanical polishing.
Step S415: referring to fig. 9, a first dielectric layer 17 is formed on the first conductive bump 16, the metal pattern block 15a, the first protective layer 110 exposed by the metal pattern block 15a, and the front surface 13a of the molding layer 13; the first dielectric layer 17 is thinned until the first conductive bump 16 is exposed.
The first dielectric layer 17 is an insulating material, which may be an organic high molecular polymer insulating material, an inorganic insulating material, or a composite material. The organic high molecular polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto build film), PBO (Polybenzoxazole), an organic polymer film, or other organic materials having similar insulating properties. The composite material is inorganic-organic composite material, and can be inorganic-organic polymer composite material, such as SiO 2 Resin polymer composite material.
The organic polymer insulating material may be a) laminated on the first conductive trace 15, the first conductive bump 16, the first protective layer 110 not covering the first conductive trace 15, and the front surface 13a of the plastic package layer 13 by a laminating process, or b) coated on the first conductive trace 15, the first conductive bump 16, the first protective layer 110 not covering the first conductive trace 15, and the front surface 13a of the plastic package layer 13, and then cured, or c) cured on the first conductive trace 15, the first conductive bump 16, the first protective layer 110 not covering the first conductive trace 15, and the front surface 13a of the plastic package layer 13 by an injection molding process.
When the material of the first dielectric layer 17 is an inorganic insulating material such as silicon dioxide or silicon nitride, the first conductive trace 15, the first conductive bump 16, the first protective layer 110 not covering the first conductive trace 15, and the front surface 13a of the molding layer 13 can be formed by a deposition process.
Compared with inorganic insulating materials, the organic high molecular polymer insulating materials and the composite materials have smaller tensile stress, and can prevent the plastic package body from warping when the first dielectric layer 17 is formed in a large area.
The first dielectric layer 17 may include one or more layers.
When the first dielectric layer 17 covers the first conductive bump 16, the first dielectric layer 17 is polished until the first conductive bump 16 is exposed.
After exposing the first conductive bump 16, a) in the alternative, as shown with reference to fig. 9, the first conductive bump 16 serves as an external connection terminal of the semiconductor package 1.
b) In an alternative, after exposing the first conductive bump 16, an anti-oxidation layer is also formed on the first conductive bump 16.
The oxidation resistant layer may include: b1 A tin layer, or b 2) a nickel layer and a gold layer stacked from bottom to top, or b 3) a nickel layer, a palladium layer and a gold layer stacked from bottom to top. The oxidation resistant layer may be formed using an electroplating process. The material of the first conductive bump 16 may be copper, and the anti-oxidation layer can prevent oxidation of copper, thereby preventing deterioration of electrical connection performance due to oxidation of copper.
After the first conductive bumps 16 are exposed, as shown in fig. 10, the first support plate 4 is removed.
The first support plate 4 may be removed by conventional methods such as laser lift-off and UV irradiation.
After removing the first support plate 4, a second support plate 5 may be disposed on the first conductive bumps 16 and the first dielectric layer 17.
The second support plate 5 is a rigid plate and may comprise a glass plate, a ceramic plate, a metal plate, or the like. The second support plate 5 may serve as a support in a subsequent process of disposing the passive component 18.
Next, referring to step S5 in fig. 2 and fig. 10, each passive component 18 is electrically connected to the front surface electrical connection point 121 of the corresponding pre-wiring substrate 12.
In some embodiments, the thinning of the molding layer 13 until the front surface 12a of the pre-wiring substrate 12 is exposed may be performed after the end of step S4 and before the start of step S5.
After the passive components 18 are arranged, the second support plate 5 is removed, as shown in fig. 11.
The second support plate 5 may be removed by conventional methods such as laser lift-off and UV irradiation.
Then, referring to step S6 in fig. 2, fig. 11 and fig. 1, a plurality of semiconductor packages 1 are formed by cutting, and each semiconductor package 1 includes a group of to-be-molded parts 2.
For the embodiment in which the pre-wiring substrates 12 of the respective sets of the members to be molded 2 are joined together, the pre-wiring substrates 12 are cut apart during the cutting process of this step S6.
In the semiconductor package 1 formed through the above steps, the use of the pre-wiring substrate 12 is advantageous in that: firstly, the fine wiring in the rewiring layer is transferred to the pre-wiring substrate 12, so that the probability of short circuit is reduced, the product yield is increased, the number of layers of the first conductive traces 15 can be reduced, and the process complexity is reduced. Second, providing a pre-formed pre-wiring substrate 12 allows testing of the pre-wiring substrate 21 prior to packaging, avoiding the use of known poor pre-wiring substrates 12. Thirdly, the pre-wiring substrate 12 is a pre-fabricated substrate, and the manufacturing process is independent of the packaging process, so that the packaging time of the whole packaging process can be saved.
Furthermore, transferring the wiring layer that needs to be formed on the die active surface 11a into the pre-wiring substrate 12, the pre-wiring substrate 12 includes complex multiple circuits embedded in the package structure 1 by being electrically connected to the pads 111 on the die active surface 11a, and the performance of the entire package structure 1 can be improved. By pre-wiring substrate 12, passive devices 18 are also incorporated into semiconductor package 1, enriching the functionality of semiconductor package 1.
Fig. 12 is a schematic cross-sectional view of a semiconductor package structure according to a second embodiment of the invention. Referring to fig. 12, the semiconductor package 6 of the present embodiment is substantially the same as the semiconductor package 1 of the previous embodiment except that: further comprising:
a second conductive trace 19 on the first conductive bump 16 and the first dielectric layer 17;
a second conductive bump 20 connected to the second conductive trace 19;
and a second dielectric layer 21 embedding the second conductive trace 19 and the second conductive bump 20, wherein the second conductive bump 20 is exposed out of the second dielectric layer 21.
In other words, in the present embodiment, the second conductive bump 20 on the second conductive trace 19 serves as an external connection terminal of the semiconductor package structure 6.
In the embodiment shown in fig. 12, the second conductive trace 19 comprises several metal pattern blocks 19a, having one layer. The second conductive trace 19 enables a second circuit layout of the first conductive trace 15 and the first conductive bump 16.
Accordingly, as for the manufacturing method, the difference from the foregoing embodiment is that: after step S4 and before step S5, the following steps are further performed:
forming a second conductive trace 19 on the first conductive bump 16 and the first dielectric layer 17;
a second conductive bump 20 is formed on the second conductive trace 19 and a second dielectric layer 21 is formed to embed the second conductive trace 19 and the second conductive bump 20, and the second conductive bump 20 is exposed out of the second dielectric layer 21.
The material and formation process of the second conductive trace 19 may refer to those of the first conductive trace 15.
The material and formation process of the second conductive bump 20 may refer to the material and formation process of the first conductive bump 16.
The material and formation process of the second dielectric layer 21 may refer to the material and formation process of the first dielectric layer 17.
In other embodiments, there may be one or more layers of conductive trace layout between the second conductive trace 19 and the first conductive bump 16.
Fig. 13 is a schematic cross-sectional view of a semiconductor package structure according to a third embodiment of the invention. Referring to fig. 13, a semiconductor package 7 of the present embodiment is substantially the same as the semiconductor packages 1 and 6 of the previous embodiments except that: omitting the first protective layer 110, the active surface 11a of the first die 11, the second end 14b of the conductive plug 14 and the front surface 13a of the molding layer 13 are provided with a third dielectric layer 22; the third dielectric layer 22 has a third opening 22a exposing the first pad 111 and the second end 14b of the conductive plug 14; the first conductive trace 15 is located on the first pad 111, the second end 14b of the conductive plug 14, and the third dielectric layer 22.
Accordingly, as for the manufacturing method, the difference from the foregoing embodiment is that: in step S3, before forming the first conductive traces 15, a third dielectric layer 22 is formed on the exposed active surface 11a of the first die 11, the second end 14b of the conductive plug 14, and the front surface 13a of the molding layer 13; forming a plurality of third openings 22a in the third dielectric layer 22, the third openings 22a exposing the first pads 111 and the second ends 14b of the conductive plugs 14; the first conductive trace 15 is then formed on the first pad 111, the second end 14b of the conductive plug 14, and the third dielectric layer 22.
The material of the third dielectric layer 22 is referenced to the material of the first dielectric layer 17.
The material of the third dielectric layer 22 is a laser-reactive material such as epoxy resin, and the third opening 22a can be formed by laser irradiation to be modified. The third opening 22a can be formed by exposing and then developing the third dielectric layer 22, which is made of a photosensitive material, such as polyimide. As for the material of the third dielectric layer 22, which is a dry-etchable or wet-etchable material, such as silicon dioxide, silicon nitride, etc., the third opening 22a may be formed by dry-etchable or wet-etchable.
Fig. 14 is a schematic cross-sectional view of a semiconductor package structure according to a fourth embodiment of the invention. Referring to fig. 14, the semiconductor package 8 of the present embodiment is substantially the same as the semiconductor packages 1 and 6 of the previous embodiments, except that: further comprising: a second die 23, the second die 23 including a plurality of second bonding pads 231, the second bonding pads 231 being located on an active surface 23a of the second die 23; the active surface 23a of the second die 23 is covered with a second protective layer 230, the second protective layer 230 exposing the second pad 231; the back surface 23b of the second die 23 faces the back surface 12b of the pre-wiring substrate 12; the plastic package layer 13 also covers the second bare chip 23; the conductive patch 14 is also located on the side of the second die 23; the first conductive traces 15 are also located on the second bonding pads 231 for electrically connecting the first die 11, the second die 23, and the pre-wiring lines 120.
The second die 23 includes an active side 23a and a back side 23b that are opposite. The second pad 231 is exposed to the active surface 23a. The second die 23 may include a variety of devices formed on a semiconductor substrate, as well as electrical interconnect structures electrically connecting the various devices. The second pads 231 are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices.
The material of the second protective layer 230 and the method of forming the same may refer to the material of the first protective layer 110 and the method of forming the same.
Accordingly, as for the manufacturing method of the semiconductor package structure 8, the difference from the foregoing embodiment is that: in step S1, each group of to-be-molded parts 2 further includes: the second die 23, and the active surface 23a of the second die 23 also face the carrier 3.
For the method of forming the molding compound layer 13 in step S2, the thicknesses of the first die 11 and the second die 23 need to be the same. The same thickness of the first die 11 and the second die 23 can be achieved by controlling the thickness of the first protective layer 110 and the second protective layer 230.
As for the method of forming the molding compound layer 13 in step S2', the same thickness of the first die 11 and the second die 23 can be achieved in the process of thinning the molding compound layer 13.
Before the plastic molding, a second opening 230a exposing the second pad 231 may be formed in the second protection layer 230. Or before molding, the second protection layer 230 may also cover the second pad 231, and the second opening 230a is formed before forming the first conductive trace 15.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. A semiconductor package structure, comprising:
a first die comprising a number of first bonding pads, the first bonding pads located on an active side of the first die;
the pre-wiring substrate is internally provided with a pre-wiring circuit, the pre-wiring circuit comprises a front surface electric connection point and a back surface electric connection point, the front surface electric connection point is exposed on the front surface of the pre-wiring substrate, and the back surface electric connection point is exposed on the back surface of the pre-wiring substrate; the back surface of the pre-wiring substrate faces the back surface of the first die;
the plastic package layer covers the first bare chip and the pre-wiring substrate, the back surface of the plastic package layer exposes the front surface of the pre-wiring substrate, and the front surface of the plastic package layer exposes the active surface of the first bare chip;
the conductive plugs are positioned in the plastic package layer and positioned on the side edge of the first bare chip, each conductive plug comprises a first end and a second end which are opposite, the first ends are connected to the back surface electric connection points, and the second ends are exposed to the front surface of the plastic package layer;
a first conductive trace on the first pad, the second end of the conductive plug, and the front side of the molding layer for electrically connecting the first die with the pre-routing line;
a first conductive bump connected to the first conductive trace;
a first dielectric layer embedding the first conductive trace and the first conductive bump, the first conductive bump being exposed outside the first dielectric layer; and
and the passive device is electrically connected to the front side electric connection point of the pre-wiring substrate.
2. The semiconductor package structure of claim 1, wherein an active side of the first die is covered with a first protective layer, the first protective layer exposing the first bonding pad; the front surface of the plastic packaging layer exposes the first protective layer and the first bonding pad; the first conductive trace is also on the first protective layer.
3. The semiconductor package structure of claim 2, further comprising: a second die comprising a number of second bonding pads, the second bonding pads located on an active side of the second die; the active surface of the second bare chip is covered with a second protective layer, and the second protective layer exposes the second bonding pad; the back surface of the second bare chip faces the back surface of the pre-wiring substrate; the plastic packaging layer also wraps the second bare chip; the conductive patch is also located on a side of the second die; the first conductive trace is also on the second pad for electrically connecting the first die, the second die, and the pre-routing line.
4. The semiconductor package structure of claim 1, further comprising: a third dielectric layer on the active surface of the first die, the second end of the conductive plug, and the front surface of the molding layer; the third dielectric layer exposes the first pad and a second end of the conductive plug; the first conductive trace is on the first pad, the second end of the conductive plug, and the third dielectric layer.
5. The semiconductor package structure of claim 1, further comprising: a second conductive trace on the first conductive bump and the first dielectric layer;
a second conductive bump connected to the second conductive trace;
a second dielectric layer embedding the second conductive trace and the second conductive bump, the second conductive bump being exposed outside the second dielectric layer.
6. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
provide the multiunit and treat the plastic-sealed piece, every group treat the plastic-sealed piece and include: a first die comprising a number of first bonding pads, the first bonding pads located on an active side of the first die; the pre-wiring substrate is internally provided with a pre-wiring circuit, the pre-wiring circuit comprises a front surface electric connection point and a back surface electric connection point, the front surface electric connection point is exposed on the front surface of the pre-wiring substrate, and the back surface electric connection point is exposed on the back surface of the pre-wiring substrate; the back surface of the pre-wiring substrate faces the back surface of the first bare chip;
forming a plastic packaging layer, wherein the plastic packaging layer coats the multiple groups of pieces to be molded, the back surface of the plastic packaging layer exposes the front surface of each pre-wiring substrate, and the front surface of the plastic packaging layer exposes the active surface of each first bare chip;
forming a plurality of conductive plugs in the molding layer, wherein the conductive plugs are located on the side of the first bare chip and comprise a first end and a second end which are opposite, the first end is connected to the back side electric connection point, and the second end is exposed on the front side of the molding layer; forming first conductive traces on the first pads, second ends of the conductive plugs, and a front side of the molding layer to electrically connect the first dies within a group with the pre-routing lines;
forming a first conductive bump on the first conductive trace and a first dielectric layer embedding the first conductive trace and the first conductive bump, the first conductive bump being exposed outside the first dielectric layer;
electrically connecting each passive device to the corresponding front surface electrical connection point of the pre-wiring substrate;
and cutting to form a plurality of semiconductor packaging structures, wherein each semiconductor packaging structure comprises a group of to-be-molded parts.
7. The method of claim 6, wherein the plurality of sets of to-be-molded components are carried on a carrier, and an active surface of each of the first dies faces the carrier;
the forming of the plastic package layer comprises:
forming a plastic package layer for embedding each group of the parts to be plastic-packaged on the surface of the carrier plate;
removing the carrier plate to expose the active surface of each first bare chip and the front surface of the plastic packaging layer; and thinning the plastic packaging layer until the front surface of each pre-wiring substrate is exposed before removing the carrier plate or after forming the first dielectric layer.
8. The method of manufacturing a semiconductor package structure according to claim 7, wherein an active surface of the first die is covered with a first protection layer, the first protection layer having a first opening exposing the first pad; the first openings serve as alignment pattern features to arrange the first bare chips on the carrier board according to a preset arrangement position.
9. The method of claim 7, wherein the back side of the first die has alignment marks to apply the pre-wiring substrate to the back side of the first die.
10. The method of claim 6, wherein the plurality of sets of to-be-molded components are carried on a carrier, and a front surface of each of the pre-wiring substrates faces the carrier;
the forming of the plastic package layer comprises:
forming a plastic package layer for embedding each group of the parts to be plastic-packaged on the surface of the carrier plate; thinning the plastic packaging layer until the active surface of each first bare chip is exposed;
and removing the carrier plate, and exposing the front surface of each pre-wiring substrate and the back surface of the plastic packaging layer.
11. The method of manufacturing a semiconductor package structure of claim 10, wherein an active surface of the first die is covered with a first protective layer; thinning the plastic packaging layer until the first protective layer is exposed; forming a first opening in the first protective layer exposing the first pad before forming the first conductive trace; or
An active side of the first die is covered with a first protective layer having a first opening exposing the first pad; and thinning the plastic packaging layer until the first protective layer and the first bonding pad are exposed.
12. The method for manufacturing a semiconductor package structure according to claim 11, wherein each group of the members to be molded further comprises: a second die comprising a number of second bonding pads, the second bonding pads located on an active side of the second die; the active surface of the second bare chip is covered with a second protective layer; the back side of the second die faces the back side of the pre-wiring substrate.
13. The method for manufacturing a semiconductor package structure according to any one of claims 6 to 12, wherein the pre-wiring substrates of the members to be molded are connected together, and the step of cutting to form a plurality of semiconductor packages is performed by cutting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202110336530.3A CN115148716A (en) | 2021-03-29 | 2021-03-29 | Semiconductor packaging structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110336530.3A CN115148716A (en) | 2021-03-29 | 2021-03-29 | Semiconductor packaging structure and manufacturing method thereof |
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| CN115148716A true CN115148716A (en) | 2022-10-04 |
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| CN202110336530.3A Pending CN115148716A (en) | 2021-03-29 | 2021-03-29 | Semiconductor packaging structure and manufacturing method thereof |
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- 2021-03-29 CN CN202110336530.3A patent/CN115148716A/en active Pending
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