CN115144730A - Chip internal circuit aging detection method and detection circuit - Google Patents
Chip internal circuit aging detection method and detection circuit Download PDFInfo
- Publication number
- CN115144730A CN115144730A CN202210798807.9A CN202210798807A CN115144730A CN 115144730 A CN115144730 A CN 115144730A CN 202210798807 A CN202210798807 A CN 202210798807A CN 115144730 A CN115144730 A CN 115144730A
- Authority
- CN
- China
- Prior art keywords
- circuit
- chip
- detection module
- detection
- abnormal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a chip internal circuit aging detection method and a detection circuit, wherein the chip internal circuit aging detection method comprises the following steps: powering on the chip; the test circuit calls each detection module to detect the internal circuit corresponding to the detection module; if the detection fails, the corresponding detection module generates a power-on abnormal signal to prompt the abnormality, the chip stops power-on, and an alarm signal notification is sent; and if the detection is passed, the detection is finished, and the chip is normally electrified to work. The invention calls each detection module of the test circuit to detect the internal circuit corresponding to the detection module after the chip is electrified, if the detection is passed, the chip is electrified normally to work, otherwise, an electrifying abnormal signal is generated to prompt the abnormality, so that the chip stops electrifying, and an alarm signal notification is sent. The invention can complete the detection of the internal circuit of the chip through the test circuit in the chip without adopting an external instrument, and has simple detection of the internal circuit of the chip and lower detection cost.
Description
Technical Field
The present invention relates to the field of technologies, and in particular, to a method and a circuit for detecting aging of an internal circuit of a chip.
Background
With the continuous development of the 5G, internet of things and new energy automobile industry, micro Controller Unit (MCU) chips are widely used, and MCU products are mainly applied to five major fields of consumer electronics, computers and networks, automotive electronics, industrial control, IC cards, and the like.
After the micro control chip is repeatedly used for a long time, the chip is internally broken down due to abrasion or fatigue (aging), so that the function of the original design cannot be executed, the operation of a program and the use of a product are influenced, and the aging detection of a circuit inside the chip is required. At present, for the aging detection of the internal circuit of the chip, an external instrument (such as an aging tester and an automatic test equipment) is usually adopted for detection, however, the adoption of the above method is complex and has high cost.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a method and a circuit for detecting aging of an internal circuit of a chip, so as to solve the problems of complicated internal aging detection method and high cost of the conventional micro control chip.
The technical scheme of the invention is as follows:
a chip internal circuit aging detection method comprises the following steps:
powering on the chip;
the test circuit calls each detection module to detect the internal circuit corresponding to the detection module;
if the detection fails, the corresponding detection module generates a power-on abnormal signal to prompt the abnormality, the chip stops being powered on, and an alarm signal notification is sent;
and if the detection is passed, the detection is finished, and the chip is normally electrified to work.
In a further configuration of the present invention, if the detection fails, the corresponding detection module generates a power-on abnormal signal to prompt an abnormality, the chip stops power-on, and the step of sending an alarm signal notification includes:
if at least one internal circuit is detected to be abnormal, judging whether the abnormal point influences the program operation of the chip;
if so, ending the chip power-on;
if not, the chip is normally powered on.
In a further configuration of the present invention, if the detection fails, the step of generating a power-on abnormal signal by the corresponding detection module to prompt an abnormality, stopping power-on of the chip, and sending an alarm signal to notify further includes:
if the first internal circuit is detected to be abnormal, judging whether the current abnormal point influences the program operation of the chip;
if so, ending the chip power-on;
if not, further detecting the next internal circuit until the detection of each internal circuit is completed.
The further arrangement of the present invention is that the step of the test circuit invoking each detection module to detect the internal circuit corresponding to the detection module further comprises:
detecting whether a system circuit is abnormal;
if the system circuit is detected to be abnormal, the system circuit sends a power-on abnormal signal to prompt the abnormality;
and if the system circuit is detected to be normal, calling the test circuit to detect each internal circuit.
In a further aspect of the present invention, the detection module comprises: the device comprises a digital circuit detection module, a peripheral circuit detection module, an analog circuit detection module and a memory detection module;
the internal circuit includes: digital circuit, peripheral circuit, analog circuit and memory.
According to a further configuration of the present invention, the power-on exception signal includes an interrupt signal, a flag signal, and an external signal.
The chip internal circuit aging detection circuit comprises a plurality of detection modules correspondingly connected with the internal circuit, wherein the detection modules are used for detecting the internal circuit after the chip is electrified and generating an electrifying abnormal signal when the corresponding internal circuit is detected to be abnormal.
In a further aspect of the present invention, the detection module comprises: the device comprises a digital circuit detection module, a peripheral circuit detection module, an analog circuit detection module and a memory detection module; wherein the content of the first and second substances,
the peripheral circuit detection module is connected with the peripheral environment detection circuit and is used for detecting whether the peripheral circuit is normal or not;
the digital circuit detection module is connected with the digital circuit and is used for detecting whether the digital circuit is normal or not;
the analog circuit detection module is connected with the analog circuit and is used for detecting whether the analog circuit is abnormal or not;
the memory detection module is connected with the memory and used for detecting whether the analog circuit is abnormal or not.
In a further aspect of the invention, the digital circuit detection module comprises: a first scanning trigger and a second scanning trigger; the first scanning trigger is connected with the input end of the digital circuit, and the second scanning trigger is connected with the output end of the digital circuit;
the first scanning trigger is used for inputting test data to the digital circuit;
the digital circuit is used for receiving the test data, performing operation and outputting operation data to the second scanning trigger;
the second scanning trigger is used for outputting the operation data output by the digital circuit;
and if the operation data output by the second scanning trigger is consistent with the expected output result, the digital circuit is normal, otherwise, the digital circuit is abnormal.
In a further aspect of the present invention, the peripheral circuit detection module comprises: a first test controller; the first test controller is connected with the peripheral circuit and used for inputting input data to the peripheral circuit, receiving output data output by the peripheral circuit, comparing the input data with the output data, if the input data is consistent with the output data, the peripheral circuit is normal, otherwise, the peripheral circuit is abnormal;
the analog circuit detection module includes: a second test controller; the second test controller is connected with the analog circuit; the second test controller is used for inputting input data to the analog circuit, receiving output data output by the analog circuit, comparing the output data with the input data, if the input data is consistent with the output data, the analog circuit is normal, otherwise, the analog circuit is abnormal;
the memory detection module includes: a third test controller; the third test controller is connected with the memory and is used for inputting the write data into the memory, reading the data of the memory to obtain read data, comparing the write data with the read data, and if the read data is consistent with the write data, the memory is normal, otherwise, the memory is abnormal.
The invention provides a chip internal circuit aging detection method and a detection circuit, wherein the chip internal circuit aging detection method comprises the following steps: powering on the chip; the test circuit calls each detection module to detect the internal circuit corresponding to the detection module; if the detection fails, the corresponding detection module generates a power-on abnormal signal to prompt the abnormality, the chip stops power-on, and an alarm signal notification is sent; and if the detection is passed, the detection is finished, and the chip is normally electrified to work. The invention calls each detection module of the test circuit to detect the internal circuit corresponding to the detection module after the chip is electrified, if the detection is passed, the chip is electrified normally to work, otherwise, an electrifying abnormal signal is generated to prompt the abnormality, so that the chip stops electrifying, and an alarm signal notification is sent. Therefore, the internal circuit of the chip can be detected through the test circuit in the chip, and an external instrument is not required for detection, so that the detection of the internal circuit of the chip is simpler, and the detection cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a flow chart of a method for detecting the aging of a chip internal circuit according to the present invention.
FIG. 2 is a flowchart illustrating an embodiment of a method for detecting aging of an internal circuit of a chip according to the present invention.
Fig. 3 is a schematic block diagram of the circuit for detecting the aging of the internal circuit of the chip according to the present invention.
FIG. 4 is a schematic diagram of the digital circuit detection module detecting digital circuits according to the present invention.
Fig. 5 is a schematic diagram of the peripheral circuit detection module detecting the peripheral circuit in the present invention.
FIG. 6 is a schematic diagram of an analog circuit detection module for detecting an analog circuit according to the present invention.
FIG. 7 is a schematic diagram of the memory detection module detecting the memory according to the present invention.
The various symbols in the drawings: 100. a chip internal circuit aging detection circuit; 110. a digital circuit detection module; 120. a peripheral circuit detection module; 121. a first test controller; 130. an analog circuit detection module; 131. a second test controller; 140. a memory detection module; 141. a third test controller; 200. a processor.
Detailed Description
The invention provides a method and a circuit for detecting aging of an internal circuit of a chip, which are further described in detail below with reference to the accompanying drawings and examples in order to make the purpose, technical scheme and effect of the invention clearer and clearer. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the embodiments and claims, the articles "a", "an", "the" and "the" may include plural forms as well, unless the context specifically dictates otherwise. If there is a description relating to "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or to imply that the number of technical features indicated is implicit. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, technical solutions between the embodiments may be combined with each other, but must be based on the realization of the technical solutions by a person skilled in the art, and when the technical solutions are contradictory to each other or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1 to 2, the present invention provides a method for detecting aging of an internal circuit of a chip.
As shown in fig. 1, the method for detecting aging of an internal circuit of a chip according to the present invention includes the steps of:
s100, powering on a chip;
s200, the test circuit calls each detection module to detect the internal circuit corresponding to the detection module;
s300, if the detection fails, the corresponding detection module generates a power-on abnormal signal to prompt the abnormality, the chip stops being powered on, and an alarm signal notification is sent;
s400, if the detection is passed, the detection is finished, and the chip is normally electrified to work.
Specifically, each detection module of the test circuit corresponds to an internal circuit to be detected by the chip, and after the chip is powered on each time, the chip calls the test circuit to detect the internal circuit of the chip. When the test circuit is implemented specifically, each module of the test circuit sequentially detects the internal circuit corresponding to the test circuit, if the detection module detects that the internal circuit is abnormal (invalid), a power-on abnormal signal is generated to give a processor of the chip to prompt the abnormality, the chip is controlled to stop power-on, an alarm signal is sent to inform the processor, and if the detection module detects that the internal circuit is normal, the chip is powered on normally to work. Therefore, the internal circuit of the chip can be detected through the Test circuit in the chip, and external instruments such as an aging tester and Automatic Test Equipment (ATE) are not required to be adopted for detection, so that the detection of the internal circuit of the chip is simpler, the detection flow is simplified, and the detection cost is reduced.
In some embodiments, step S200 comprises:
s210, if at least one internal circuit is detected to be abnormal, judging whether abnormal points influence the program operation of the chip;
s220, if the influence is caused, ending the chip power-on;
and S230, if the influence is not caused, normally powering on the chip.
Specifically, when the detection module detects that the internal circuit corresponding to the detection module is abnormal, whether an abnormal point generated by the abnormal module influences the operation of the current program of the chip is judged, if so, the chip is stopped to be powered on, and if not, the chip is normally powered on.
In some embodiments, step S200 further comprises:
s211, if the first internal circuit is detected to be abnormal, judging whether the current abnormal point influences the program operation of the chip;
s212, if the influence is caused, ending the chip power-on;
and S213, if the influence is not caused, further detecting the next internal circuit until the detection of each internal circuit is finished.
Specifically, when the detection module detects that the internal circuit corresponding to the detection module is abnormal, the chip judges whether an abnormal point caused by the abnormality of the current internal circuit influences the operation of the current program of the chip, if so, the chip is stopped to be powered on, if not, the next internal circuit is detected, and the chip can continue to operate normally until all internal circuits are detected to pass.
In some embodiments, step S200 further comprises, before step S:
s110, detecting whether a system circuit is abnormal or not;
s120, if the system circuit is detected to be abnormal, the system circuit sends a power-on abnormal signal to prompt the abnormality;
and S130, if the system circuit is detected to be normal, calling a test circuit to detect each internal circuit.
Specifically, after the chip is powered on, the system circuit is first detected, and if the system circuit is normal, the test circuit is called to detect the internal circuit. If the system circuit is abnormal, the system circuit sends a power-on abnormal signal to the processor to prompt the abnormality, so that the chip is controlled to stop power-on.
In some embodiments, the detection module comprises: the device comprises a digital circuit detection module, a peripheral circuit detection module, an analog circuit detection module and a memory detection module; the internal circuit includes: digital circuit, peripheral circuit, analog circuit and memory.
Specifically, after the chip is powered on, the test circuit can sequentially transfer the peripheral circuit detection module to detect the peripheral circuit, transfer the digital circuit detection module to detect the digital circuit, transfer the analog circuit detection module to detect the analog circuit and transfer the memory module to detect the memory, if the detection of the detection module fails, the corresponding detection module generates a power-on abnormal signal to the processor to indicate that the internal circuit corresponding to the detection module fails, and judges whether the failure point can affect the operation of the existing program, if so, the detection is stopped and the power-on of the chip is stopped, if not, the next internal circuit is detected, and the chip can normally operate sequentially until the internal circuit is detected to pass.
In some embodiments, the power-on exception signal includes an interrupt signal, a flag signal, and an external signal.
Referring to FIG. 2, for a better understanding of the present invention, an embodiment of the present invention is further described below.
As shown in fig. 2, after the chip is powered on, the system circuit is first detected, and if the system circuit is not detected properly, the chip is powered off. If the system circuit is detected to be free of problems, the chip can automatically transfer a peripheral circuit detection module to detect the peripheral circuit, transfer a digital circuit detection module to detect the digital circuit, transfer an analog circuit detection module to detect the analog circuit and transfer a memory module to detect the memory according to the sequence, and if a certain internal circuit is detected to be failed, the detection module corresponding to the internal circuit can generate an interrupt signal or a flag bit signal or an external signal to prompt that the corresponding internal circuit is abnormal (invalid). If the current internal circuit is detected to be abnormal, whether abnormal points caused by the current internal circuit abnormality influence the operation of the current program of the chip is judged, if the abnormal points cause the current internal circuit abnormality, the chip is stopped to be electrified, if the abnormal points do not influence the operation of the current program of the chip, the next internal circuit is detected, and the chip detection work is finished until all the internal circuits pass the detection, which indicates that the chip can continue to operate normally.
Referring to fig. 3, in some embodiments, the present invention further provides a chip internal circuit aging detection circuit 100 applied to the above description, which includes a plurality of detection modules correspondingly connected to the internal circuit, where the detection modules are used to detect the internal circuit after the chip is powered on, and to generate a power-on abnormal signal when a corresponding internal circuit is detected to be abnormal.
Specifically, the chip internal circuit aging detection circuit 100 is integrated on a Micro Control Unit (MCU), and when the chip is powered on, each detection module of the test circuit is called to detect the internal circuit corresponding to the detection module, if the detection is passed, the chip is powered on normally, otherwise, a power-on abnormal signal is generated to prompt an abnormality, so that the chip is powered off, and an alarm signal notification is sent. Therefore, the internal circuit of the chip can be detected through the test circuit in the chip, and an external instrument is not required for detection, so that the detection of the internal circuit of the chip is simpler, and the detection cost is reduced.
Referring to fig. 3, in some embodiments, the detection module includes: a digital circuit detection module 110, a peripheral circuit detection module 120, an analog circuit detection module 130 and a memory detection module 140; the peripheral circuit detection module 120 is connected to the peripheral environment detection circuit, and the peripheral circuit detection module 120 is configured to detect whether the peripheral circuit is normal; the digital circuit detection module 110 is connected to the digital circuit, and the digital circuit detection module 110 is configured to detect whether the digital circuit is normal; the analog circuit detection module 130 is connected to the analog circuit, and the analog circuit detection module 130 is configured to detect whether the analog circuit is abnormal; the memory detection module 140 is connected to the memory, and the memory detection module 140 is configured to detect whether the analog circuit is abnormal.
Specifically, after the chip is powered on, the test circuit will sequentially call the peripheral circuit detection module 120 to detect the peripheral circuit, call the digital circuit detection module 110 to detect the digital circuit, call the analog circuit detection module 130 to detect the analog circuit, and call the memory detection module 140 to detect the memory, if any detection module fails, the corresponding detection module will generate a power-on abnormal signal to the processor 200 to indicate that the corresponding internal circuit fails, and determine whether the failure point will affect the operation of the existing program, if so, stop the detection and stop the power-on of the chip, if not, detect the next internal circuit, and sequentially until the internal circuit passes the detection, the chip can operate normally.
Referring to fig. 3 and 4, in some embodiments, the digital circuit detecting module 110 includes: a first scanning trigger and a second scanning trigger; the first scanning trigger is connected with the input end of the digital circuit, and the second scanning trigger is connected with the output end of the digital circuit; the first scanning trigger is used for inputting test data to the digital circuit; the digital circuit is used for receiving the test data, performing operation and outputting operation data to the second scanning trigger; the second scanning trigger is used for outputting the operation data output by the digital circuit; and if the operation data output by the second scanning trigger is consistent with the expected output result, the digital circuit is normal, otherwise, the digital circuit is abnormal.
Specifically, the digital circuit detection module 110 is implemented by replacing flip-flops (DFFs) in the scan chain with scan flip-flops (SDFFs), as shown in fig. 4. In fig. 4, SE is Scan switching enable signal, and in normal mode, SE =0, and SE =1, scan common is performed, and SI is the entry of data flow during test. The specific working process of the digital circuit detection module 110 is as follows: when the SE is effectively pulled up, test data are serially input into an SDFF (namely a first scanning trigger) through an SI, then the SE is pulled down, a median value (namely the test data) of the SDFF (namely the first scanning trigger) is operated by a digital circuit, then operation data are output to reach a D end of an SDFF (namely a second scanning trigger) of the next stage, at the moment, a CLK (clock) period is generated, output data of the D end of the SDFF (namely the second scanning trigger) are sequentially and serially output, if the output operation data are consistent with an expected output result, the digital circuit tested at present is normal, otherwise, abnormal processing is carried out, and a power-on abnormal signal is sent out.
Referring to fig. 3 and 5, in some embodiments, the peripheral circuit detection module 120 includes: the first test controller 121; the first test controller 121 is connected to the peripheral circuit, and the first test controller 121 is configured to input data to the peripheral circuit, receive output data output by the peripheral circuit, compare the input data with the output data, and if the input data is consistent with the output data, the peripheral circuit is normal, otherwise, the peripheral circuit is abnormal.
Specifically, in fig. 4, the bist _ en, bist _ CLK, and bist _ RSTN are test signals, the S _ CLK, S _ DOUT, and S _ RSTN are signals in a normal operating state, the test _ fail and the test _ done are test state signals, and data is transmitted between the first test controller 121 and the peripheral circuit through a Multiplexer (MUX). When the best _ en =0, the peripheral circuit normally works, when the best _ en =1, the peripheral circuit detection module 120 starts to test the peripheral circuit of the micro control chip, and compares the input data with the output data through the first test controller 121, if the input data and the output data are inconsistent, the test _ fail is pulled high, and the test _ done is pulled high to indicate that the test is completed.
Referring to fig. 3 and 6, in some embodiments, the analog circuit detecting module 130 includes: the second test controller 131; the second test controller 131 is connected with an analog circuit; the second test controller 131 is configured to input data to the analog circuit, receive output data output by the analog circuit, compare the output data with the input data, and if the input data is consistent with the output data, the analog circuit is normal, otherwise, the analog circuit is abnormal.
Specifically, the bist _ en, bist _ CLK, and bist _ RSTN are test signals, the S _ CLK, S _ DOUT, and S _ RSTN are signals in a normal operating state, the test _ fail and the test _ done are test state signals, and data is transmitted between the second test controller 131 and the analog circuit through a Multiplexer (MUX).
When the best _ en =0, the analog circuit normally works, when the best _ en =1, the analog circuit detection module 130 starts to test the analog circuit inside the micro control chip, and the second test controller 131 compares the input data with the output data, if the input data and the output data are inconsistent, the test _ fail is pulled high, and the test _ done is pulled high to indicate that the test is completed.
Referring to fig. 3 and 7, in some embodiments, the memory detection module 140 includes: the third test controller 141; the third test controller 141 is connected to the memory, and the third test controller 141 is configured to input write data into the memory, then read data of the memory to obtain read data, and compare the write data with the read data, where if the read data is consistent with the write data, the memory is normal, and otherwise, the memory is abnormal.
Specifically, the bist _ en, bist _ CLK, and bist _ RSTN are test signals, the S _ CLK, S _ DOUT, and S _ RSTN are signals in a normal operating state, the test _ fail and the test _ done are test state signals, and data is transmitted between the third test controller 141 and the analog circuit through a Multiplexer (MUX).
When the best _ en =0, the memory (RAM/ROM) works normally, and when the best _ en =1, the memory detection module 140 starts to test the RAM/ROM inside the MCU, and reads after writing, and then compares the write data with the read data, if not, then the test _ fail is pulled high, and the test is completed.
In summary, the present invention provides a method and a circuit for detecting aging of an internal circuit of a chip, wherein the method comprises: powering on the chip; the test circuit calls each detection module to detect the internal circuit corresponding to the detection module; if the detection fails, the corresponding detection module generates a power-on abnormal signal to prompt the abnormality, the chip stops being powered on, and an alarm signal notification is sent; if the detection is passed, the detection is finished, and the chip is normally electrified to work. The invention calls each detection module of the test circuit to detect the internal circuit corresponding to the detection module after the chip is electrified, if the detection is passed, the chip is electrified normally to work, otherwise, an electrifying abnormal signal is generated to prompt the abnormality, so that the chip stops electrifying, and an alarm signal notification is sent. Therefore, the internal circuit of the chip can be detected through the test circuit in the chip, an external instrument is not needed for detection, the dependence degree on automatic test equipment is reduced, the detection of the internal circuit of the chip is simpler, the detection flow is simplified, and the detection cost is reduced.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A method for detecting aging of an internal circuit of a chip is characterized by comprising the following steps:
powering on the chip;
the test circuit calls each detection module to detect the internal circuit corresponding to the detection module;
if the detection fails, the corresponding detection module generates a power-on abnormal signal to prompt the abnormality, the chip stops power-on, and an alarm signal notification is sent;
and if the detection is passed, the detection is finished, and the chip is normally electrified to work.
2. The method for detecting aging of internal circuit of chip as claimed in claim 1, wherein if the detection fails, the corresponding detection module generates power-on abnormal signal to prompt abnormality, the chip stops power-on, and the step of sending out alarm signal notification includes:
if at least one internal circuit is detected to be abnormal, judging whether the abnormal point influences the program operation of the chip;
if so, ending the chip power-on;
if not, the chip is normally powered on.
3. The method according to claim 2, wherein if the detection fails, the corresponding detection module generates a power-on abnormal signal to indicate an abnormality, the chip stops power-on, and the step of sending an alarm signal notification further comprises:
if the first internal circuit is detected to be abnormal, judging whether the current abnormal point influences the program operation of the chip;
if so, ending the chip power-on;
if not, further detecting the next internal circuit until the detection of each internal circuit is completed.
4. The method for detecting aging of internal circuit of chip as claimed in claim 1, wherein the step of the test circuit invoking each detection module to detect the internal circuit corresponding to the detection module further comprises:
detecting whether a system circuit is abnormal;
if the system circuit is detected to be abnormal, the system circuit sends out a power-on abnormal signal to prompt the abnormality;
and if the system circuit is detected to be normal, calling the test circuit to detect each internal circuit.
5. The method for detecting the aging of the circuit inside the chip as claimed in claim 1, wherein the detection module comprises: the device comprises a digital circuit detection module, a peripheral circuit detection module, an analog circuit detection module and a memory detection module;
the internal circuit includes: digital circuit, peripheral circuit, analog circuit and memory.
6. The method according to claim 1, wherein the power-on abnormality signal includes an interrupt signal, a flag signal, and an external signal.
7. The chip internal circuit aging detection circuit applied to any one of claims 1-6, comprising a plurality of detection modules correspondingly connected with the internal circuit, wherein the detection modules are used for detecting the internal circuit after the chip is powered on and generating a power-on abnormal signal when the corresponding internal circuit is detected to be abnormal.
8. The chip internal circuit degradation detection circuit according to claim 7, wherein the detection module comprises: the device comprises a digital circuit detection module, a peripheral circuit detection module, an analog circuit detection module and a memory detection module; wherein the content of the first and second substances,
the peripheral circuit detection module is connected with the peripheral environment detection circuit and is used for detecting whether the peripheral circuit is normal or not;
the digital circuit detection module is connected with the digital circuit and is used for detecting whether the digital circuit is normal or not;
the analog circuit detection module is connected with the analog circuit and is used for detecting whether the analog circuit is abnormal or not;
the memory detection module is connected with the memory and used for detecting whether the analog circuit is abnormal or not.
9. The in-chip circuit degradation detection circuit of claim 8, wherein the digital circuit detection module comprises: a first scanning trigger and a second scanning trigger; the first scanning trigger is connected with the input end of the digital circuit, and the second scanning trigger is connected with the output end of the digital circuit;
the first scanning trigger is used for inputting test data to the digital circuit;
the digital circuit is used for receiving the test data, performing operation and outputting operation data to the second scanning trigger;
the second scanning trigger is used for outputting the operation data output by the digital circuit;
and if the operation data output by the second scanning trigger is consistent with the expected output result, the digital circuit is normal, otherwise, the digital circuit is abnormal.
10. The chip internal circuit degradation detection circuit according to claim 8, wherein the peripheral circuit detection module comprises: a first test controller; the first test controller is connected with the peripheral circuit and used for inputting input data to the peripheral circuit, receiving output data output by the peripheral circuit, comparing the input data with the output data, if the input data is consistent with the output data, the peripheral circuit is normal, otherwise, the peripheral circuit is abnormal;
the analog circuit detection module includes: a second test controller; the second test controller is connected with the analog circuit; the second test controller is used for inputting input data to the analog circuit, receiving output data output by the analog circuit, comparing the output data with the input data, if the input data is consistent with the output data, the analog circuit is normal, otherwise, the analog circuit is abnormal;
the memory detection module includes: a third test controller; the third test controller is connected with the memory and used for inputting the write data into the memory, reading the data of the memory to obtain read data, comparing the write data with the read data, if the read data is consistent with the write data, the memory is normal, otherwise, the memory is abnormal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210798807.9A CN115144730B (en) | 2022-07-08 | 2022-07-08 | Chip internal circuit aging detection method and detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210798807.9A CN115144730B (en) | 2022-07-08 | 2022-07-08 | Chip internal circuit aging detection method and detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115144730A true CN115144730A (en) | 2022-10-04 |
| CN115144730B CN115144730B (en) | 2023-04-18 |
Family
ID=83412719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210798807.9A Active CN115144730B (en) | 2022-07-08 | 2022-07-08 | Chip internal circuit aging detection method and detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115144730B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117521588A (en) * | 2024-01-08 | 2024-02-06 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201096847Y (en) * | 2007-08-22 | 2008-08-06 | 比亚迪股份有限公司 | A chip aging testing system |
| CN101303392A (en) * | 2008-06-04 | 2008-11-12 | 北京中星微电子有限公司 | Digital logic chip and method capable of testing design |
| CN101719088A (en) * | 2009-11-23 | 2010-06-02 | 北京龙芯中科技术服务中心有限公司 | Device and method for detecting processor chip on line |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
| CN105319495A (en) * | 2014-11-26 | 2016-02-10 | 北京同方微电子有限公司 | Built-in automatic aging testing device of integrated circuit chips |
| CN111459726A (en) * | 2019-01-18 | 2020-07-28 | 中山远实微科技有限公司 | Chip and chip self-repairing method |
| US20210148969A1 (en) * | 2018-10-08 | 2021-05-20 | HKC Corporation Limited | Chip abnormality detecting circuit and chip abnormality detecting device |
| CN113064052A (en) * | 2021-03-24 | 2021-07-02 | 深圳佰维存储科技股份有限公司 | Chip aging test circuit and chip aging test system |
| CN113791338A (en) * | 2021-11-17 | 2021-12-14 | 北京中科海芯科技有限公司 | Chip testing method and device |
| CN114076883A (en) * | 2021-11-10 | 2022-02-22 | 北京中电华大电子设计有限责任公司 | Aging circuit, chip aging test method and chip |
| CN114168395A (en) * | 2021-11-12 | 2022-03-11 | 天固信息安全系统(深圳)有限公司 | Chip power-on control method, control device and storage medium |
-
2022
- 2022-07-08 CN CN202210798807.9A patent/CN115144730B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201096847Y (en) * | 2007-08-22 | 2008-08-06 | 比亚迪股份有限公司 | A chip aging testing system |
| CN101303392A (en) * | 2008-06-04 | 2008-11-12 | 北京中星微电子有限公司 | Digital logic chip and method capable of testing design |
| CN101719088A (en) * | 2009-11-23 | 2010-06-02 | 北京龙芯中科技术服务中心有限公司 | Device and method for detecting processor chip on line |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
| CN105319495A (en) * | 2014-11-26 | 2016-02-10 | 北京同方微电子有限公司 | Built-in automatic aging testing device of integrated circuit chips |
| US20210148969A1 (en) * | 2018-10-08 | 2021-05-20 | HKC Corporation Limited | Chip abnormality detecting circuit and chip abnormality detecting device |
| CN111459726A (en) * | 2019-01-18 | 2020-07-28 | 中山远实微科技有限公司 | Chip and chip self-repairing method |
| CN113064052A (en) * | 2021-03-24 | 2021-07-02 | 深圳佰维存储科技股份有限公司 | Chip aging test circuit and chip aging test system |
| CN114076883A (en) * | 2021-11-10 | 2022-02-22 | 北京中电华大电子设计有限责任公司 | Aging circuit, chip aging test method and chip |
| CN114168395A (en) * | 2021-11-12 | 2022-03-11 | 天固信息安全系统(深圳)有限公司 | Chip power-on control method, control device and storage medium |
| CN113791338A (en) * | 2021-11-17 | 2021-12-14 | 北京中科海芯科技有限公司 | Chip testing method and device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117521588A (en) * | 2024-01-08 | 2024-02-06 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
| CN117521588B (en) * | 2024-01-08 | 2024-05-10 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115144730B (en) | 2023-04-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6717429B2 (en) | IC having comparator inputs connected to core circuitry and output pad | |
| US7552028B2 (en) | Recording medium, test apparatus and diagnostic method | |
| CN115144730B (en) | Chip internal circuit aging detection method and detection circuit | |
| US6857093B2 (en) | Semiconductor integrated circuit device capable of self-testing internal power supply currents provided to internal circuits integrated on chip | |
| US20050157565A1 (en) | Semiconductor device for detecting memory failure and method thereof | |
| US6346822B2 (en) | Semiconductor integrated circuit having diagnosis function | |
| US6934884B1 (en) | One-chip microcomputer and control method thereof as well as an IC card having such a one-chip microcomputer | |
| US7913002B2 (en) | Test apparatus, configuration method, and device interface | |
| CN103065689A (en) | Integrated circuit chip and semiconductor memory device | |
| JP3200565B2 (en) | Microprocessor and inspection method thereof | |
| JP4162902B2 (en) | Comparator abnormality detection device | |
| US5513189A (en) | Boundary scan system with improved error reporting using sentinel bit patterns | |
| CN109144024B (en) | Integrated circuit chip and inspection method thereof | |
| JPH1069396A (en) | Chip inspection system and controller | |
| JP2007010605A (en) | Testing device and testing method | |
| JP3605997B2 (en) | Semiconductor device | |
| US6850860B2 (en) | Semiconductor device testing apparatus and test method therefor | |
| US6986082B2 (en) | Testing system for semiconductor memory device | |
| KR200258985Y1 (en) | Test device with noise level detection | |
| US20200004305A1 (en) | Data processing device | |
| JP2853381B2 (en) | Semiconductor integrated circuit | |
| KR100480561B1 (en) | Micro-rom having check sum part | |
| JP2953376B2 (en) | Semiconductor integrated circuit | |
| US6820226B2 (en) | Method, apparatus and computer program product for contention testing | |
| JP2005078603A (en) | Test method of data processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |