CN115132910B - Measuring device for surface distribution of two-level defects and preparation method thereof - Google Patents
Measuring device for surface distribution of two-level defects and preparation method thereof Download PDFInfo
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- CN115132910B CN115132910B CN202211051919.4A CN202211051919A CN115132910B CN 115132910 B CN115132910 B CN 115132910B CN 202211051919 A CN202211051919 A CN 202211051919A CN 115132910 B CN115132910 B CN 115132910B
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H—ELECTRICITY
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- H10N60/0912—Manufacture or treatment of Josephson-effect devices
Abstract
The invention relates to a measuring device for surface distribution of two-level defects and a preparation method thereof, wherein the measuring device comprises an electric field generating device and a surface defect measuring structure; the surface defect measuring structure comprises a bottom sheet and a top sheet; the top sheet is provided with an electrode; the electrodes comprise grating electrodes or grid electrodes; the negative film is provided with a bit circuit; the bottom sheet and the top sheet are connected through micro-convex point flip-chip welding to form a structure with an electrode right above the bit circuit; the electric field generating device is connected with the electrodes to realize electric field regulation and control on the surface distribution of the two-level defects. The invention applies voltage to different areas of the grating electrode or the grid electrode to generate electric fields at different positions of the surface of the bit circuit, thereby realizing the electric field regulation and control of the surface distribution of the two-level defect and realizing the measurement of the surface distribution of the two-level defect.
Description
Technical Field
The invention belongs to the technical field of quantum computation, relates to a measuring device for a two-level defect, and particularly relates to a measuring device for surface distribution of the two-level defect and a preparation method thereof.
Background
The quantum computer utilizes the principle of quantum mechanics to calculate, can solve the problem that some classical calculations are difficult to solve, and has the capability far beyond the classical computer in the aspects of password security, artificial intelligence, biochemical pharmaceutical simulation and the like. Superconducting quantum computing is widely considered to be one of the methods that have the most possibility to take the lead to practical quantum computing, because of its advantages in controllability, low loss, scalability, and the like.
At present, although the development of superconducting quantum computers has been advanced, in order to operate quantum algorithms having utility value, further improvement of the number and quality of qubits is required. However, the superconducting quantum chip introduces two-level defects in the material growth and device processing processes, which can cause energy loss of the qubit, leading to bit decoherence, and seriously affecting the bit quality. Therefore, the research on the mechanism of the two-level defect can inhibit the formation of the two-level defect in the chip production process, and the method plays a vital role in improving the decoherence time of the superconducting quantum chip.
The development of superconducting quantum computers is limited by the decoherence time of bits, and the two-level defects introduced in the growth of quantum bit chip materials and device processing are one of the core factors causing decoherence of bits. The spatial distribution and generation mechanism of the two-level defects on the bit surface interface are researched, or the formation of the two-level defects in the chip production process can be reduced, and the bit de-coherence time is prolonged, so that the development of superconducting quantum calculation is promoted, and the realization and application of quantum calculation are promoted.
Therefore, it is necessary to provide a device for measuring the surface distribution of two-level defects and a method for manufacturing the same.
Disclosure of Invention
The invention aims to provide a measuring device for surface distribution of two-level defects and a preparation method thereof, wherein the measuring device can generate electric fields at different positions on the surface of a bit circuit, so that the electric field regulation and control of the surface distribution of the two-level defects are realized.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the invention provides a device for measuring the surface distribution of two-level defects, comprising an electric field generating device and a surface defect measuring structure;
the surface defect measuring structure comprises a backsheet and a topsheet;
the top sheet is provided with an electrode; the electrodes comprise grating electrodes or grid electrodes;
the negative film is provided with a bit circuit;
the bottom sheet and the top sheet are connected through micro-convex point flip-chip welding to form a structure with an electrode right above the bit circuit;
the electric field generating device is connected with the electrodes to realize electric field regulation and control on the surface distribution of the two-level defects.
The measuring device provided by the invention can realize the generation of electric fields at different positions on the surface of the bit circuit by forming the grating electrode or the grid electrode right above the bit circuit and matching with the use of the electric field generating device, thereby realizing the electric field regulation and control of the surface distribution of the two-level defect and realizing the measurement of the surface distribution of the two-level defect.
The electric field generating device comprises an electric field generating device which is conventional in the field, and the type of the electric field generating device is not particularly limited as long as voltage can be applied to the electrodes.
The material of the bottom plate or the top plate of the invention respectively and independently comprises any one of silicon, sapphire, silicon carbide, diamond, gaAs or SiGe.
Preferably, the bottom sheet or top sheet each independently comprises a silicon bottom sheet or a sapphire bottom sheet.
Preferably, the bit circuit and the electrode are each independently formed of a superconducting material.
The superconducting material of the present invention comprises aluminum and/or tantalum.
Preferably, the bit circuit has a josephson junction structure.
The material of the micro-convex point comprises indium.
The wire bonding in the art to external circuitry is typically done only in the negative. The arrangement of the micro-convex points can realize the support of the top sheet on one hand and can conduct the electrode circuit of the top sheet to the bottom sheet on the other hand.
The superconducting conducting material is arranged between the micro-convex points and the bottom plate, and comprises but is not limited to aluminum and/or tantalum. The indium has good flexibility, and the invention uses the indium as the micro-convex point, thereby being beneficial to reducing the loss during conduction. However, indium has a defect of forming an alloy layer with the superconducting conductive material, and is not favorable for reducing loss.
Preferably, a barrier layer is arranged between the micro-bumps and the bottom sheet.
The barrier layer arranged between the micro-convex points and the bottom sheet means that the barrier layer is arranged between the micro-convex points and the superconducting conduction material on the surface of the bottom sheet, so that an alloy layer is prevented from being formed between the indium and the superconducting conduction material.
Preferably, the barrier layer comprises any one or combination of at least two of a titanium nitride barrier layer, a titanium barrier layer, or a Pt barrier layer, with typical but non-limiting combinations including a titanium nitride barrier layer in combination with a titanium barrier layer, a titanium barrier layer in combination with a Pt barrier layer, a titanium nitride barrier layer in combination with a Pt barrier layer, or a titanium nitride barrier layer, a titanium barrier layer in combination with a Pt barrier layer.
Preferably, the grid electrode comprises a grid inner electrode and a grid outer electrode, and the grid inner electrode and the grid outer electrode are insulated by a dielectric layer.
The grid electrode further comprises a conventional metal contact (pad) disposed on the periphery of the top sheet, and the present invention is not described herein. The grid electrode is connected with the pad through the extending metal wire, and then the peripheral metal contact point is connected with the micro-convex point of the bottom plate.
Exemplary materials of the dielectric layer include, but are not limited to, silicon oxide and/or silicon nitride.
In a second aspect, the present invention provides a method of manufacturing a measuring device according to the first aspect, the method comprising the steps of:
(1) Preparing a bit circuit on the surface of the negative film;
(2) Arranging an electrode on the surface of the top sheet;
(3) The bottom sheet and the top sheet are connected through flip-chip bonding of the micro-bumps to form a structure with electrodes right above the bit circuit;
the step (1) and the step (2) are not in sequence.
Preferably, the step (1) of preparing the bit circuit on the surface of the negative film comprises: growing a superconducting material film on the surface of the negative film, and then forming a bit circuit;
the method for growing the superconducting material film on the surface of the bottom plate comprises but is not limited to a magnetron sputtering method and/or an epitaxial growth method.
The bit circuit comprises a Josephson junction structure, and when the bit circuit is formed, a capacitor, an inductor and a coplanar waveguide with relatively large size in the bit circuit are formed firstly, and then the Josephson junction structure with relatively small size is formed. The method for forming the bit circuit is a conventional method in the field, and exemplarily, a capacitance, an inductance and a coplanar waveguide with larger size in the bit circuit are prepared by adopting an ultraviolet photoetching method and/or an etching method; then, preparing a Josephson junction structure by adopting an electron beam lithography method and/or an electron beam evaporation method to complete the setting of the bit circuit on the surface of the negative film.
Preferably, the micro-bumps are disposed on the topsheet and/or the backsheet.
The micro-bumps in the flip chip bonding of the micro-bumps are arranged on the top sheet and/or the bottom sheet, and the method for arranging the micro-bumps comprises but is not limited to vacuum in-situ deposition.
Preferably, a barrier layer is further arranged between the micro-convex points and the bottom sheet.
Taking the case that the micro-convex points are arranged on the bottom sheet, the barrier layer is arranged between the micro-convex points and the bottom sheet, namely, the superconducting conduction material is arranged between the micro-convex points and the bottom sheet, and the barrier layer is arranged between the micro-convex points and the superconducting conduction material on the surface of the bottom sheet.
The setting method of the superconducting conducting material is the same as the growth method of the superconducting material film, and the setting method comprises but is not limited to a magnetron sputtering method and/or an epitaxial growth method. As a further preferred technical scheme, the superconducting conducting material and the superconducting material film grow simultaneously, that is, the superconducting film grows by adopting a magnetron sputtering method and/or an epitaxial growth method, and then the superconducting conducting material and the bit circuit are obtained by adopting an ultraviolet lithography method and/or an etching method; preferably, after the superconducting film is grown, when a capacitor, an inductor and a coplanar waveguide with relatively large size in a bit circuit are formed by using an ultraviolet lithography method and/or an etching method, the superconducting conducting material can be obtained at the same time.
The method for disposing the barrier layer includes, but is not limited to, magnetron sputtering and/or epitaxial growth.
The technical scheme that the micro-convex points are arranged on the top sheet is the same as the technical scheme that the micro-convex points are arranged on the bottom sheet, and the detailed description of the invention is omitted.
The structure of the electrode comprises a grating electrode or a grid electrode.
Preferably, when the electrode is a photogate electrode, the step (2) of disposing an electrode on the surface of the top sheet comprises: a film of superconducting material is grown on the surface of the top sheet, and then a grating electrode is formed.
In the present invention, the method for growing the thin film of superconducting material on the surface of the top sheet includes, but is not limited to, magnetron sputtering and/or epitaxial growth.
The method for forming the grating electrode comprises the steps of preparing an electrode extension area and pad areas at two ends of the electrode by adopting an ultraviolet photoetching method and/or an etching method, and then preparing the grating electrode which needs to be positioned right above a bit circuit by adopting an electron beam photoetching method and/or an etching method.
Preferably, when the electrode is a mesh electrode, the step (2) of disposing an electrode on the surface of the top sheet comprises:
at least 1 layer of the mesh electrode is grown on the surface of the top sheet, for example, 1, 2, 3, 4, 5 or 6 layers, but not limited to the values recited, and other values within the range are equally applicable.
When at least 2 layers of grid electrodes grow on the surface of the top sheet, any two adjacent layers of grid electrodes are insulated by medium layers. In the invention, the number of the grid electrode layers on the surface of the top sheet is at least 2, and the arrangement of the medium layers is matched, so that the risk of circuit cross short circuit between the internal grid electrode and the external grid electrode is avoided.
For example, to facilitate the explanation of the technical solution of the present invention, taking the top sheet surface as an example of growing 2 layers of mesh electrodes, the disposing of the electrodes on the top sheet surface includes:
(a) Growing a first superconducting material film on the surface of the top sheet, and then forming an in-grid electrode;
(b) Forming a dielectric layer on the top sheet and the surface of the grid inner electrode, growing a second superconducting material film on the surface of the dielectric layer, and then forming a grid outer electrode;
(c) And removing the redundant dielectric layer to expose the grid inner electrode.
In step (c), the excessive medium layer is removed to expose the grid inner electrode, and meanwhile, the conventional metal contact points on the periphery of the top sheet are exposed.
The first superconducting material film and the second superconducting material film are made of tantalum and/or aluminum respectively and independently.
The method for growing the first superconducting material film and the second superconducting material film comprises but is not limited to a magnetron sputtering method and/or an epitaxial growth method.
The method for forming the grid inner electrode in the step (a) includes, but is not limited to, processing the first superconducting material film by using an ultraviolet lithography method and/or an etching method, preparing an electrode extension area and pad areas at two ends of the electrode, and then preparing the grid inner electrode positioned right above the bit circuit by using an electron beam lithography method and/or an etching method.
The method for forming the grid external electrode in the step (b) includes, but is not limited to, processing the second superconducting material film by using an ultraviolet lithography method and/or an etching method, preparing an electrode extension area and pad areas at two ends of the electrode, and then preparing the grid external electrode by using an electron beam lithography method and/or an etching method.
The method for removing the excess dielectric layer in step (c) includes, but is not limited to, any one or a combination of at least two of uv lithography, e-beam lithography, or etching, and typical but non-limiting combinations include a combination of uv lithography and e-beam lithography, a combination of e-beam lithography and etching, a combination of uv lithography and etching, or a combination of uv lithography, e-beam lithography and etching.
As a preferable technical solution of the preparation method according to the second aspect of the present invention, the preparation method comprises the steps of:
(1) Growing a superconducting material film on the surface of the negative film, and then forming a bit circuit; then, arranging micro-bumps on the bottom sheet, wherein the micro-bumps are used for flip-chip bonding connection of the bottom sheet and the top sheet;
(2) The surface of the top sheet is provided with electrodes:
(3) The bottom sheet and the top sheet are connected through flip-chip bonding of the micro-bumps to form a structure with electrodes right above the bit circuit;
the step (1) and the step (2) are not in sequence;
the step (2) of disposing an electrode on the surface of the top sheet includes:
growing a superconducting material film on the surface of the top sheet, and then forming a grating electrode;
or the like, or, alternatively,
at least 1 layer of grid electrode is grown on the surface of the top sheet.
Compared with the prior art, the invention has the following beneficial effects:
the measuring device provided by the invention can realize the generation of electric fields at different positions on the surface of the bit circuit by forming the grating electrode or the grid electrode right above the bit circuit and matching with the use of the electric field generating device, thereby realizing the electric field regulation and control of the surface distribution of the two-level defect and realizing the measurement of the surface distribution of the two-level defect.
Drawings
FIG. 1 is a schematic structural diagram of a device for measuring the surface distribution of two-level defects provided in example 1;
fig. 2 is a schematic diagram illustrating the distribution of the bit circuit and the grating electrode in the measuring apparatus provided in embodiment 1;
FIGS. 3 and 4 are schematic views showing the application of the measuring apparatus of example 1, wherein V1 and V2 represent voltages applied to the electrodes;
FIG. 5 is a schematic structural diagram of an apparatus for measuring the surface distribution of two-level defects provided in example 3;
FIG. 6 is a schematic structural diagram of an apparatus for measuring the surface distribution of two-level defects provided in example 4;
FIG. 7 is a schematic diagram showing the distribution of bit circuits and grid electrodes in the measuring apparatus provided in embodiment 4;
FIG. 8 is a schematic view showing the structure of a grid electrode in the measuring apparatus provided in example 4; wherein the thick solid line is an extension lead which is communicated with the electrode and the peripheral metal contact point.
Wherein: 1, a negative film; 2, a topsheet; 3, a bit circuit; 4, micro bumps; 5, a grating electrode; 6, a barrier layer; 7, grid inner electrodes; 8, grid outer electrode; 81, metal contact points; 9, a dielectric layer; 10, a metal base.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments. It should be understood by those skilled in the art that the examples are only for the understanding of the present invention and should not be construed as the specific limitations of the present invention.
Example 1
The embodiment provides a measuring device for the surface distribution of two-level defects as shown in fig. 1, which comprises an electric field generating device and a surface defect measuring structure; the surface defect measuring structure comprises a bottom sheet 1 and a top sheet 2; the bottom plate 1 is a silicon bottom plate, and the top plate 2 is a silicon top plate;
the top sheet 2 is provided with electrodes; the electrode is a grating electrode 5;
the negative film 1 is provided with a bit circuit 3; the bit circuit 3 is formed by a superconducting material, and the superconducting material is aluminum;
the bit circuit 3 has a Josephson junction structure, the bottom sheet 1 and the top sheet 2 are connected by flip-chip bonding through micro bumps 4, and a structure with electrodes right above the bit circuit 3 is formed (see FIG. 2); the micro-bumps 4 are made of indium.
The electric field generating device is connected with the grating electrode 5, and electric field regulation and control of the surface distribution of the two-level defects are realized.
The preparation method of the measuring device in the embodiment comprises the following steps:
(1) A superconducting film is grown on the surface of the silicon substrate by adopting a magnetron sputtering method, a capacitor, an inductor and a coplanar waveguide with larger size in the bit circuit 3 are prepared by adopting an ultraviolet photoetching method and an etching method, and a superconducting conductive aluminum material is obtained at the periphery of the silicon substrate; then, preparing a Josephson junction structure by adopting an electron beam lithography method and an electron beam evaporation plating method to complete the setting of the bit circuit 3 on the surface of the negative film 1; then depositing the micro-convex points 4 on the surface of the superconducting conductive aluminum material in a vacuum in-situ manner;
(2) The surface of the silicon top sheet is provided with electrodes:
(3) The silicon bottom sheet and the silicon top sheet are connected through flip chip welding of the micro bumps 4 to form a structure that the electrodes are arranged right above the bit circuit 3;
the step (2) of arranging the grating electrode 5 on the surface of the silicon top sheet comprises the following steps: a superconducting material film is grown on the surface of a silicon top sheet by adopting a magnetron sputtering method, then an electrode extension area and pad areas at two ends of an electrode are prepared by adopting an ultraviolet photoetching method and an etching method, and then a grating electrode 5 which needs to be positioned right above a bit circuit 3 is prepared by adopting an electron beam photoetching method and the etching method.
When the measuring device provided by this embodiment is applied, an operator switches on different areas of the metal base 10 and the grating electrode 5, and applies voltages to different areas of the grating electrode 5 (see fig. 3 and 4), so as to generate electric fields at different positions on the surface of the bit circuit 3, thereby implementing electric field regulation and control on the surface distribution of the two-level defect, and implementing measurement of the surface distribution of the two-level defect.
Example 2
The embodiment provides a measuring device for surface distribution of two-level defects, which comprises an electric field generating device and a surface defect measuring structure; the surface defect measuring structure comprises a bottom sheet 1 and a top sheet 2; the bottom plate 1 is a sapphire bottom plate, and the top plate 2 is a sapphire top plate;
the top sheet 2 is provided with electrodes; the electrode is a grating electrode 5;
the negative film 1 is provided with a bit circuit 3; the bit circuit 3 is formed by a superconducting material, and the superconducting material is tantalum;
the bit circuit 3 has a Josephson junction structure, the bottom sheet 1 and the top sheet 2 are connected by flip-chip bonding through micro-bumps 4, and a structure with electrodes right above the bit circuit 3 is formed; the micro-bumps 4 are made of indium.
The electric field generating device is connected with the grating electrode 5, and electric field regulation and control of surface distribution of the two-level defects are realized.
The preparation method of the measuring device in the embodiment comprises the following steps:
(1) A superconducting film is grown on the surface of the sapphire substrate by adopting a magnetron sputtering method, a capacitor, an inductor and a coplanar waveguide with larger size in the bit circuit 3 are prepared by adopting an ultraviolet lithography method and an etching method, and a superconducting conduction tantalum material is obtained at the periphery of the sapphire substrate; then preparing a Josephson junction structure by adopting an electron beam lithography method and electron beam evaporation to complete the setting of the bit circuit 3 on the surface of the negative film 1; then depositing the micro-convex points 4 on the surface of the superconducting conductive tantalum material in a vacuum in-situ manner;
(2) The surface of the sapphire top sheet is provided with electrodes:
(3) The sapphire bottom plate and the sapphire top plate are connected through flip-chip welding of the micro-bumps 4 to form a structure with electrodes right above the bit circuit 3;
the step (2) of arranging the grating electrode 5 on the surface of the sapphire top sheet comprises the following steps: a superconducting material film is grown on the surface of a sapphire top sheet by adopting a magnetron sputtering method, then an electrode extension area and pad areas at two ends of an electrode are prepared by adopting an ultraviolet photoetching method and an etching method, and then a grating electrode 5 which needs to be positioned right above a bit circuit 3 is prepared by adopting an electron beam photoetching method and the etching method.
When the measuring device provided by the embodiment is applied, an operator switches on different areas of the metal base 10 and the grating electrode 5 to apply voltages to different areas of the grating electrode 5, so that electric fields are generated at different positions on the surface of the bit circuit 3, and therefore, the electric field regulation and control of the surface distribution of the two-level defect are realized, and the measurement of the surface distribution of the two-level defect is realized.
Example 3
This embodiment provides a measuring apparatus of the surface distribution of two-level defects as shown in fig. 5, compared with embodiment 1, this embodiment provides a barrier layer 6 between the micro-bump and the superconducting conductive aluminum material; the barrier layer 6 is a titanium nitride barrier layer 6.
When the measuring device provided by the embodiment is applied, an operator switches on different areas of the metal base 10 and the grating electrode 5 to apply voltages to different areas of the grating electrode 5, so that electric fields are generated at different positions on the surface of the bit circuit 3, the electric field regulation and control on the surface distribution of the two-level defect are realized, and the measurement of the surface distribution of the two-level defect is realized.
Compared with the embodiment 1, the embodiment avoids the formation of an alloy layer between the micro-convex points and the superconducting conductive aluminum material through the arrangement of the barrier layer 6, and reduces the loss when the top sheet is conducted with the bottom sheet.
Example 4
The embodiment provides a measuring device for the surface distribution of two-level defects as shown in fig. 6, which comprises an electric field generating device and a surface defect measuring structure; the surface defect measuring structure comprises a bottom sheet 1 and a top sheet 2; the bottom plate 1 is a silicon bottom plate, and the top plate 2 is a silicon top plate;
the top sheet 2 is provided with electrodes; the electrode is a grid electrode (see figure 8 for structural diagram);
the negative film 1 is provided with a bit circuit 3; the bit circuit 3 is formed by a superconducting material, and the superconducting material is aluminum;
the bit circuit 3 has a Josephson junction structure, the bottom sheet 1 and the top sheet 2 are connected by flip-chip bonding through micro bumps 4, and a structure with electrodes right above the bit circuit 3 is formed (see FIG. 7); the micro-bumps 4 are made of indium.
The electric field generating device is connected with the grid electrode to realize electric field regulation and control on the surface distribution of the two-level defects.
The preparation method of the measuring device in the embodiment comprises the following steps:
(1) A superconducting film is grown on the surface of the silicon substrate by adopting a magnetron sputtering method, a capacitor, an inductor and a coplanar waveguide with larger size in the bit circuit 3 are prepared by adopting an ultraviolet photoetching method and an etching method, and a superconducting conductive aluminum material is obtained at the periphery of the silicon substrate; then, preparing a Josephson junction structure by adopting an electron beam lithography method and an electron beam evaporation plating method to complete the setting of the bit circuit 3 on the surface of the negative film 1; then depositing the micro-convex points 4 on the surface of the superconducting conductive aluminum material in a vacuum in-situ manner;
(2) The surface of the silicon top sheet is provided with electrodes:
(3) The silicon bottom sheet and the silicon top sheet are connected through flip-chip bonding of the micro-bumps 4 to form a structure with electrodes right above the bit circuit 3;
the step (2) of arranging the grid electrode on the surface of the silicon top sheet comprises the following steps:
(a) Growing a first superconducting material film on the surface of the silicon top sheet by adopting a magnetron sputtering method, then processing the first superconducting material film by adopting an ultraviolet lithography method and an etching method, preparing an electrode extension area and pad areas at two ends of an electrode, and then preparing a grid inner electrode 7 positioned right above a bit circuit 3 by adopting an electron beam lithography method and an etching method;
(b) Forming a dielectric layer 9 on the top plate 2 and the surfaces of the grid inner electrodes 7 by adopting a magnetron sputtering method, growing a second superconducting material film on the surface of the dielectric layer 9, processing the second superconducting material film by adopting an ultraviolet lithography method and an etching method, preparing an electrode extension area and pad areas at two ends of an electrode, and preparing a grid outer electrode 8 positioned above the bit circuit 3 by adopting an electron beam lithography method and an etching method; the dielectric layer 9 is a silicon nitride dielectric layer 9;
(c) And removing the redundant dielectric layer 9 by adopting an ultraviolet lithography method, an electron beam lithography method and an etching method to expose the grid inner electrode 7 and the metal contact 81 on the periphery of the top plate.
When the measuring device provided by the embodiment is applied, an operator can apply voltages to different areas of the grid electrode, so that electric fields are generated at different positions on the surface of the bit circuit 3, the electric field regulation and control on the surface distribution of the two-level defect are realized, and the measurement of the surface distribution of the two-level defect is realized.
Example 5
The embodiment provides a measuring device for surface distribution of two-level defects, which comprises an electric field generating device and a surface defect measuring structure; the surface defect measuring structure comprises a bottom sheet 1 and a top sheet 2; the bottom plate 1 is a sapphire bottom plate, and the top plate 2 is a sapphire top plate;
the top sheet 2 is provided with electrodes; the electrode is a grid electrode;
the negative film 1 is provided with a bit circuit 3; the bit circuit 3 is formed by a superconducting material, and the superconducting material is tantalum;
the bit circuit 3 has a Josephson junction structure, the bottom sheet 1 and the top sheet 2 are connected by flip-chip bonding through micro-bumps 4, and a structure with electrodes right above the bit circuit 3 is formed; the micro-bumps 4 are made of indium.
The electric field generating device is connected with the grid electrode to realize electric field regulation and control on the surface distribution of the two-level defects.
The preparation method of the measuring device in the embodiment comprises the following steps:
(1) A superconducting film is grown on the surface of the sapphire substrate by adopting a magnetron sputtering method, a capacitor, an inductor and a coplanar waveguide with larger size in the bit circuit 3 are prepared by adopting an ultraviolet lithography method and an etching method, and a superconducting conduction tantalum material is obtained at the periphery of the sapphire substrate; then, preparing a Josephson junction structure by adopting an electron beam lithography method and an electron beam evaporation plating method to complete the setting of the bit circuit 3 on the surface of the negative film 1; then depositing the micro-convex points 4 on the surface of the superconducting conductive tantalum material in a vacuum in-situ manner;
(2) The surface of the sapphire top sheet is provided with electrodes:
(3) The sapphire bottom plate and the sapphire top plate are connected through flip-chip welding of the micro-bumps 4 to form a structure with electrodes right above the bit circuit 3;
the step (2) of arranging the grid electrode on the surface of the sapphire top sheet comprises the following steps:
(a) Growing a first superconducting material film on the surface of the sapphire top sheet by adopting a magnetron sputtering method, then processing the first superconducting material film by adopting an ultraviolet lithography method and an etching method to prepare an electrode extension area and pad areas at two ends of an electrode, and then preparing a grid inner electrode 7 positioned right above a bit circuit 3 by adopting an electron beam lithography method and an etching method;
(b) Forming a dielectric layer 9 on the top plate 2 and the surfaces of the grid inner electrodes 7 by adopting a magnetron sputtering method, growing a second superconducting material film on the surface of the dielectric layer 9, then processing the second superconducting material film by adopting an ultraviolet lithography method and an etching method, preparing an electrode extension area and pad areas at two ends of the electrode, and then preparing grid outer electrodes 8 positioned above the bit circuit 3 by adopting an electron beam lithography method and an etching method; the dielectric layer 9 is a silicon oxide dielectric layer 9;
(c) And removing the redundant dielectric layer 9 by adopting an ultraviolet lithography method, an electron beam lithography method and an etching method to expose the grid inner electrode 7 and the metal contact 81 on the periphery of the top plate.
When the measuring device provided by the embodiment is applied, an operator can apply voltages to different areas of the grid electrode, so that electric fields are generated at different positions on the surface of the bit circuit 3, the electric field regulation and control on the surface distribution of the two-level defect are realized, and the measurement of the surface distribution of the two-level defect is realized.
In summary, the measuring apparatus provided by the present invention can realize the generation of electric fields at different positions on the surface of the bit circuit by forming the grating electrode or the grid electrode directly above the bit circuit and using the electric field generating apparatus, thereby realizing the electric field regulation and control of the surface distribution of the two-level defect, and realizing the measurement of the surface distribution of the two-level defect.
The above description is only for the specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and it should be understood by those skilled in the art that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are within the protection scope and the disclosure of the present invention.
Claims (10)
1. The device for measuring the surface distribution of the two-level defects is characterized by comprising an electric field generating device and a surface defect measuring structure;
the surface defect measuring structure comprises a bottom sheet and a top sheet;
the top sheet is provided with an electrode; the electrodes comprise grating electrodes or grid electrodes;
the negative film is provided with a bit circuit;
the bottom sheet and the top sheet are connected through micro-convex point flip-chip welding to form a structure with an electrode right above the bit circuit;
the electric field generating device is connected with the electrodes to realize electric field regulation and control on the surface distribution of the two-level defects.
2. The measurement device of claim 1, wherein the bottom piece and the top piece each independently comprise a silicon bottom piece or a sapphire bottom piece.
3. The measurement device of claim 1, wherein the bit circuit is formed from a superconducting material;
the grating electrode or the grid electrode is formed of a superconducting material.
4. A measuring device as claimed in claim 1, wherein a barrier layer is provided between the microprotrusions and the backing sheet.
5. The measurement device of claim 1, wherein the grid electrode comprises an inner grid electrode and an outer grid electrode;
the grid inner electrode and the grid outer electrode are insulated through a dielectric layer.
6. A method for manufacturing a measuring device according to any of claims 1-5, characterized in that the method comprises the steps of:
(1) Preparing a bit circuit on the surface of the negative film;
(2) Arranging an electrode on the surface of the top sheet;
(3) The bottom sheet and the top sheet are connected through flip-chip bonding of the micro-bumps to form a structure with electrodes right above the bit circuit;
the step (1) and the step (2) are not in sequence.
7. The method of claim 6, wherein the step (1) of preparing the bit circuit on the surface of the negative film comprises: growing a superconducting material film on the surface of the negative film, and then forming a bit circuit;
the micro convex points are arranged on the top sheet and/or the bottom sheet.
8. The method for preparing a nonwoven fabric according to claim 6 or 7, wherein the step (2) of providing an electrode on the surface of the top sheet comprises: a film of superconducting material is grown on the surface of the top sheet, and then a grating electrode is formed.
9. The method for preparing a nonwoven fabric according to claim 6 or 7, wherein the step (2) of providing an electrode on the surface of the top sheet comprises:
at least 1 layer of grid electrode is grown on the surface of the top sheet.
10. The method of claim 6, comprising the steps of:
(1) Growing a superconducting material film on the surface of the negative film, and then forming a bit circuit;
(2) The surface of the top sheet is provided with electrodes:
(3) The bottom sheet and the top sheet are connected through flip-chip bonding of the micro-bumps to form a structure with electrodes right above the bit circuit;
the step (1) and the step (2) are not sequenced;
the step (2) of disposing an electrode on the surface of the top sheet includes:
growing a superconducting material film on the surface of the top sheet, and then forming a grating electrode;
or the like, or, alternatively,
at least 1 layer of grid electrode is grown on the surface of the top sheet.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108805293A (en) * | 2018-06-26 | 2018-11-13 | 清华大学 | The more bit control systems and method of based superconductive quantum calculation |
| CN110646503A (en) * | 2019-09-29 | 2020-01-03 | 中国科学院苏州纳米技术与纳米仿生研究所 | Method and device for measuring spatial distribution of two-level defects |
| CN111108687A (en) * | 2017-10-19 | 2020-05-05 | 国际商业机器公司 | Capacitive-shunted asymmetric DC SQUID for quantization readout and reset |
| CN217181558U (en) * | 2022-03-11 | 2022-08-12 | 合肥本源量子计算科技有限责任公司 | Superconducting circuit, quantum chip and quantum computer |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111108687A (en) * | 2017-10-19 | 2020-05-05 | 国际商业机器公司 | Capacitive-shunted asymmetric DC SQUID for quantization readout and reset |
| CN108805293A (en) * | 2018-06-26 | 2018-11-13 | 清华大学 | The more bit control systems and method of based superconductive quantum calculation |
| CN110646503A (en) * | 2019-09-29 | 2020-01-03 | 中国科学院苏州纳米技术与纳米仿生研究所 | Method and device for measuring spatial distribution of two-level defects |
| CN217181558U (en) * | 2022-03-11 | 2022-08-12 | 合肥本源量子计算科技有限责任公司 | Superconducting circuit, quantum chip and quantum computer |
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