CN211789023U

CN211789023U - Quantum chip three-dimensional structure

Info

Publication number: CN211789023U
Application number: CN202020277705.9U
Authority: CN
Inventors: 李海欧; 马荣龙; 张鑫; 曹刚; 郭光灿; 郭国平
Original assignee: University of Science and Technology of China USTC
Current assignee: University of Science and Technology of China USTC
Priority date: 2020-03-09
Filing date: 2020-03-09
Publication date: 2020-10-27
Anticipated expiration: 2030-03-09

Abstract

The application discloses quantum chip spatial structure, this spatial structure provide a new three-dimensional preparation and packaging structure, solved the electrode of quantum dot arrange the difficulty on the two-dimensional plane and the electrode of quantum dot arrange the required planar area too big problem, reduced quantum chip spatial structure's cost. In addition, the coupling between the quantum dots of the three-dimensional structure is regulated and controlled by the first communication structure and the second communication structure, the purposes of full electric control and independent adjustment of all parameters are achieved, the state of the quantum bits is read by the quantum chip three-dimensional structure through an RF (radio Frequency) measuring circuit, the quantum dots for signal detection do not need to be manufactured, the number of the quantum dots is saved, and the quantum dot structure is optimized. Furthermore, the three-dimensional structure is coupled with the quantum dots by using the superconducting resonant cavity layer, so that the problem of inextricable arrangement caused by the increase of the number of electrodes when the quantum dots are expanded is solved.

Description

Quantum chip three-dimensional structure

Technical Field

The application relates to the technical field of quanta, more specifically to a quantum chip three-dimensional structure.

Background

Quantum computers (Quantum computers) are a class of physical devices that perform high-speed mathematical and logical operations, store, and process Quantum information following Quantum mechanical laws. When a device processes and calculates quantum information and runs quantum algorithms, the device is a quantum computer.

Quantum computers are considered to be the inevitable product of the aftermolarity era and are considered to have great potential in cryptography, big data, scientific simulation, machine learning, and artificial intelligence. The heart of a quantum computer is a quantum processor, also known as a quantum chip. The superposition state principle following quantum mechanics is the basis for constructing the quantum bit, and the grid electric control quantum dot based on the semiconductor is a feasible scheme for constructing the quantum bit and further constructing a semiconductor quantum chip to realize the quantum computer chip. There are three basic types of semiconductor qubit cells: different rotation directions of electron spins, two different position states of a single electron charge, or a hybrid quantum state of charge and spin, etc.

The preparation process of the semiconductor grid electric control quantum dot is completely compatible with the traditional silicon integrated circuit processing and manufacturing process, can be accurately controlled in parameter design and optimization of devices and processing and preparation of the devices, has better expandability and integration, and is considered to be one of the most promising schemes for realizing the quantum computer. The semiconductor quantum chip of the traditional semiconductor grid electric control quantum dot structure has less quantum bit number and smaller volume, and can integrate electrodes, microwave circuits and charge detection on the surface of a semiconductor substrate, which is called as a two-dimensional structure.

However, as the research on semiconductor qubits goes deep and the requirements for constructing semiconductor quantum computers are met, the number of required qubits is gradually increased, which specifically reflects that the number of electrodes of the semiconductor qubits is increased and the number of corresponding charge detectors is increased, which causes the problems of serious crosstalk between lines, poor arrangement of electrode leads, and the like, and further limits the properties of the qubits.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, the application provides a quantum chip three-dimensional structure to solve the problem that the electrodes are difficult to arrange on a two-dimensional plane and block the number expansion of quantum dots.

In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:

a quantum chip three-dimensional structure, comprising: a first stereo structure and a second stereo structure; wherein the content of the first and second substances,

the first three-dimensional structure comprises a quantum dot layer, a first insulating layer and a first communication structure which are sequentially stacked, wherein,

the quantum dot layer comprises a plurality of quantum dots arranged in an array;

the first insulating layer is used for isolating the quantum dot layer from the first communication structure;

the first communication structure is located on the first insulating layer, part of the first communication structure is connected with the quantum dot layer, and is used for transmitting the received first direct-current voltage, second direct-current voltage and first high-frequency microwave signals to the quantum dot layer, forming a first regulating electric field by using the first direct-current voltage, forming a second regulating electric field by using the second direct-current voltage, so as to control the state of quantum bits of quantum dots in the quantum dot layer by using the first high-frequency microwave signals, controlling the coupling strength among the quantum dots by using the first regulating electric field, and controlling the number of carriers in the quantum dots by using the second regulating electric field; and an RF measurement circuit coupled to the RF measurement circuit to cause the RF measurement circuit to transmit a first probe signal to the quantum dot layer via the first communication structure and to cause the RF measurement circuit to determine a state of a quantum bit in the quantum dot layer based on the reflected first probe signal;

the second three-dimensional structure comprises a superconducting resonant cavity layer and a second communication structure which are sequentially stacked, wherein,

the second communication structure is connected with the quantum dot layer and the superconducting resonant cavity layer, and is used for realizing the coupling of quantum dots in the superconducting resonant cavity layer and the quantum dot layer, and transmitting a third direct-current voltage provided by the superconducting resonant cavity layer to the quantum dot layer, so that a third regulating electric field is formed by using the third direct-current voltage, and the third regulating electric field, the first regulating electric field and the second regulating electric field are bound together to form quantum dots;

the superconducting resonant cavity layer is further used for receiving a second high-frequency microwave signal so as to read the state of the quantum bit in the quantum dot layer by using the second high-frequency microwave signal.

Optionally, the quantum dot layer includes a central region and an edge region surrounding the central region;

the edge region also comprises a plurality of through silicon vias and a plurality of ion implantation regions; the plurality of through silicon vias are distributed at four end positions of the edge area, and the plurality of ion implantation areas are distributed on four edges of the edge area;

the multiple quantum dots arranged in an array are located in the central region, an adjustable coupling region is arranged between every two adjacent quantum dots, the quantum dots adjacent to the ion injection region in the multiple quantum dots are first-class quantum dots, the quantum dots adjacent to the through silicon via are third-class quantum dots, and the other quantum dots are second-class quantum dots.

Optionally, the quantum dot layer further includes: a plurality of micro-magnets;

the micro-magnets are distributed in gaps among the quantum dots, in gaps among the through silicon vias, or in gaps among the ion implantation regions.

Optionally, the first communication structure includes: a first communication line layer and a second communication line layer; wherein the content of the first and second substances,

the first communication line layer is connected with the adjustable coupling area and used for transmitting the received first direct-current voltage to the adjustable coupling area and forming a first regulating electric field by using the first direct-current voltage so as to regulate the coupling strength between the quantum dots by using the first regulating electric field; and an RF measurement circuit coupled to the RF measurement circuit to cause the RF measurement circuit to transmit a first probe signal to the quantum dot layer via the first communication structure and to cause the RF measurement circuit to determine a state of a quantum bit in the quantum dot layer based on the reflected first probe signal;

the second communication line layer is connected with the quantum dot layer and used for transmitting the received second direct-current voltage and the first high-frequency microwave signal to the quantum dot layer and forming a second regulating electric field by using the second direct-current voltage so as to control the state of quantum bits in the quantum dot layer by using the first high-frequency microwave signal and control the number of carriers in the quantum dots by using the second regulating electric field.

Optionally, the first communication line layer includes a first communication line layer a and a first communication line layer B; wherein the content of the first and second substances,

the first communication line layer a includes: the quantum dot layer is arranged on the surface of the substrate, the quantum dot layer is arranged on the quantum dot layer, the quantum;

the first communication line layer B includes: the quantum dot layer is arranged on the surface of the substrate, the quantum dot layer is arranged on the quantum dot layer, the quantum dot;

the first communication line layer A and the first communication line layer B are used for transmitting the received first direct current voltage to the quantum dot layer and forming a first regulating electric field by using the first direct current voltage so as to regulate the coupling strength between the quantum dots by using the first regulating electric field; the RF measurement circuit is also used for being connected with the RF measurement circuit so as to enable the RF measurement circuit to transmit a first detection signal to the quantum dot layer through the first communication line layer and enable the RF measurement circuit to judge the state of the quantum bit in the quantum dot layer according to the reflected first detection signal;

the first direction is perpendicular to the second direction.

Optionally, the second communication line layer includes:

the third surface lead is parallel to the plane where the quantum dot layer is located and used for leading out the third vertical electrode, one end of the third vertical electrode is connected with the third surface lead, the other end of the third vertical electrode is connected with the quantum dot, the connecting end of the third surface lead and the third vertical electrode is the third metal connecting point, and the connecting end of the third vertical electrode and the quantum dot layer is the third cut-off point.

Optionally, the second communication structure includes: a third communication line and a fourth communication line;

the third communication line comprises a quantum dot connecting electrode, a superconducting resonant cavity connecting electrode and a metal connecting electrode;

the quantum dot connecting electrode comprises a first horizontal part and a first vertical part, the first horizontal part is positioned on the surface of the first insulating layer, the first vertical part penetrates through the quantum dot layer through the through silicon via, one end of the first vertical part is connected with the first horizontal part, and the other end of the first vertical part is connected with the metal connecting electrode;

the superconducting resonant cavity connecting electrode comprises a second horizontal part and a second vertical part, one end of the second horizontal part is connected with the metal connecting electrode, and the other end of the second horizontal part is connected with the second vertical part; the second vertical part penetrates through a second insulating layer of the superconducting resonant cavity layer, one end, far away from the second horizontal part, of the second vertical part is connected with the superconducting resonant cavity layer, and the connecting end of the second vertical part and the superconducting resonant cavity layer is a fourth cut-off point;

the fourth communication circuit comprises a first connecting electrode and a second connecting electrode, wherein one end of the first connecting electrode is connected with the signal input plate of the superconducting resonant cavity layer, the other end of the first connecting electrode is used for receiving the second high-frequency microwave signal, and the connecting end of the first connecting electrode and the signal input plate is a fifth cut-off point; one end of the second connection electrode is connected with the direct current electrode of the superconducting resonant cavity layer, and the other end of the second connection electrode is used for receiving the third direct current voltage.

Optionally, the superconducting resonant cavity layer includes: a plurality of superconducting resonant cavities;

the superconducting resonant cavity comprises: the second insulating layer, the central conducting strip line, the direct current electrode, the metal support, the coupling electrode and the two signal input plates; wherein the content of the first and second substances,

two ends of the central conducting strip line are respectively connected with the two signal input plates, a voltage node of the superconducting resonant cavity leads out the coupling electrode, and the coupling electrode is connected with the third type of quantum dots through the third communication line;

the direct current electrode is used for receiving the third direct current voltage, the third direct current voltage is applied to the third type of quantum dots through the coupling electrode to form a third regulating electric field, and the third regulating electric field, the first regulating electric field and the second regulating electric field are bound together to form the quantum dots.

The signal input board is used for receiving the second high-frequency microwave signal;

the metal support is used for supporting the upper layer structure;

the second insulating layer is used for bearing the fourth communication line.

It can be seen from the above technical scheme that the embodiment of the application provides a quantum chip three-dimensional structure, wherein, the quantum chip three-dimensional structure is composed of a superconducting resonant cavity layer, a second communication structure, a quantum dot layer, a first insulating layer and a first communication structure which are sequentially stacked, wherein the first communication structure is used as an electrode of a quantum dot in the quantum dot layer, and the electrodes of the quantum dot which are two-dimensionally arranged are arranged in a three-dimensional structure, so that the problem that the electrodes of the quantum dot are difficult to arrange on a two-dimensional plane is solved, the problem that the plane area required by the arrangement of the electrodes of the quantum dot is too large is avoided, and the cost of the quantum chip three-dimensional structure is reduced.

In addition, the coupling between the quantum dots of the quantum chip three-dimensional structure is regulated and controlled by the first communication structure and the second communication structure, the purposes of full electric control and independent adjustment of all parameters are achieved, the quantum chip three-dimensional structure reads the state of the quantum bits in the quantum dot layer through the RF measuring circuit, the quantum dots for signal detection do not need to be manufactured in the quantum dot layer, the number of the quantum dots is saved, and the quantum dot structure is optimized.

Furthermore, the manufacturing and packaging method of the quantum chip three-dimensional structure uses the superconducting resonant cavity to be coupled with the quantum dots, and the discrete quantum dot layers are connected, so that different quantum dot layers form a quantum dot array structure integrally, and the problem of inextricable arrangement caused by the increase of the number of electrodes when the quantum dots are expanded is solved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic diagram of a quantum chip three-dimensional structure according to an embodiment of the present application;

fig. 2 is a schematic top view of a quantum dot layer according to an embodiment of the present disclosure;

fig. 3 is a schematic top view of a quantum dot layer according to another embodiment of the present application;

fig. 4 is a schematic top view of a quantum dot layer according to yet another embodiment of the present application;

fig. 5 is a schematic diagram illustrating a connection relationship between a first communication structure and the quantum dot layer according to an embodiment of the present application;

fig. 6 is a schematic top view of surface leads of a first communication line layer and a second communication line layer according to an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating a top view of a superconducting resonant cavity layer according to an embodiment of the present application;

fig. 8 is a schematic cross-sectional view of the second communication structure according to an embodiment of the present application;

fig. 9 is a schematic perspective view of a superconducting resonant cavity, a third communication line, a fourth communication line, and a quantum dot layer according to an embodiment of the present application;

fig. 10 is a schematic plan view of an encapsulation structure of a superconducting resonant cavity and a quantum dot layer according to an embodiment of the present application;

FIG. 11 is an enlarged schematic view of the dashed box of FIG. 10;

FIG. 12 is a schematic cross-sectional view of a quantum chip according to an embodiment of the present disclosure;

fig. 13-23 are manufacturing processes of a quantum chip three-dimensional structure according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The embodiment of the application provides a quantum chip three-dimensional structure, as shown in fig. 1, including: the superconducting resonant cavity layer 600, the second communication structure 500, the quantum dot layer 100, the first insulating layer 110 and the first communication structure 200A are sequentially stacked; wherein the content of the first and second substances,

the quantum dot layer 100, the first insulating layer 110, and the first communication structure 200A are sequentially stacked to constitute the first three-dimensional structure;

the superconducting resonant cavity layer 600 and the second communication structure 500 are sequentially stacked to form the second three-dimensional structure;

the quantum dot layer 100 includes a plurality of quantum dots arranged in an array;

the first insulating layer 110 is used to isolate the quantum dot layer 100 from the first communication structure 200A;

the first communication structure 200A is located on the first insulating layer 110, and is partially connected to the quantum dot layer 100, and configured to transmit the received first dc voltage, second dc voltage, and first high-frequency microwave signal to the quantum dot layer 100, form a first control electric field using the first dc voltage, form a second control electric field using the second dc voltage, control a state of a quantum bit of a quantum dot in the quantum dot layer 100 using the first high-frequency microwave signal, control a coupling strength between the quantum dots using the first control electric field, and control a number of carriers in the quantum dot using the second control electric field; and for connecting an RF measurement circuit to cause the RF measurement circuit to transmit a first probe signal to the quantum dot layer 100 through the first communication structure 200A and to cause the RF measurement circuit to determine the state of a quantum bit in the quantum dot layer 100 from the reflected first probe signal;

the second communication structure 500 is connected to the quantum dot layer 100 and the superconducting resonant cavity layer 600, and is configured to implement coupling between the superconducting resonant cavity layer 600 and the quantum dots in the quantum dot layer 100, and transmit a third dc voltage provided by the superconducting resonant cavity layer 600 to the quantum dot layer 100, so as to form a third control electric field by using the third dc voltage, and form quantum dots by using the third control electric field and the first control electric field and the second control electric field together through confinement;

the superconducting resonant cavity layer 600 is further configured to receive a second high-frequency microwave signal, so as to read the state of the quantum bit in the quantum dot layer 100 by using the second high-frequency microwave signal.

In this embodiment, the fact that the superconducting resonant cavity layer 600, the second communication structure 500, the quantum dot layer 100, the first insulating layer 110, and the first communication structure 200A are stacked means that main portions or main portions of the superconducting resonant cavity layer 600, the second communication structure 500, the quantum dot layer 100, the first insulating layer 110, and the first communication structure 200A are located in different layers, and when a plane where the quantum dot layer 100 is located is referred to as a horizontal plane, the main portions or main portions of the second communication structure 500 and the first communication structure 200A are portions excluding other layers which are vertically connected.

In addition, the first high-frequency microwave signal and the second high-frequency microwave signal both refer to microwave signals with frequencies in the GHz order, and specifically may be microwave signals with frequencies varying from several GHz to several tens of GHz, where a specific frequency of the first high-frequency microwave signal is related to the bit flip frequency, and a specific frequency of the second high-frequency microwave signal is related to the resonance frequency of the superconducting resonant cavity. In this embodiment, the quantum chip three-dimensional structure is formed by sequentially stacking the superconducting resonant cavity layer 600, the second communication structure 500, the quantum dot layer 100, the first insulating layer 110, and the first communication structure 200A, where the first communication structure 200A exists as an electrode of a quantum dot in the quantum dot layer 100, and the electrodes of the quantum dot arranged in two dimensions are arranged in a three-dimensional structure, so that a problem that a large number of electrodes occupy a large amount of planar area is avoided, a problem that the electrodes of the quantum dot are difficult to arrange on a two-dimensional plane is solved, a problem that the planar area required for the arrangement of the electrodes of the quantum dot is too large is avoided, and the cost of the quantum chip three-dimensional structure is reduced.

In addition, the coupling between the quantum dots of the quantum chip three-dimensional structure is regulated and controlled by the first communication structure 200A and the second communication structure 500, so that the purposes of full electric control and independent adjustment of all parameters are achieved, the quantum chip three-dimensional structure reads the state of the quantum bits in the quantum dot layer 100 through an RF (radio Frequency) measurement circuit, the quantum dots for signal detection do not need to be manufactured in the quantum dot layer 100, the number of the quantum dots is saved, and the quantum dot structure is optimized.

Furthermore, the method for manufacturing and packaging the quantum chip three-dimensional structure uses the superconducting resonant cavity layer 600 to couple with the quantum dots, and connects the discrete quantum dot layers, so that different quantum dot layers form a quantum dot array structure integrally, and the problem of incomplete arrangement caused by the increase of the number of electrodes when the quantum dots are expanded is solved.

Optionally, the first insulating layer 110 may be a silicon dioxide layer.

The following describes the structures of the layers of the quantum chip three-dimensional structure provided in the embodiments of the present application.

Referring to fig. 2, fig. 2 is a schematic top view structure diagram of a quantum dot layer 100 provided in an embodiment of the present application, in fig. 2, a plurality of quantum dots 102 are shown, and a black line connecting two quantum dots 102 adjacent to each other in a first direction indicates that the two quantum dots 102 are coupled to each other, and since the coupling between the quantum dots 102 is controlled by an electrode at the position, a region between the two quantum dots 102 coupled to each other is also referred to as a tunable coupling region 101;

similarly, the black line connecting two quantum dots 102 adjacent to each other in the second direction also indicates that the two quantum dots 102 are coupled to each other, and since the coupling between the quantum dots 102 is controlled by the electrode at the position, the region between the two quantum dots 102 coupled to each other is also referred to as the tunable coupling region 101.

In fig. 2, an arrow R1 indicates the first direction, an arrow R2 indicates the second direction, and the first direction is a transverse extending direction and the second direction is a longitudinal extending direction, taking fig. 2 as an example.

In fig. 2, the boundaries of the quantum dot layer 100 are not shown, nor is the number of quantum dots 102 limited.

Referring to fig. 3, the quantum dot layer 100 includes a central region and an edge region surrounding the central region;

the edge region further comprises a plurality of through silicon vias 104 and a plurality of ion implantation regions 103; the plurality of through silicon vias 104 are distributed at four end positions of the edge region, and the plurality of ion implantation regions 103 are distributed at four edges of the edge region;

the plurality of quantum dots 102 arranged in an array are located in the central region, an adjustable coupling region 101 is arranged between two adjacent quantum dots 102, quantum dots 102 adjacent to the ion implantation region 103 in the plurality of quantum dots 102 are first-type quantum dots 1021, quantum dots 102 adjacent to the through-silicon-via 104 are third-type quantum dots 1023, and the other quantum dots 102 are second-type quantum dots 1022.

In fig. 3, the quantum dots 102 are approximately circular with a diameter of 50nm, and the distance between two adjacent quantum dots 102 in the first and second directions is about 50 nm. The quantum dots 102 in the quantum dot layer 100 are mainly classified into three types, that is, the quantum dots 102 adjacent to the ion implantation region 103 are referred to as first type quantum dots 1021, the quantum dots 102 adjacent to the through-silicon via 104 are referred to as third type quantum dots 1023, and the other quantum dots 102 located in the middle (i.e., the quantum dots 102 around which the quantum dots 102 are located) are referred to as second type quantum dots 1022.

The ion implantation region 103 is formed by implanting N-type or P-type ions into a shallow substrate layer by a physical bombardment method to provide carriers (such as electrons or holes) for the quantum dots 102, a black line between the quantum dots 1021 and the first-type quantum dots represents the coupling between the quantum dots 1021 and the ion implantation region 103, the coupling is closed without additional carriers, and an ohmic contact electrode is formed inside the ion implantation region 103 to apply a second direct current voltage through the first communication structure to regulate the fermi level in the ion implantation region 103.

The through-silicon via 104 is formed by ion bombardment or chemical etching to form a small hole penetrating through the entire substrate at the edge of the silicon wafer for passing through the lead of the second communication structure.

On the basis of the above-described embodiment, in an embodiment of the present application, as shown in fig. 4, the quantum dot layer 100 further includes: a plurality of micro-magnets 111;

the micro-magnets 111 are distributed in the gaps between the quantum dots 102, the through silicon vias 104, or the ion implantation regions 103.

On the basis of the quantum dot layer 100 shown in fig. 3, a structure located on the first insulating layer is added: and the micro magnet 111 is obtained by photoetching or electron beam etching, and then a magnet material is evaporated on the surface of the first insulating layer to obtain the micro magnet 111. After the micro-magnet 111 is magnetized by applying an external magnetic field, the micro-magnet 111 can provide a stable magnetic field gradient at the quantum dot 102, and the control of the spin qubit is realized by changing the spin direction of the carrier in the quantum dot 102 under the combined action of the first high-frequency microwave previously applied to the first communication structure.

Next, a possible structure of the first communication structure is described, referring to fig. 5 and fig. 6, where fig. 5 is a schematic diagram of a specific electrode arrangement of the first communication structure, and fig. 6 is a schematic diagram of a top view of a surface lead of the first communication structure. The first communication structure includes: a first communication line layer and a second communication line layer 400; wherein the content of the first and second substances,

the first communication line layer is connected with the adjustable coupling area and used for transmitting the received first direct-current voltage to the quantum dot layer, forming a first regulating electric field by using the first direct-current voltage so as to regulate the coupling strength between the quantum dots by using the first regulating electric field, and connecting an RF measuring circuit so that the RF measuring circuit transmits a first detection signal to the quantum dot layer through the first communication structure and the RF measuring circuit judges the state of the quantum bit in the quantum dot layer according to the reflected first detection signal;

the second communication line layer 400 is connected to the quantum dot layer, and is configured to transmit the received second dc voltage and the first high-frequency microwave signal to the quantum dot layer, and form a second control electric field by using the second dc voltage, so as to control a state of a quantum bit of a quantum dot in the quantum dot layer by using the first high-frequency microwave signal, and control the number of carriers in the quantum dot by using the second control electric field.

Wherein the first communication line layer comprises a first communication line layer A200 and a first communication line layer B300; wherein the content of the first and second substances,

the first communication line a layer 200 includes: a first surface lead 201, a first metal connection point 202, a first vertical electrode 203 and a first cut-off point 204, wherein the first surface lead 201 is parallel to the plane of the quantum dot layer for leading out the first vertical electrode 203, one end of the first vertical electrode 203 is connected to the first surface lead 201, and the other end is connected to an adjustable coupling region extending in a first direction, the connection end of the first surface lead 201 and the first vertical electrode 203 is the first metal connection point 202, and the connection end of the first vertical electrode 203 and the adjustable coupling region is the first cut-off point 204;

the first communication line B layer 300 includes: a second surface lead 301, a second metal connection point 302, a second vertical electrode 303, and a second cut-off point 304, where the second surface lead 301 is parallel to the plane where the quantum dot layer is located, and is used to lead out the second vertical electrode 303, one end of the second vertical electrode 303 is connected to the second surface lead 301, and the other end of the second vertical electrode 303 is connected to an adjustable coupling region extending in a second direction, a connection end of the second surface lead 301 and the second vertical electrode 303 is the second metal connection point 302, and a connection end of the second vertical electrode 303 and the adjustable coupling region is the second cut-off point 304;

the first communication line a layer 200 and the first communication line B layer 300 are configured to transmit a received first direct current voltage to the quantum dot layer 100, and form a first control electric field using the first direct current voltage, so as to control the coupling strength between the quantum dots using the first control electric field; the RF measurement circuit is also used for being connected with the RF measurement circuit so as to enable the RF measurement circuit to transmit a first detection signal to the quantum dot layer through the first communication line layer and enable the RF measurement circuit to judge the state of the quantum bit in the quantum dot layer according to the reflected first detection signal;

the first direction is perpendicular to the second direction.

The second communication line layer 400 includes:

a third surface lead 401, a third metal connection point 402, a third vertical electrode 403, and a third cut-off point 404, where the third surface lead 401 is parallel to the plane where the quantum dot layer is located, and is used to lead out the third vertical electrode 403, one end of the third vertical electrode 403 is connected to the third surface lead 401, and the other end is connected to the quantum dot, a connection end between the third surface lead 401 and the third vertical electrode 403 is the third metal connection point 402, and a connection end between the third vertical electrode 403 and the quantum dot layer 100 is the third cut-off point 404.

Similarly, in fig. 5, the arrow R1 represents the first direction, the arrow R2 represents the second direction, and taking the example shown in fig. 5 as an example, the first direction is a transverse extending direction, and the second direction is a longitudinal extending direction, i.e., in fig. 5, the first direction and the second direction are perpendicular, but in other embodiments of the present application, the first direction and the second direction may not be perpendicular.

As the name implies, the communication line serves to establish a communication bridge between the quantum dot system and an external system. The first communication line layer mainly has two functions, the first function is to transmit a received first direct current voltage to the quantum dot layer, the first direct current voltage forms a first regulation and control electric field at the position of the first cut-off point 204 so as to utilize the first regulation and control electric field to regulate and control the coupling strength between the quantum dots, and the second function is to connect an RF measurement circuit and utilize the RF measurement circuit to measure the state of carriers in the quantum dots adjacent to the specific first communication line layer. The first communication line layer is formed of high frequency signal lines, which pass microwaves at frequencies generally less than 1 GHz.

The second communication line layer 400 also has two main functions, the first is to apply a second dc voltage for adjusting the level of energy in the quantum dots to control the number of carriers, the second is to receive a first high-frequency microwave signal, when the frequency of the first high-frequency microwave signal matches the corresponding frequency between zeeman splitting or other energy levels of carriers in the quantum dots, the state of the qubit can be controlled, the second communication line layer 400 is composed of high-frequency signal lines, and it is required that the attenuation of microwave signals passing at higher frequencies is reduced.

In the following description of the structure of the superconducting resonant cavity layer, referring to fig. 7, the superconducting resonant cavity layer 600 includes: a plurality of superconducting resonant cavities 601; optionally, the superconducting resonant cavity layer 600 may include four superconducting resonant cavities 601.

Each of the superconducting resonant cavities 601 includes: a second insulating layer (not shown in fig. 7), a central strip line 602, a dc electrode 603, a metal support 606, a coupling electrode 604, and two signal input boards 605; wherein the content of the first and second substances,

two ends of the central conducting strip line 602 are respectively connected to the two signal input boards 605, two coupling electrodes 604 are led out from a voltage node of the superconducting resonant cavity 601, and the coupling electrodes 604 are connected with the third type quantum dots 1023 through the third communication line;

the dc electrode 603 is configured to receive the third dc voltage, and the third dc voltage is applied to the third type of quantum dots 1023 through the coupling electrode 604, so as to implement regulation and control on the third type of quantum dots;

the signal input board 605 is used for receiving the second high-frequency microwave signal;

the metal support 606 is used for supporting the upper layer structure;

the second insulating layer is used for bearing the third communication line and the fourth communication line.

In fig. 7, the second insulating layer is not shown, and in the preparation process, after the second insulating layer is formed, a second communication structure may be fabricated on the second insulating layer.

For the second communication structure, referring to fig. 8, the second communication structure includes: a third communication line 510 and a fourth communication line 520;

the third communication line 510 includes a quantum dot connection electrode 511, a superconducting resonant cavity connection electrode 513, and a metal connection electrode 512;

the quantum dot connection electrode 511 comprises a first horizontal portion and a first vertical portion, the first horizontal portion is located on the surface of the first insulating layer 110, the first vertical portion penetrates through the quantum dot layer through the through-silicon via 104, one end of the first vertical portion is connected to the first horizontal portion, and the other end of the first vertical portion is connected to the metal connection electrode 512;

the superconducting resonant cavity connection electrode 513 includes a second horizontal portion and a second vertical portion, one end of the second horizontal portion is connected to the metal connection electrode 512, and the other end of the second horizontal portion is connected to the second vertical portion; the second vertical part penetrates through the second insulating layer 501 of the superconducting resonant cavity layer, one end of the second vertical part, which is far away from the second horizontal part, is connected with the superconducting resonant cavity coupling electrode 604, and the connection end of the second vertical part and the superconducting resonant cavity layer is a fourth cut-off point 514;

referring to fig. 8 and 9, the fourth communication line 520 includes a first connection electrode 521 and a second connection electrode 523, wherein one end of the first connection electrode 521 is connected to the signal input board 605 of the superconducting resonant cavity 601, the other end is used for receiving the second high-frequency microwave signal, and a connection end of the first connection electrode 521 and the signal input board is a fifth cut-off point 522; one end of the second connection electrode 523 is connected to the dc electrode 603 of the superconducting resonant cavity, and the other end is configured to receive the third dc voltage.

Referring to fig. 9, fig. 9 is a schematic perspective view of the superconducting resonant cavity, the third communication line, the fourth communication line and the quantum dot layer, and fig. 9 shows the structures of the third communication line and the fourth communication line and the positions of the third communication line and the fourth communication line connected to the superconducting resonant cavity layer and the quantum dot layer in detail.

The superconducting resonant cavity 601 is only partially illustrated, and no serial numbers of the superconducting resonant cavity 601 are shown.

Similarly, the quantum dot layer 100 only depicts the lattice of partial quantum dots 102, and the dotted lines represent the outward expansion of the quantum dots 102. As shown in fig. 9, the through-silicon vias 104 are located at two sides of the third type of quantum dots 1023 far away from the first type of quantum dots 1021, and are through holes vertically penetrating through the substrate, and the quantum dot connection electrodes 511 of the third communication circuit penetrate through the through-silicon vias 104, so as to realize the coupling between the superconducting resonant cavity 601 and the third type of quantum dots 1023. The remainder of quantum dot layer 100 is not shown. Since the size of the superconducting resonant cavity 601 is much larger than that of the quantum dot 102, in order to clearly show the relationship between the third communication line and the fourth communication line and the superconducting resonant cavity 601 and the quantum dot 102, the quantum dot portion is amplified in fig. 9.

The specific connection relationship among the quantum dot connection electrode 511, the superconducting resonant cavity connection electrode 513, the metal connection electrode 512 and the fourth cut-off point 514 in the third communication line 510 is shown in fig. 9.

The specific connection relationship among the fourth communication line 520, the first connection electrode 521, the cut-off point 522 of the first connection electrode 521, the second connection electrode 523, and the cut-off point 524 of the second connection electrode 523 is referred to fig. 9. The first connecting electrode 521 and the second connecting electrode 523 both extend to a position beyond the superconducting resonant cavity layer, and are wrapped by a box (or shell) with a metal wire during three-dimensional packaging, so that the fourth communication line 520 is connected with an external circuit.

Referring to fig. 10, fig. 10 is a schematic plan view of a three-dimensional structure package of a superconducting resonant cavity and a quantum chip, and fig. 10 schematically illustrates a top view of a structure including a quantum dot layer 100, a third communication line 510, a fourth communication line 520, and a superconducting resonant cavity layer 600, wherein some structures of the quantum dot layer 100, the third communication line 510, the fourth communication line 520, and the superconducting resonant cavity layer 600 are not shown due to coincidence in a top view angle.

The quantum dot layer 100 has a small area, and is located at the center of a square surrounded by four adjacent superconducting resonators 601, the third type of quantum dots 1023 at the four corners are connected to the coupling electrode 604 of the superconducting resonators 601 through a third communication line 510, and the third communication line only shows the superconducting resonator connection electrode 513.

The superconducting resonant cavity 601 is connected to an external circuit through a fourth communication line 520, and a second connection electrode 523 of the fourth communication line 520 is connected to a dc electrode 603 of the superconducting resonant cavity as shown in fig. 10.

Fig. 11 is an enlarged schematic view of a dashed box in fig. 10.

For a more clear description of the packaging structure of the quantum chip three-dimensional structure, referring to fig. 12, fig. 12 is a schematic cross-sectional view of the packaging of the quantum chip three-dimensional structure, and fig. 12 is a partial schematic view of a single superconducting resonant cavity packaged with two quantum dot layers, some parts of which are not shown due to angles.

Fig. 12 shows that the areas of the first communication line a layer 200, the second communication line B layer 300, and the second communication line layer 400 are gradually reduced, and they are covered by a "cover" with metal wires in a three-dimensional package to connect the first communication line a layer, the second communication line B layer, and the second communication line layer with an external circuit.

Correspondingly, the embodiment of the application also provides a manufacturing and packaging method of the quantum chip three-dimensional structure, which comprises the following steps:

providing a substrate;

respectively manufacturing a first three-dimensional structure and a second three-dimensional structure on the substrate,

the first three-dimensional structure is specifically a quantum dot layer, a first insulating layer and a first communication structure which are sequentially stacked on the substrate, wherein,

the first communication structure is located on the first insulating layer, part of the structure is connected with the quantum dot layer, and is used for transmitting the received first direct-current voltage, second direct-current voltage and first high-frequency microwave signals to the quantum dot layer, forming a first regulating electric field by using the first direct-current voltage, forming a second regulating electric field by using the second direct-current voltage, so as to control the state of quantum bits in the quantum dot layer by using the first high-frequency microwave signals, controlling the coupling strength between the quantum dots by using the first regulating electric field, and controlling the number of carriers in the quantum dots by using the second regulating electric field; and an RF measurement circuit coupled to the RF measurement circuit to cause the RF measurement circuit to transmit a first probe signal to the quantum dot layer via the first communication structure and to cause the RF measurement circuit to determine a state of a quantum bit in the quantum dot layer based on the reflected first probe signal;

the second three-dimensional structure is specifically a superconducting resonant cavity layer and a second communication structure which are sequentially stacked on the substrate, wherein,

Optionally, the substrate for the first three-dimensional structure is a substrate on which isotopically purified silicon is grown.

Optionally, the substrate for the second three-dimensional structure may be a silicon wafer substrate.

Optionally, the main steps of respectively manufacturing the first three-dimensional structure and the second three-dimensional structure on the substrate include: preparing an overlay exposure mark by extreme ultraviolet lithography, electron beam evaporation coating and metal stripping technologies; the extreme ultraviolet lithography and ion beam etching technology is used for preparing the through silicon via; preparing an ohmic contact electrode by ultraviolet photoetching, wet etching technology, electron beam evaporation coating and high-temperature annealing; preparing a micro-magnet structure by extreme ultraviolet lithography, electron beam evaporation coating and metal stripping technologies; manufacturing a first communication line layer, a second communication line layer, a third communication line and a fourth communication line by extreme ultraviolet lithography, an ion beam etching technology, an electron beam evaporation coating, a metal stripping technology and an atomic layer deposition technology; preparing the superconducting resonant cavity by magnetron sputtering coating, extreme ultraviolet lithography and reactive ion etching.

The detailed steps comprise: 1. a step of preparing the first stereostructure:

(1) preparing a mark for overlay exposure by using extreme ultraviolet lithography, electron beam evaporation coating and metal stripping technologies: cleaning the surface of a substrate on which high-quality silicon dioxide grows by using a standard sample cleaning process, and then obtaining metal marks for accurate electrode alignment in different steps at the designed position of the surface of a first insulating layer by using an extreme ultraviolet lithography technology, an electron beam evaporation coating technology and a metal stripping technology, wherein the coating metal is titanium-gold alloy (Ti/Au).

(2) The extreme ultraviolet lithography and ion beam etching technology is used for preparing the through silicon via: and (3) cleaning the surface of the substrate treated in the step (1) by using a standard cleaning process, and then manufacturing a through silicon via penetrating through the silicon wafer at a designed position by using an ultraviolet lithography technology and an ion beam etching technology.

(3) Preparing a third communication circuit quantum dot connecting electrode by using extreme ultraviolet lithography, electron beam evaporation coating and metal stripping technologies: cleaning the substrate processed in the steps (1) to (2) by using a standard sample cleaning process, using an extreme ultraviolet lithography technology, carrying out position calibration through the overlay mark manufactured in the step (1), and manufacturing a first horizontal part of a quantum dot connecting electrode of a third communication circuit at a designed position by using an electron beam evaporation coating technology and a metal stripping technology, wherein the material is titanium-palladium (Ti/Pd) alloy; and manufacturing a first vertical part electrode penetrating through the silicon through hole by using an oblique evaporation process again by using extreme ultraviolet lithography, electron beam evaporation coating and metal stripping technologies, and connecting the first vertical part electrode with the previously manufactured first horizontal part to jointly form a third communication circuit quantum dot connecting electrode.

(4) Preparing an ohmic contact electrode by ultraviolet photoetching, wet etching technology, electron beam evaporation coating and high-temperature annealing: cleaning the substrate processed in the steps (1) to (3) by using a standard sample cleaning process, carrying out overlay exposure by using the overlay mark manufactured in the step (1) by using an ultraviolet lithography technology, exposing an ohmic contact window with set parameters at the inner design position of each ion implantation area, and removing the first insulating layer in the window by using a wet etching technologyAnd evaporating a titanium-gold alloy (Ti/Au) into the ohmic contact window by using an electron beam evaporation coating technology, and obtaining an ohmic contact electrode by using a metal stripping technology. The substrate was again cleaned using the standard sample cleaning process and placed in an annealing furnace using a 15% hydrogen (H) gas₂) And 85% nitrogen (N)₂) The mixed gas is taken as a protective gas to anneal for 30 minutes at 400 ℃, so that the evaporated ohmic contact metal permeates into the ion implantation area, the contact resistance between the evaporated ohmic contact metal and implanted ions is reduced, and a high-quality ohmic contact electrode is formed.

(5) Preparing a micro-magnet structure by extreme ultraviolet lithography, electron beam evaporation coating and metal stripping technologies: and (2) cleaning the substrate by using a standard sample cleaning process, performing overlay exposure on the surface of the first insulating layer by using the overlay mark manufactured in the step (1) by using an extreme ultraviolet lithography technology to form a window for manufacturing the micro-magnet, evaporating cobalt (Co) metal into the window by using an electron beam evaporation coating technology, and obtaining the micro-magnet by using a metal stripping technology.

(6) Manufacturing a first communication line A by extreme ultraviolet lithography, an ion beam etching technology, an electron beam evaporation coating and a metal stripping technology, and: on the basis of the steps, cleaning the sample by using a standard sample cleaning process, carrying out overlay exposure by using the overlay mark manufactured in the step (1) by using an extreme ultraviolet lithography technology to expose a mask pattern of the vertical electrode of the first communication line and the second communication line, depositing a titanium palladium alloy (Ti/Pd) with a certain thickness by using an electron beam evaporation coating technology until the titanium palladium alloy reaches the design height of the first communication line layer, and then growing high-quality insulating layer aluminum oxide (Al) in the gap of the vertical electrode₂O₃) Or hafnium oxide (HfO)₂) The insulating function between the electrodes is realized, and the function of supporting the upper-layer electrode structure is also realized. And removing the insulating layer on the surface of the vertical electrode by extreme ultraviolet lithography and ion beam etching, and manufacturing a first metal contact by using an electron beam evaporation coating technology and a metal stripping technology. And manufacturing a first surface lead by using extreme ultraviolet lithography, electron beam evaporation coating and metal stripping technologies again, wherein the first surface lead, the first vertical electrode manufactured in the front and the first metal contact form a first communication line A together. The remaining second vertical electrode and the firstThe three vertical electrodes are used for the subsequent fabrication of the first communication line B and the second communication line.

(7) And (6) repeating the step (6), and manufacturing a first communication line B and a second communication line by using extreme ultraviolet lithography, an ion beam etching technology, an electron beam evaporation coating technology and a metal stripping technology to obtain the first three-dimensional structure.

2. A step of preparing the second stereostructure:

(8) preparing a superconducting resonant cavity by magnetron sputtering coating, extreme ultraviolet lithography and reactive ion etching: after a silicon dioxide layer with good quality is grown on the surface of a substrate used for manufacturing the superconducting resonant cavity, the substrate is cleaned by a standard sample cleaning process, a layer of niobium-titanium-nitrogen (NiTiN) superconducting thin film is manufactured on the surface of the whole substrate by a magnetron sputtering coating technology, the standard sample cleaning process is carried out again, the superconducting resonant cavity and a pattern used for alignment are exposed by an extreme ultraviolet lithography technology, the niobium-titanium-nitrogen (NiTiN) thin film in the pattern is removed by a reactive ion etching technology, and the superconducting resonant cavity and a mark used for the alignment technology are obtained.

(9) Manufacturing a fourth communication circuit by using an ultraviolet photoetching, ion beam etching technology, electron beam evaporation coating and metal stripping technology: on the basis of the superconducting resonant cavity sample, a standard sample cleaning process is used for cleaning the sample, then an extreme ultraviolet lithography technology is used, the overlay mark manufactured in the step (8) is used for overlay exposure, a mask pattern of the fourth communication line is exposed, and a titanium palladium alloy (Ti/Pd) is deposited by an electron beam evaporation coating technology and used for manufacturing the fourth communication line.

(10) Manufacturing a third communication line superconducting resonant cavity connecting electrode by using an extreme ultraviolet lithography, an ion beam etching technology, an electron beam evaporation coating technology and a metal stripping technology: cleaning the sample by using a standard sample cleaning process on the basis of the step (9), performing overlay exposure by using an overlay mark manufactured in the step (8) by using an extreme ultraviolet lithography technology to expose a mask pattern of a second vertical part of the third communication line superconducting resonant cavity connecting electrode, and depositing a titanium palladium alloy (Ti/Pd) with a certain thickness by using an electron beam evaporation coating technology and a metal stripping technology, wherein the thickness of the Ti/Pd alloy is determined by the third communication line superconducting resonant cavity connecting electrodeThe design position of the second horizontal portion of the connection electrode. Then growing high-quality insulating layer aluminum oxide (Al) in the gap of the vertical electrode₂O₃) Or hafnium oxide (HfO)₂) The insulating function between the electrodes is realized, and the function of supporting the upper-layer electrode structure is also realized. And removing the insulating layer on the surface of the second vertical part by extreme ultraviolet lithography and ion etching, and manufacturing the second horizontal part by using the extreme ultraviolet lithography, electron beam evaporation coating and metal stripping technology, wherein the metal material is titanium palladium alloy (Ti/Pd). And the second vertical part and the third vertical part form a third communication line superconducting resonant cavity connecting electrode together.

(11) Manufacturing a third communication circuit metal connecting electrode by using extreme ultraviolet lithography, electron beam evaporation coating and metal stripping technologies: and (3) cleaning the sample by using a standard sample cleaning process on the basis of the step (10), performing overlay exposure by using an overlay mark manufactured in the step (8) by using an extreme ultraviolet lithography technology to expose a mask pattern of a metal connecting electrode and a metal support of the third communication circuit, and manufacturing the metal connecting electrode by using an electron beam evaporation coating and metal stripping technology, wherein the metal material is titanium palladium alloy (Ti/Pd). And obtaining the second three-dimensional structure.

3. Packaging the first three-dimensional structure and the second three-dimensional structure to obtain the three-dimensional structure of the quantum chip:

(12) and (3) connecting the first three-dimensional structure manufactured in the steps (1) to (7) and the second three-dimensional structure manufactured in the steps (8) to (11) according to an upper-lower structure, wherein the connection rule is that a third communication circuit metal connecting electrode in the second three-dimensional structure and a first vertical part of a third communication circuit quantum dot connecting electrode in the first three-dimensional structure are connected to form a complete third communication circuit, and the first three-dimensional structure and the second three-dimensional structure are connected through a third communication circuit to form a quantum chip three-dimensional structure.

The standard sample cleaning process comprises the following steps: the samples were sequentially washed with Acetone (ACE), Trichloroethylene (TCE), Acetone (ACE), isopropyl alcohol (IPA), and deionized water (DI) for 5 minutes each, with ultrasonic washing for each reagent, and finally blown dry with high purity nitrogen.

The optimized sample cleaning process comprises the following steps: the samples were sequentially soaked with Acetone (ACE), Trichloroethylene (TCE), Acetone (ACE), isopropyl alcohol (IPA) and deionized water (DI) for 5 minutes each, and finally blown dry with high purity nitrogen (this step is not suitable for ultrasonic cleaning to prevent the quantum dot nano-sized electrodes from being damaged).

The metal stripping technology comprises the steps of soaking 1-methyl-2-pyrrolidone (NMP) at a constant temperature of 80 ℃, wherein a titanium-gold alloy (Ti/Au), a titanium-palladium alloy (Ti/Pd) and cobalt (Co) are soaked for 1.5 hours.

The ultraviolet photoetching technology used for the ohmic contact electrode selects AZ5214E as photoresist, baking for 90 seconds at 95 ℃, and using AZ 400K: 1:6 DI, 1 min development, fixation with deionized water (DI), 12 sec fixation; removing silicon dioxide in the photoetching window by using a wet etching process (using BOE solution) (determining etching time according to the thickness of silicon oxide, etching 10nm silicon oxide for 10s), then evaporating and coating titanium-gold alloy (Ti/Au) in the etching window by using electron beams, wherein the thicknesses of the titanium-gold alloy and the titanium-gold alloy are respectively 5nm and 45nm, wherein 5nm of titanium (Ti) is an adhesion layer, and cleaning by using a standard cleaning process after soaking 1-methyl-2-pyrrolidone (NMP) reagent for 1.5 hours in a constant-temperature 80 ℃ environment in the process of metal stripping.

Ion beam etching technology for removing aluminum oxide insulating layer (Al) above titanium palladium alloy (Ti/Pd) electrode₂O₃) So that the communication line electrodes manufactured twice are conducted into a whole. Specifically, argon (Ar) is used, the flow is controlled to be 10sccm, the accelerating voltage is 25V, and the etching speed is 180s to etch the aluminum oxide (Al) with the thickness of about 5nm₂O₃)。

The source used in atomic layer deposition techniques is determined by the material of the insulating layer being grown, usually alumina (Al)₂O₃) Pure water (H) is used for the insulating layer₂O) and Trimethylaluminum (TMA) at 250 ℃ using argon (Ar) as a carrier gas. The specific growth time is determined according to the thickness of the insulating layer, and 5nm of aluminum oxide (Al) is generally grown₂O₃) It took 0.5 hours.

A magnetron sputtering coating process used for a superconducting resonant cavity selects niobium-titanium alloy (NiTi) as a target material, a nitrogen source is provided by using a flow ratio of argon to nitrogen Ar, N2 of 6sccm to 10sccm, the temperature of a cavity is kept at 250 ℃, the pressure of the cavity is 0.5Pa, the coating time is 10s, and the coating thickness is 10 nm.

The reactive ion etching process for superconductive resonant cavity with CF₄When the etching gas is used, the flow is controlled to be 30sccm, the cavity pressure is about 5Pa, the etching power is 50W, the etching time is 90s, and the etching thickness is 10 nm.

Specifically, referring to fig. 13 to 23, the fabricating the first and second three-dimensional structures on the substrate respectively includes:

the step of fabricating the second three-dimensional structure comprises:

in fig. 13, a silicon wafer substrate 610 of good quality is prepared as the substrate, and its surface is oxidized to form a silicon dioxide insulating layer 620 of high quality as an insulating layer. A layer of superconducting metal film is grown on the surface of the first insulating layer by evaporation, then a corresponding mask pattern is manufactured by utilizing a photoresist and extreme ultraviolet lithography process or an electron beam and electron beam lithography process, and the superconducting metal film without the protection of the photoresist or the electron beam is removed by utilizing reactive ion etching, so that a superconducting resonant cavity 601 with good quality is obtained, as shown in fig. 14. When the superconducting resonant cavity chip and the semiconductor quantum computing chip are packaged, in order to prevent the third/fourth communication lines from being damaged by the extrusion in the packaging process, a plurality of metal pillars 606 are vapor-plated on the superconducting resonant cavity layer for supporting the first three-dimensional structure and protecting the second communication structure in the packaging process, as shown in fig. 15 and 16.

The step of preparing the first steric structure comprises:

in fig. 17 to 18, an isotope-purified silicon wafer is prepared, and a layer of good quality silicon dioxide (SiO) is grown on the surface of the isotope-purified silicon layer 121₂) An insulating layer 122, and ion implantation into the ion implantation region 103 is completed before the process. The TSV 104 is then fabricated by an euv lithography or electron beam lithography process and a reactive ion etching process, as shown in fig. 19. In FIG. 20, a third communication line quantum coupled to the superconducting resonant cavity 601 is fabricated by depositing a metal electrode by evaporationAnd the point connecting electrodes 511 are distributed on the front part of the semiconductor quantum computing chip and then are connected with the third communication circuit metal connecting electrodes 512 together to form a third communication circuit when finally packaging. After the third communication circuit coupled with the superconducting resonant cavity chip is manufactured, a quantum dot metal electrode structure and a lead layer structure packaged with an external circuit need to be prepared. In fig. 21, the first vertical electrode 203 of the first communication line a layer, the second vertical electrode 303 of the first communication line B layer, and the third vertical electrode 403 of the second communication line are repeatedly manufactured by the euv lithography or the e-beam lithography process and the metal evaporation method, wherein the position of the second vertical electrode 303 in the first communication line B layer is not marked because the second vertical electrode 303 of the first communication line B layer and the third vertical electrode 403 of the second communication line are overlapped in the cross-sectional view. When the electrode is grown to the surface lead layer 200 of the first communication line A layer, the metal connection point 202 of the first communication line A layer and the surface lead 201 of the first communication line A layer are manufactured, the electrode is guided to the edge of the lead layer 200 of the first communication line A layer to be convenient for being packaged with an external circuit, and then the remaining parts of the first communication line B and the second communication line are continuously manufactured. This procedure is repeated to obtain the structure of the wiring layer 300 of the B layer of the first communication line as shown in fig. 22 and the structure of the wiring layer 400 of the second communication line as shown in fig. 23.

To sum up, the embodiment of the application provides a quantum chip spatial structure, wherein, quantum chip spatial structure comprises superconductive resonant cavity layer, second communication structure, quantum dot layer, first insulating layer and the first communication structure that stacks gradually the setting, wherein, first communication structure does the electrode of the quantum dot in the quantum dot layer exists, arranges the electrode of the quantum dot that the two-dimentional was arranged with three-dimensional structure's form, has solved the electrode of quantum dot and has arranged the problem of difficulty on two-dimensional plane, has avoided the electrode of quantum dot to arrange required planar area oversize problem, has reduced quantum chip spatial structure's cost.

Furthermore, the quantum chip three-dimensional structure couples the quantum dots by using the superconducting resonant cavity, and connects the discrete quantum dot layers, so that different quantum dot layers form a quantum dot array structure integrally, and the problem of incomplete arrangement caused by the increase of the number of electrodes when the quantum dots are expanded is solved.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A quantum chip three-dimensional structure is characterized by comprising: a first stereo structure and a second stereo structure; wherein the content of the first and second substances,

2. The quantum chip volume structure of claim 1, wherein the quantum dot layer comprises a central region and an edge region surrounding the central region;

3. The quantum chip volume structure of claim 2, wherein the quantum dot layer further comprises: a plurality of micro-magnets;

4. The quantum chip volumetric structure of claim 2, wherein the first communication structure comprises: a first communication line layer and a second communication line layer; wherein the content of the first and second substances,

5. The quantum chip three-dimensional structure according to claim 4, wherein the first communication line layer comprises a first communication line A layer and a first communication line B layer; wherein the content of the first and second substances,

the first direction is perpendicular to the second direction.

6. The quantum chip solid structure according to claim 5, wherein the second communication line layer comprises:

7. The quantum chip solid structure of claim 2, wherein the second communication structure comprises: a third communication line and a fourth communication line;

8. The quantum chip solid structure according to claim 7, wherein the superconducting resonant cavity layer comprises: a plurality of superconducting resonant cavities;

the direct current electrode is used for receiving the third direct current voltage, the third direct current voltage is applied to the third type of quantum dots through the coupling electrode to form a third regulating electric field, and the third regulating electric field, the first regulating electric field and the second regulating electric field are bound together to form the quantum dots;

the metal support is used for supporting the upper layer structure;

the second insulating layer is used for bearing the fourth communication line.