CN217181558U - Superconducting circuit, quantum chip and quantum computer - Google Patents
Superconducting circuit, quantum chip and quantum computer Download PDFInfo
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- CN217181558U CN217181558U CN202220555191.8U CN202220555191U CN217181558U CN 217181558 U CN217181558 U CN 217181558U CN 202220555191 U CN202220555191 U CN 202220555191U CN 217181558 U CN217181558 U CN 217181558U
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Abstract
The application provides a superconducting circuit, quantum chip and quantum computer, superconducting circuit includes qubit circuit, adjustable coupler circuit, first connecting circuit and second connecting circuit, wherein, adjustable coupler circuit sets up in two between the qubit circuit, respectively with two qubit circuit coupling is connected for adjust adjacent two interact intensity between the qubit circuit, first connecting circuit set up in the qubit circuit with between the adjustable coupler circuit, second connecting circuit, respectively with two the qubit circuit is connected. The superconducting circuit provided by the application considers the residual coupling between the quantum bits and the adjustable coupling, corrects the difference between the actually manufactured quantum chip and the theoretical circuit design, and improves the fidelity of the quantum bit gate.
Description
Technical Field
The application belongs to the technical field of quantum computing, and particularly relates to a superconducting circuit, a quantum chip and a quantum computer.
Background
Quantum computers are physical devices that perform high-speed mathematical and logical operations, store and process quantum information in compliance with the laws of quantum mechanics. The quantum computer is characterized by high running speed, strong information processing capability, wide application range and the like. Quantum computation has the advantage of solving speed in principle on the mathematical problems of large prime factorization, global search and the like. At present, different quantum systems have been established and simple quantum algorithms have been implemented, of which superconducting quantum computing is now the most promising quantum computing system.
In quantum computing systems, the most important is the qubit gate to achieve fidelity. The quantum chip includes a number of qubits and adjustable couplings between adjacent qubits, wherein the qubits and the adjustable couplings are each electronic devices having physical dimensions, which are determined by circuit design. However, in the prior art, when a circuit design is performed on a quantum chip integrated with multiple qubits, residual coupling between the qubits and adjustable coupling are not considered, so that the circuit design and the physical structure of the quantum chip are different, and the qubit parameters cannot be regulated to target parameters required by a target qubit gate in actual measurement of the quantum chip, thereby reducing the fidelity of the qubit gate. Therefore, how to optimize the circuit design of the quantum chip, correct the difference between the actually manufactured quantum chip and the theoretical circuit design, and improve the fidelity of the qubit gate is a problem that needs to be solved at present.
SUMMERY OF THE UTILITY MODEL
The application aims to provide a superconducting circuit, a quantum chip and a quantum computer, so as to solve the defects and shortcomings in the prior art, and the circuit design of the quantum chip can be optimized, so that the difference between the actually manufactured quantum chip and the theoretical circuit design can be corrected, and the fidelity of a quantum bit gate can be improved.
To achieve the above object, in a first aspect, the present application provides a superconducting circuit including:
a qubit circuit;
the adjustable coupler circuit is arranged between the two quantum bit circuits, is respectively coupled with the two quantum bit circuits, and is used for adjusting the interaction strength between the two adjacent quantum bit circuits;
a first connection circuit disposed between the qubit circuit and the adjustable coupler circuit;
and the second connecting circuits are respectively connected with the two quantum bit circuits.
Optionally, the qubit circuit and the adjustable coupler circuit have the same constituent elements.
Optionally, the qubit circuit includes a superconducting quantum interferometer, a first capacitor, a second capacitor, and a third capacitor;
a first pole of the first capacitor is connected with a first pole of the superconducting quantum interferometer, and a second pole of the first capacitor is connected with a second pole of the superconducting quantum interferometer;
the first pole of the second capacitor is connected with the first pole of the superconducting quantum interferometer, and the second pole of the second capacitor is connected with the ground;
the first pole of the third capacitor is connected with the second pole of the superconducting quantum interferometer, and the second pole of the third capacitor is connected with the ground.
Optionally, the second connection circuit includes a fourth capacitor and a fifth capacitor.
Optionally, the first pole and the second pole of the fourth capacitor are respectively connected to the first poles of the superconducting quantum interferometers in the two adjacent qubit circuits;
and the first pole and the second pole of the fifth capacitor are respectively connected with the second poles of the superconducting quantum interferometers in the two adjacent qubit circuits.
Optionally, the first connection circuit includes a sixth capacitor, a seventh capacitor, an eighth capacitor, and a ninth capacitor;
a first pole of the sixth capacitor is connected with a first pole of a quantum superconducting interferometer in the qubit circuit, and a second pole of the sixth capacitor is connected with a first pole of a quantum superconducting interferometer in the tunable coupler circuit;
a first pole of the seventh capacitor is connected with a first pole of a quantum superconducting interferometer in the qubit circuit, and a second pole of the seventh capacitor is connected with a second pole of the quantum superconducting interferometer in the tunable coupler circuit;
the first pole of the eighth capacitor is connected with the second pole of the quantum superconducting interferometer in the quantum bit circuit; a second pole of the eighth capacitor is connected with a first pole of a quantum superconducting interferometer in the adjustable coupler circuit;
the first pole of the ninth capacitor is connected with the second pole of the quantum superconducting interferometer in the qubit circuit, and the second pole of the ninth capacitor is connected with the second pole of the quantum superconducting interferometer in the tunable coupler circuit.
Optionally, the superconducting quantum interferometer comprises two josephson junctions in parallel.
Optionally, the apparatus further comprises a reading circuit, and the reading circuit is coupled to the qubit circuit.
In a second aspect, the present application provides a quantum chip having at least a superconducting circuit as described in the first aspect formed thereon.
In a third aspect, the present application provides a quantum computer, wherein the quantum computer is at least provided with the quantum chip of the second aspect and a measurement and control device connected with the quantum chip.
Compared with the prior art, the superconducting circuit, the quantum chip and the quantum computer have the following beneficial effects: the superconducting circuit comprises a qubit circuit, an adjustable coupler circuit, a first connecting circuit and a second connecting circuit, wherein the adjustable coupler circuit is arranged between the qubit circuits and is respectively coupled with the qubit circuits for adjusting the interaction strength between the adjacent two qubit circuits, the first connecting circuit is arranged between the qubit circuits and the adjustable coupler circuit, and the second connecting circuit is respectively connected with the qubit circuits. The superconducting circuit provided by the application considers the residual coupling between the quantum bits and the adjustable coupling, corrects the difference between the actually manufactured quantum chip and the theoretical circuit design, and improves the fidelity of the quantum bit gate.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a superconducting circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of another superconducting circuit according to an embodiment of the present application.
Detailed Description
The superconducting circuit, the quantum chip and the quantum computer proposed in the present application are further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present application.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
According to different physical systems adopted for constructing the qubits, the qubits include superconducting circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quanta, photons and the like in terms of physical implementation manners.
The superconducting circuit is the best solid quantum computation implementation method at present. Because the energy level structure of the superconducting circuit can be regulated and controlled by an external electromagnetic signal, the design customization controllability of the circuit is strong. Meanwhile, due to the existing mature integrated circuit process, the quantum chip designed based on the superconducting circuit also has incomparable expandability. However, when a circuit design is performed on a quantum chip integrated with multiple qubits, residual coupling between the qubits and the adjustable coupling are not considered, so that the difference exists between the circuit design and the physical structure of the quantum chip, and the parameter of the qubit cannot be regulated to a target parameter required by a target qubit gate in actual measurement of the quantum chip, thereby reducing the fidelity of the qubit gate. The core idea of the application is to provide a superconducting circuit, and when the superconducting circuit is designed, residual couplings among quantum bits and between the quantum bits and the adjustable couplings are equivalent to corresponding electronic elements, so that the difference between actually manufactured quantum chips and theoretical circuit design is corrected, and the fidelity of a quantum bit gate is improved.
To this end, the present embodiment provides a superconducting circuit, which includes a qubit, a tunable coupler circuit, a first connection circuit, and a second connection circuit, with reference to fig. 1. The adjustable coupler circuit is arranged between the two qubit circuits, is respectively coupled with the two qubit circuits, and is used for adjusting the interaction strength between the two adjacent qubit circuits; the first connection circuit is disposed between the qubit circuit and the adjustable coupler circuit; the second connection circuit is respectively connected with the two quantum bit circuits.
In the superconducting circuit design provided by this embodiment, in consideration of the residual coupling between the qubit and the tunable coupling, an equivalent electronic device is provided in the first connection circuit for correcting the residual coupling; meanwhile, in consideration of residual coupling between the two qubits, an equivalent electronic device is arranged in the second connection circuit and used for correcting the residual coupling so as to reduce the difference between the actually manufactured quantum chip and the theoretical circuit design and improve the fidelity of the qubit gate.
Illustratively, the qubit circuit and the adjustable coupler circuit have the same components and the same connection relationship among the components, but the qubit circuit and the adjustable coupler circuit have different functions implemented in the superconducting circuit.
Specifically, the qubit circuit comprises a superconducting quantum interferometer and a first capacitor C 1 A second capacitor C 2 And a third capacitor C 3 . Wherein the first capacitor C 1 Is connected to a first pole of the superconducting quantum interferometer, the first capacitance C 1 Is connected to a second pole of the superconducting quantum interferometer; the second capacitor C 2 Is connected to the first pole of the superconducting quantum interferometer, and the second capacitor C 2 The second pole of the first diode is connected to the ground; the third capacitor C 3 Is connected to the second pole of the superconducting quantum interferometer, and the third capacitor C 3 Is connected to ground. In particular, the superconducting quantum interferometer comprises two josephson junctions connected in parallel.
The above description corresponds to a detailed description of the qubit circuit located on the left side in fig. 1. As is apparent from the figure, the qubit circuit adjacent to the qubit circuit and located on the right side in fig. 1 includes a superconducting quantum interferometer and a first capacitor C 1 A second capacitor C 2 And a third capacitor C 3 (ii) a The adjustable coupler circuit positioned between the two quantum bit circuits comprises a superconducting quantum interferometer and a first capacitor C 1 A second capacitor C 2 And a third capacitor C 3 And the connection relationship between them is the same as above.
It can be seen that the qubit circuit and the adjustable coupler circuit in the superconducting circuit provided by this embodiment are both in a dual-island structure, that is, two ends of the josephson junction of the qubit circuit and the adjustable coupler circuit are not directly grounded, and noise and interference are reduced by capacitive coupling grounding.
Illustratively, the second connection circuit includes a fourth capacitor C 4 And a fifth capacitance C 5 . Specifically, the fourth capacitor C 4 The first pole and the second pole of the superconducting quantum interferometer are respectively connected with the first poles of the superconducting quantum interferometers in the two adjacent quantum bit circuits; the fifth capacitor C 5 Respectively connecting the second poles of the superconducting quantum interferometers in two adjacent qubit circuits.
Exemplarily, the first connection circuit comprises a sixth capacitor C 6 A seventh capacitor C 7 An eighth capacitor C 8 And a ninth capacitor C 9 . Wherein the sixth capacitor C 6 Is connected to the first pole of the quantum superconducting interferometer in the qubit circuit, and the sixth capacitor C 6 Is connected to a first pole of a quantum superconducting interferometer in the tunable coupler circuit; the seventh capacitor C 7 Is connected to the first pole of the quantum superconducting interferometer in the qubit circuit, and the seventh capacitor C 7 Is connected to a second pole of a quantum superconducting interferometer in the tunable coupler circuit; the eighth capacitor C 8 Is connected to a second pole of a quantum superconducting interferometer in the qubit circuit; the eighth capacitor C 8 Is connected to a first pole of a quantum superconducting interferometer in the tunable coupler circuit; the ninth capacitor C 9 Is connected to the second pole of the quantum superconducting interferometer in the qubit circuit, and the ninth capacitor C 9 Is connected to a second pole of a quantum superconducting interferometer in the tunable coupler circuit.
The above detailed description corresponds to the first connection circuit between the qubit circuit and the adjustable coupler circuit on the left side in fig. 1. In addition, as shown in the figure, the first connection circuit between the qubit circuit on the right in fig. 1 and the adjustable coupler circuit comprises a sixth capacitor C 6 And a seventh capacitor C 7 An eighth capacitor C 8 And a ninth capacitor C 9 And the connection relationship between them is the same as above. It is to be understood that the designations 1, 2, 3, 4, 5, 6 in the drawings all represent connecting nodes.
It should be noted that, in this embodiment, each of the first capacitor, the second capacitor, … …, and the ninth capacitor may be an equivalent capacitor formed by connecting a plurality of capacitor elements in series, in parallel, or by partially connecting the capacitor elements in series and partially connecting the capacitor elements in parallel, where the number and the electrical connection relationship of the capacitor elements may be determined as needed.
In this embodiment, the fourth capacitor and the fifth capacitor are arranged in the first connection circuit to represent spatial coupling between the qubits and the adjustable coupling, and the sixth capacitor, the seventh capacitor, the eighth capacitor and the ninth capacitor are arranged in the second connection circuit to represent spatial coupling between two qubits, so as to reduce a difference between an actually manufactured quantum chip and a theoretical circuit design, so that when the actually manufactured quantum chip is tested, a variation range of an effective coupling amount of two coupled qubits generated along with a frequency variation of an adjustable coupler frequency includes a coupling strength of 0 point (i.e. the two qubits do not interact with each other), thereby realizing that when the effective coupling between the qubits is required, the coupling amount between the qubits can be accurately controlled, and when the coupling between the qubits is not required, the elimination of the invalid coupling between qubits can be accomplished, thereby improving the fidelity of the single-qubit gate and the dual-qubit gate.
Illustratively, referring to fig. 2, the superconducting circuit further includes a reading circuit, and the reading circuit is coupled to the qubit circuit and configured to read the regulated quantum state of the qubit circuit. Specifically, the reading circuit comprises a tenth capacitor C with one pole grounded 10 And with said tenth capacitance C 10 An inductor connected in parallel.
Illustratively, the reading circuit and the qubit circuits are connected by capacitive coupling, and in this embodiment, one end of each qubit circuit is connected by a capacitor C qr Coupled to one end of one of the read circuits, and the other ends of the read circuits are coupled to a common read signal transmission line (Transitionline) electrically connected to each qubitAnd the reading circuit corresponding to the way acquires quantum state information. It is understood that the designations a, b, c, d, e, f, g in the drawings all represent connecting nodes.
In addition, the above reference symbols are C 1 All references merely denote the same element name and do not denote the same performance parameter, e.g., the first capacitor C in the qubit circuit in a test requirement 1 With a first capacitor C in the adjustable coupler circuit 1 All of which have different capacitance parameters.
Based on the same application concept, the present embodiment also provides a quantum chip on which at least the superconducting circuit as described above is formed.
Based on the same application concept, the present embodiment further provides a quantum computer, wherein the quantum computer is at least provided with the quantum chip and the measurement and control device connected with the quantum chip.
To sum up, the superconducting circuit, the quantum chip and the quantum computer provided by the application have the following advantages: the superconducting circuit comprises a qubit circuit, an adjustable coupler circuit, a first connecting circuit and a second connecting circuit, wherein the adjustable coupler circuit is arranged between the qubit circuits and is respectively coupled with the qubit circuits for adjusting the interaction strength between the adjacent two qubit circuits, the first connecting circuit is arranged between the qubit circuits and the adjustable coupler circuit, and the second connecting circuit is respectively connected with the qubit circuits. The superconducting circuit provided by the application considers the residual coupling between the quantum bits and the adjustable coupling, corrects the difference between the actually manufactured quantum chip and the theoretical circuit design, and improves the fidelity of the quantum bit gate.
The above description is only for the purpose of describing the preferred embodiments of the present application, and is not intended to limit the scope of the present application, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A superconducting circuit, comprising:
a qubit circuit;
the adjustable coupler circuit is arranged between the two quantum bit circuits, is respectively coupled with the two quantum bit circuits, and is used for adjusting the interaction strength between the two adjacent quantum bit circuits;
a first connection circuit disposed between the qubit circuit and the adjustable coupler circuit;
and the second connecting circuits are respectively connected with the two quantum bit circuits.
2. The superconducting circuit of claim 1, wherein the qubit circuit and the tunable coupler circuit are identical in constituent elements.
3. The superconducting circuit of claim 2, wherein the qubit circuit includes a superconducting quantum interferometer, a first capacitance, a second capacitance, and a third capacitance;
a first pole of the first capacitor is connected with a first pole of the superconducting quantum interferometer, and a second pole of the first capacitor is connected with a second pole of the superconducting quantum interferometer;
the first pole of the second capacitor is connected with the first pole of the superconducting quantum interferometer, and the second pole of the second capacitor is connected with the ground;
the first pole of the third capacitor is connected with the second pole of the superconducting quantum interferometer, and the second pole of the third capacitor is connected with the ground.
4. The superconducting circuit of claim 3, wherein the second connection circuit includes a fourth capacitance and a fifth capacitance.
5. The superconducting circuit of claim 4, wherein the first and second poles of the fourth capacitor connect the first poles of the superconducting quantum interferometers in two adjacent qubit circuits, respectively;
and the first pole and the second pole of the fifth capacitor are respectively connected with the second poles of the superconducting quantum interferometers in the two adjacent qubit circuits.
6. The superconducting circuit of claim 3, wherein the first connection circuit includes a sixth capacitance, a seventh capacitance, an eighth capacitance, and a ninth capacitance;
a first pole of the sixth capacitor is connected with a first pole of a quantum superconducting interferometer in the qubit circuit, and a second pole of the sixth capacitor is connected with a first pole of a quantum superconducting interferometer in the tunable coupler circuit;
a first pole of the seventh capacitor is connected with a first pole of a quantum superconducting interferometer in the qubit circuit, and a second pole of the seventh capacitor is connected with a second pole of the quantum superconducting interferometer in the tunable coupler circuit;
the first pole of the eighth capacitor is connected with the second pole of the quantum superconducting interferometer in the quantum bit circuit; a second pole of the eighth capacitor is connected with a first pole of a quantum superconducting interferometer in the adjustable coupler circuit;
the first pole of the ninth capacitor is connected with the second pole of the quantum superconducting interferometer in the qubit circuit, and the second pole of the ninth capacitor is connected with the second pole of the quantum superconducting interferometer in the tunable coupler circuit.
7. The superconducting circuit of claim 3, wherein the superconducting quantum interferometer comprises two josephson junctions in parallel.
8. The superconducting circuit of claim 1, further comprising a read circuit coupled to the qubit circuit.
9. A quantum chip characterized in that at least the superconducting circuit of any one of claims 1 to 8 is formed thereon.
10. A quantum computer, characterized in that the quantum computer is provided with at least a quantum chip according to claim 9 and a measurement and control device connected to the quantum chip.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115132910A (en) * | 2022-08-30 | 2022-09-30 | 材料科学姑苏实验室 | Measuring device for surface distribution of two-level defects and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115132910A (en) * | 2022-08-30 | 2022-09-30 | 材料科学姑苏实验室 | Measuring device for surface distribution of two-level defects and preparation method thereof |
| CN115132910B (en) * | 2022-08-30 | 2022-11-25 | 材料科学姑苏实验室 | Measuring device for surface distribution of two-level defects and preparation method thereof |
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