CN115132823A - Planar SiC MOSFET integrated with reverse freewheeling diode - Google Patents

Planar SiC MOSFET integrated with reverse freewheeling diode Download PDF

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CN115132823A
CN115132823A CN202210665711.5A CN202210665711A CN115132823A CN 115132823 A CN115132823 A CN 115132823A CN 202210665711 A CN202210665711 A CN 202210665711A CN 115132823 A CN115132823 A CN 115132823A
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赵琳娜
顾晓峰
谈威
鹿存莉
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Jiangnan University
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Jiangnan University
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Abstract

The invention discloses a planar SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) integrated with a reverse freewheeling diode, and belongs to the technical field of semiconductors. The grid of the device is of a separated grid structure, grid polycrystalline silicon is divided into a left part and a right part through source polycrystalline silicon, an additional P-shield area is added at the bottom of the grid polycrystalline silicon, and the source polycrystalline silicon is connected with the P-shield area through a continuous flow tube oxide; the structure enables the channel diode integrated at the bottom of the oxide with the planar structure to replace a body diode in a device to be used as a freewheeling diode, reduces the bipolar degradation effect caused by the recombination of electrons and holes in the traditional SiC MOSFET, reduces the turn-on voltage drop of the freewheeling diode to be smaller than that of the body diode, and reduces the power consumption of a circuit system; the utility model provides a separation grid structure has replaced traditional monoblock grid structure, has reduced electric capacity between grid and the drain electrode just to the area, has improved device capacitance characteristic and miller effect, has reduced the switching loss and the on-off time of device.

Description

Planar SiC MOSFET integrated with reverse freewheeling diode
Technical Field
The invention relates to a planar SiC MOSFET integrated with a reverse freewheeling diode, and belongs to the technical field of semiconductors.
Background
Third generation semiconductor materials typified by silicon carbide have entered the market due to their excellent material properties. Compared with the traditional Si-based semiconductor, the SiC MOSFET has higher breakdown voltage, higher stability, higher thermal conductivity and wider forbidden bandwidth, and is more and more widely applied nowadays.
Compared with a groove type SiC MOSFET, the planar SiC MOSFET has a more mature and simpler technical process, the process of additionally etching a groove on a SiC crystal is omitted, and the groove quality of the groove type SiC MOSFET determines various characteristics of a device to a great extent, such as breakdown voltage, switch service life, gate charge, on-resistance and the like, which has great technical pressure for many enterprises, so the planar SiC MOSFET still occupies the leading position of the commercial market of the SiC MOSFET; in addition, when the planar MOSFET faces high forward bias voltage, high impact ionization and high electric field intensity at the corner of the trench gate are not considered, so that the planar MOSFET has higher withstand voltage level, so that the planar SiC MOSFET has higher competitiveness in the range of 3000V to 4500V, and has the capability of completely replacing the Si IGBT to become an ideal high-voltage power switch device.
As a switching device, a freewheeling diode in the reverse direction is often required in the circuit due to oscillations or voltage spikes, avoiding degradation of the device. There are now several main approaches to using freewheeling diodes: 1. a diode is connected in parallel in the circuit, but the additional switch capacitance and grid charge degradation of the circuit are caused, and the energy loss of the whole circuit is improved; 2. when the device is packaged, the freewheeling diode and the MOSFET are made into a set of facilities, so that the area utilization rate of a chip is reduced, and the use reliability of the device is reduced due to extra current leakage of the device caused by integration of a plurality of systems. 3. The parasitic body diode of the switching element is used as a freewheeling diode when the reverse voltage is applied, but for the traditional SiC MOSFET, the use of the body diode brings about some characteristics: firstly, the threshold voltage of a body diode of the SiC MOSFET is higher and is about 3V, so that the extra energy consumption of the circuit is improved, and the utilization rate of the energy is reduced; and secondly, the bipolar degradation of the device can be caused by the conduction of the body diode, and the defects in the SiC material are increased due to the recombination of electron hole pairs, and the doped region drifts, so that various types of leakage current of the permanent MOSFET are increased, and finally, permanent damage failure is formed.
In addition, the high impact ionization and the electric field concentration of the contact surface of the gate oxide and the JFET area of the traditional planar switching triode under the high forward bias voltage cause the advanced breakdown of the oxidation medium of the device under the high field and the static characteristic degradation of the device under the long-term use. In addition, in the process that the power MOSFET device applies charges to the grid electrode to be started, due to the existence of a grid leakage capacitor (Miller capacitor) between the input and the output, the capacitor is charged firstly in the driving process of the grid electrode, and then the device is started, so that the device has a platform voltage for a long time in the starting process, the switching energy loss of the device is increased, and the use of the device is very adversely affected.
Disclosure of Invention
In order to solve various problems generated when a parasitic body diode is used for freewheeling in the traditional planar SiC MOSFET structure, the invention provides a planar SiC MOSFET integrated with a reverse freewheeling diode, wherein a grid electrode of the planar SiC MOSFET device is of a separated grid structure, polycrystalline silicon connected to the grid electrode is divided into a left part and a right part through polycrystalline silicon connected to a source electrode, an additional P-shield area is added at the bottom of a freewheeling tube oxide below the polycrystalline silicon connected to the source electrode, and the polycrystalline silicon connected to the source electrode is connected with the P-shield area through a freewheeling tube oxide; the thickness of the flow tube oxide under the polysilicon connected to the source is less than the thickness of the tunnel oxide under the polysilicon connected to the gate.
Optionally, the cell structure of the planar SiC MOSFET includes a drain metal 1, a first conductivity type substrate layer 2, a first conductivity type epitaxial layer 3, a JFET region 4, and a source metal 13, which are sequentially stacked from bottom to top;
a P-base area 11, a P-plus area 10 and an N-plus area 9 are symmetrically arranged on the left side and the right side above the JFET area 4, and a P-shield area 5 is arranged in the middle above the JFET area 4; wherein, the left P-plus area 10 is positioned at the upper left of the left P-base area 11; the left N-plus area 9 is positioned above the left P-base area 11, the right side and the lower side of the left N-plus area 9 are wrapped by the left P-base area 11, and the left side of the left N-plus area 9 is attached to the left P-plus area 10; a right P-base area 11, a right P-plus area 10 and a right N-plus area 9 are symmetrically arranged with the left side;
the P-shield region 5 is positioned in the middle of the top of the JFET region 4;
the left channel oxide 8 is positioned above the left N-plus region 9, the left P-base region 11 and the JFET region 4; the right side tunnel oxide 8 and the left side tunnel oxide 8 are symmetrically arranged;
the left gate polysilicon 7 is located above the left channel oxide 8; the right gate polysilicon 7 is located over the right channel oxide 8;
the left and right flow continuing pipe oxides 12 are positioned above the P-shield area 5;
the source polycrystalline silicon 6 is positioned above the P-shield area 5 and the afterflow tube oxide 12, the bottom of the source polycrystalline silicon penetrates through the afterflow tube oxide 12 and is connected with the P-shield area 5, and the top of the source polycrystalline silicon penetrates through the blocking oxide 14 and is connected with the source metal 13;
the blocking oxide 14 is divided into a left part and a right part after being penetrated by the top of the source electrode polycrystalline silicon 6, and the left blocking oxide 14 is positioned above, on the left and on the right of the left grid electrode polycrystalline silicon 7; the right blocking oxide is positioned above, on the left and on the right of the right grid polysilicon 7;
the source metal 13 is located above the P-plus region 10, the N-plus region 9, the blocking oxide 14, and the source polysilicon 6.
Optionally, the oxide under the gate polysilicon 7 is a channel oxide 8, the oxide at other positions around the gate polysilicon is a blocking oxide 14, and the thickness of the blocking oxide 14 is greater than that of the channel oxide 8; the thickness of the tunnel oxide 8 is greater than the thickness of the flow tube oxide 12.
Optionally, the thickness of the tunnel oxide 8 is 40nm to 100nm, and the thickness of the afterflow tube oxide 12 is 10nm to 40 nm; the blocking oxide 14 has a thickness of 0.5 to 5 μm.
Optionally, the length of the contact hole between the source metal 13 and the source polysilicon 6 is 1 μm to 5 μm.
Optionally, the length of the contact hole between the P-shield region 5 and the source polysilicon 6 is 0.4 μm to 1 μm.
Optionally, the width of the P-shield region 5 is 1 μm to 2 μm, and the thickness is 0.5 μm to 1 μm; the distance between the P-shield area 5 and the P-base areas 11 on the two sides is 1-5 mu m.
Optionally, the width of one side of the afterflow tube oxide 12 is 0.5 μm to 1 μm.
Optionally, the doping type of the P-shield region 5 is P-type doping, the doping element is Al element, and the doping concentration is 1 × 10 17 ～1×10 19 cm -3 And the doping concentration of the middle part is higher than that of the upper end and the lower end.
The application also provides a preparation method of the planar SiC MOSFET device integrated with the reverse freewheeling diode, which comprises the following steps:
providing a first conduction type substrate 2, and growing a first conduction type epitaxial layer 3;
a JFET area 4 is grown on the surface of the first conduction type epitaxial layer 3;
adopting photoresist as a mask, injecting Al ions into the JFET region 4 by adopting an ion injection process to form a P-base region 11;
adopting photoresist as a mask, and injecting N ions into the P-base area 11 by adopting an ion injection process to form an N-plus area 9;
adopting photoresist as a mask, and injecting Al ions into the JFET region 4 by adopting an ion injection process to form a P-shield region 5;
using photoresist as a mask, reserving a contact hole between source polysilicon 6 and a P-shield area 5 at the top of the MOSFET, and depositing a dielectric material at the top of the MOSFET to form a follow current tube oxide 12; using photoresist as a mask, depositing a dielectric material on the top of the MOSFET to thicken the dielectric material, and forming a channel oxide 8;
using photoresist as a mask, and depositing grid polysilicon 7 on the surface of the channel oxide 8;
using photoresist as a mask, and depositing source polycrystalline silicon 6 on the surface of the oxide 12 of the follow current tube;
using photoresist as a mask, and depositing a dielectric material above the N-plus region 9, the P-plus region 10, the gate polysilicon 7 and the channel oxide 8 to form a blocking oxide 14;
etching the blocking oxide 14 by using the photoresist as a mask;
metal is deposited on top of the device as source metal 13 and on the bottom of the device as drain metal 1.
The invention has the beneficial effects that:
by providing a SiC planar power MOSFET device with a special structure, the grid of the device is a split-grid structure and consists of two parts of polysilicon connected to a source electrode and polysilicon connected to the grid, and an additional P-shield area is added to the bottom of the follow current tube oxide. The source electrode polycrystalline silicon is connected with the P-shield area by penetrating through the afterflow tube oxide, and the thickness of the afterflow tube oxide is obviously smaller than that of the channel oxides at two ends. The structure has the following advantages that firstly, the channel diode integrated at the bottom of the planar structure oxide can replace a body diode as a freewheeling diode in a device, the bipolar degradation effect caused by the recombination of electrons and holes in a commercial SiC MOSFET is reduced, the turn-on voltage drop of the freewheeling diode is smaller than that of the body diode, and the power consumption of a circuit system is reduced; secondly, the original whole grid structure is changed into a separate grid structure, so that the capacitor dead-against area between the grid and the drain is reduced, the capacitor characteristic and the Miller effect of the device are improved, and the switching loss and the switching time of the device are reduced; thirdly, the structure reduces the peak electric field under high voltage by adding an additional P-shield area, optimizes the electric field distribution of the grid electrode during forward voltage resistance, thereby prolonging the service life of the device, and finally greatly improving the breakdown voltage of the device and amplifying the characteristics of the planar SiC MOSFET under the condition that the on-resistance of the device is not obviously increased; fourthly, the additional P-shield region weakens the impact ionization of the oxide in long-term use, reduces the number of electrons or holes injected into the oxide under high field strength, weakens the performance degradation of the device in repeated avalanche, short circuit and the like, improves the stability of the oxide above the JFET region in long-term use, and enables the oxide to still keep higher level operation in long-term use.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a cell structure diagram of a conventional planar SiC MOSFET device;
fig. 2 is a cell structure diagram of a SiC planar power MOSFET device with reverse freewheeling effect according to the present invention;
FIGS. 3-7 are flow charts of methods for fabricating device structures of the present invention;
in fig. 1-7, 1-drain metal; 2-a first conductivity type substrate; 3-epitaxy of the first conductivity type; 4-JFET region; 5-P-shield region; 6-source polysilicon; 7-gate polysilicon; 8-tunnel oxide; 9-N-plus region; 10-P-plus region; 11-P-base region; 12-a flow-continuing tube oxide; 13-source metal; 14-blocking oxide.
Fig. 8 is a comparison graph of the voltage-current characteristic curve and the forward breakdown characteristic curve of the device in the on state of the conventional structure and the structure of the present invention.
FIG. 9 is a graph comparing voltage and current simulation results of a conventional structure and a structure according to the present invention when a free wheel diode is operated.
FIG. 10 shows the current I in the reverse direction SD ＝100A/cm 2 In the conventional structure and the structure of the invention, the vertical distribution graph of the internal hole concentration of the device changes along with the depth of the device.
Fig. 11 is a graph comparing simulation results of gate charge characteristics of conventional structures and structures of the present invention.
FIG. 12 shows the current I in the reverse direction SD ＝100A/cm 2 In time, the voltage condition V of the device of the traditional structure and the structure of the invention DS Comparative figures for the situation.
FIG. 13 shows the input capacitance characteristics (C) of the device with the conventional structure and the structure of the present invention ISS ) Output capacitance characteristic (C) OSS ) And transfer capacitance characteristics (C) RSS ) The simulation results of (2) are compared with the graph.
FIG. 14 is a graph showing the concentration distribution of P-shield region 5.
FIG. 15 shows the current I in the reverse direction SD ＝100A/cm 2 And comparing the structure simulation of the hole concentration distribution condition in the traditional structure and the structural device of the invention.
FIG. 16 shows the reverse current I of the device with the conventional structure and the structure of the present invention SD ＝100A/cm 2 The current of (c) goes away to the graph.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, a cell structure diagram of a conventional planar SiC MOSFET device (a SiC MOSFET device is composed of a plurality of cells with the same structure) shows that, in the structure of the conventional SiC MOSFET device, when the device operates in a reverse bias, a large amount of current passes through a parasitic body diode of the device, and holes and electrons in a P-base region 11 and a JFET region 4 of the device are recombined, which causes an increase in defects inside the SiC material, and a drift in a doped region, thereby increasing MOSFET leakage current, causing permanent failure damage, ultimately affecting the service life of the switching device and bringing about a great safety hazard.
In addition, since the conventional planar SiC MOSFET operates at a high forward bias voltage, the impact ionization rate and the electric field concentration of the oxide medium above the JFET region are very high, leading to possible premature breakdown and performance degradation of the device during long-term operation, and the like.
Therefore, the present application provides a SiC planar power MOSFET device with a novel structure, which is specifically introduced as follows:
the first embodiment is as follows:
the embodiment provides a planar SiC MOSFET device integrated with a reverse freewheeling diode, wherein a grid electrode of the device is a split-grid structure, polysilicon connected to the grid electrode is divided into a left part and a right part by polysilicon connected to a source electrode, an additional P-shield area is added at the bottom of a freewheeling tube oxide below the polysilicon connected to the source electrode, and the polysilicon connected to the source electrode is connected with the P-shield area by penetrating through the freewheeling tube oxide; the thickness of the flow tube oxide under the polysilicon connected to the source is significantly less than the thickness of the tunnel oxide under the polysilicon connected to the gate.
Specifically, referring to fig. 2, the cell structure of the planar SiC MOSFET device includes a drain metal 1, a first conductivity type substrate layer 2, a first conductivity type epitaxial layer 3, a JFET region 4, and a source metal 13, which are sequentially stacked from bottom to top;
a P-base region 11, a P-plus region 10, an N-plus region 9 and a P-shield region 5 are arranged above the JFET region 4;
the P-shield region 5 is positioned in the middle of the top of the JFET region 4;
the P-base area 11 is located at two ends of the top of the JFET area 4, the P-plus area 10 and the N-plus area 9 are attached to two ends of the top of the P-base area 11 at two sides, the P-plus area 9 is located on one side far away from the P-shield area, and the N-plus area 9 is located on one side close to the P-shield area 5;
the channel oxide 8, the blocking oxide 14 and the follow current tube oxide 12 are positioned above the P-shield area 5, the JFET area 4, the P-base area 11, the N-plus area 9 and the P-plus area 10;
the gate polysilicon 7 is positioned above the channel oxide 8, and both sides and the upper part of the gate polysilicon are wrapped by blocking oxides 14; the source polycrystalline silicon 6 is positioned above the P-shield area 5 and the follow current tube oxide 12, blocking oxides 14 are arranged on two sides of the source polycrystalline silicon, and the bottom of the source polycrystalline silicon penetrates through the follow current tube oxide 12 and is connected with the P-shield area 5;
the source metal 13 is located above the P-plus region 10, the N-plus region 9, the blocking oxide 14, and the source polysilicon, and the top portion thereof is connected to the source polysilicon 6 through the blocking oxide 14.
In the SiC planar power MOSFET device with the structure, the length of a contact hole between the source metal 13 and the source polysilicon 6 is 1-5 mu m; the length of the contact hole between the P-shield area 5 and the source electrode polycrystalline silicon 6 is 0.4-1 mu m.
The doping concentration of the first conductivity type substrate layer 2 is 8 x 10 15 ～1×10 20 cm -3 The depth is 0.5 to 10 μm.
The doping concentration of the first conductivity type epitaxial layer 3 is 1 × 10 14 ～1×10 16 cm -3 The thickness is 5 to 15 μm.
The doping concentration of the JFET region 4 is 1 x 10 14 ～1×10 17 cm -3 The thickness is 1 to 5 μm.
The doping concentration of the P-shield region 5 is 1 x 10 17 ～1×10 19 cm -3 The doping concentration of the middle part is higher than that of the upper end and the lower end, the thickness is 0.5-1 mu m, and the distance between the P-shield area 5 and the P-base areas 11 on the two sides is 1-5 mu m.
The doping concentration of the P-base region 11 is 1 x 10 16 ～1×10 18 cm -3 The thickness is 0.5 to 2 μm.
The doping concentration of the P-plus region 10 is 1X 10 18 ～1×10 20 cm -3 The thickness is 0.1 to 0.5 μm.
The doping concentration of the N-plus region 9 is 1X 10 18 ～1×10 20 cm -3 The thickness is 0.1 to 0.5 μm.
The thickness of the tunnel oxide 8 is 0.5 to 1 μm.
The thickness of the afterflow tube oxide 12 is 0.1 to 0.5 μm, and the length thereof is 0.5 to 1 μm.
The doping concentration of the source polysilicon 6 is 1 × 10 18 ～1×10 20 cm -3 The thickness is 1 to 2 μm.
The doping concentration of the gate polysilicon 7 is 1 × 10 18 ～1×10 20 cm -3 The thickness is 1 to 2 μm.
The thickness of the source metal 13 is 0.5 to 1.5 μm.
The blocking oxide 14 has a thickness of 0.5 to 5 μm.
The width of the single device cell body is 1-5 μm.
The SiC planar power MOSFET device with the structure has the following current diode which consists of two parts:
the first part is a heterojunction diode formed by N-type source polysilicon 6 and the JFET region 4 of SiC material, thereby enabling integration of the Si/SiC heterojunction diode in an N-channel SiC planar power MOSFET.
The second part is a channel diode, which forms a channel under the freewheeling tube oxide 12 when the device is operated at reverse voltage, thereby bleeding off the reverse transient current.
When reverse voltage is applied to the outside of the SiC MOSFET device, a freewheeling diode integrated in the device is turned on, so that the current flow direction of the traditional SiC MOSFET device is changed:
as shown in the left diagram of fig. 16, the current flow of the conventional SiC MOSFET device is: source metal 13 → P-source region 10 → P-base region 11 → JFET region 4 → first conductivity type epitaxial layer 3 → first conductivity type substrate 2 → drain metal 1;
as shown in the right diagram of fig. 16, the current flow inside the planar SiC MOSFET device of the present invention is: source metal 13 → source polysilicon 6 → channel between P-shield region 5 and the flow tube oxide 12 → JFET region 4 → first conductivity type epitaxial layer 3 → first conductivity type substrate 2 → drain metal 1;
it can be seen that the heterojunction diode formed by the N-type source polysilicon 6 and the JFET region 4 of the SiC and the free wheel diode formed by the channel diode share the current originally passing through the parasitic diode in the SiC MOSFET device, i.e. the free wheel diode in the body is turned on in advance in the parasitic diode in the body, at this time, the conduction of the parasitic diode in the body is inhibited, the bipolar degradation effect in the device is avoided, and meanwhile, the threshold voltage of the free wheel diode is only about 1.5V, which reduces the power loss of the circuit system; in addition, the grid polysilicon is etched to form source polysilicon and grid polysilicon, so that the input capacitance, Miller capacitance and grid charge characteristics of the SiC MOSFET are optimized. Due to the existence of the gate-drain capacitance (miller capacitance) between the input and the output, the miller platform exists in the starting process of the power MOSFET device, and the switching energy loss of the device is increased. The application provides a SiC MOSFET device structure is through reducing the overlap area between grid and the drain, truns into some grid-drain electric capacity into source-drain electric capacity, has shortened the miller platform zone time of device greatly, has effectively promoted the switching characteristic, grid electric charge and the electric capacity characteristic of device, has finally reduced the on-off time and the switching loss of device.
As shown in fig. 2, in the SiC planar power MOSFET device designed in the present application, since the conduction voltage drop of the integrated Si/SiC heterojunction diode is about 1.2V, which is much smaller than the conduction voltage drop (3V) of the body diode of the SiC MOSFET, when the SiC MOSFET is reverse voltage-resistant, the freewheeling diode in the body is turned on in advance at the body diode, and at this time, the conduction of the body diode is suppressed, thereby avoiding the reliability problem caused by the degradation of the body diode. And the reverse recovery characteristic of the SiC freewheeling diode is superior to that of a SiC MOSFET body diode, and the SiC freewheeling diode is embodied as high-speed switching reaction, lower reverse recovery current and reverse recovery charge, so that the switching speed of the device is improved.
Example two
The present embodiment provides a method for manufacturing a planar SiC power MOSFET device integrated with a reverse freewheeling diode, for manufacturing the planar SiC MOSFET device of the reverse freewheeling diode according to the first embodiment, with reference to fig. 3 to 7, the method includes:
as shown in fig. 3, a doping concentration of 8 × 10 is provided 15 ～1×10 20 cm -3 A first conductive type substrate 2 with a depth of 0.5-10 μm, a first conductive type epitaxial layer 3 is grown, and the doping concentration of the first conductive type epitaxial layer 3 is 1 × 10 14 ～1×10 16 cm -3 The thickness is 5 to 15 μm.
Growing a JFET region 4 on the surface of the first conductivity type epitaxial layer 3; the doping concentration of the JFET region 4 is 1 x 10 14 ～1×10 17 cm -3 The thickness is 1 to 5 μm.
Injecting Al ions into the JFET region 4 by adopting an ion injection process to form a P-base region 11; the doping concentration of the P-base region 11 is 1 x 10 16 ～1×10 18 cm -3 The thickness is 0.5 to 2 μm.
As shown in fig. 4, a photoresist is used as a mask, and an ion implantation process is used to implant Al ions into the P-base region 11 to form a P-plus region 10; the doping concentration of the P-plus region 10 is 1X 10 18 ～1×10 20 cm -3 The thickness is 0.1 to 0.5 μm.
Implanting N ions on the P-base region 11 by adopting an ion implantation process by using photoresist as a mask to form an N-plus region 9; the doping concentration of the N-plus region 9 is 1X 10 18 ～1×10 20 cm -3 The thickness is 0.1 to 0.5 μm.
Adopting photoresist as a mask, injecting Al ions on the JFET area 4 by adopting an ion injection process to form a P-shield area 5, wherein the doping concentration of the P-shield area 5 is 1 multiplied by 10 17 ～1×10 19 cm -3 And the doping concentration of the middle part is higher than that of the upper end and the lower end, the width is 1-2 mu m, and the thickness is 0.5-1 mu m.
As shown in fig. 5, a photoresist is used as a mask, a contact hole of the source polysilicon 6 and the P-shield area 5 is reserved at the top of the MOSFET, and the length of the contact hole is 0.4-1 μm; depositing a dielectric material on the top of the MOSFET to form a follow current tube oxide 12, wherein the thickness of the follow current tube oxide 12 is 0.1-0.5 mu m, and the length of the follow current tube oxide 12 is 0.5-1 mu m; using photoresist as a mask, depositing a dielectric material on the top of the MOSFET to thicken the dielectric material to form a tunnel oxide 8, wherein the thickness of the tunnel oxide 8 is 0.5-1 mu m;
using photoresist as a mask, depositing a gate polysilicon 7 on the surface of the channel oxide 8, wherein the doping concentration of the gate polysilicon 7 is 1 multiplied by 10 18 ～1×10 20 cm -3 The thickness is 1 to 2 μm;
as shown in fig. 6, using photoresist as mask, depositing source polysilicon 6 on the surface of the oxide 12 of the follow current tube, the doping concentration of the source polysilicon 6 is 1 × 10 18 ～1×10 20 cm -3 The thickness is 1-2 μm;
using photoresist as a mask, and depositing dielectric materials above the N-plus region 9, the P-plus region 10, the gate polysilicon 7 and the channel oxide 8 to form a blocking oxide 14, wherein the thickness of the blocking oxide 14 is 0.5-5 mu m;
etching the blocking oxide 14 as a contact hole of the subsequent source electrode metal 13 and the source electrode polysilicon 6 by using the photoresist as a mask, wherein the length of the contact hole is 1-5 mu m;
a source metal 13 and a drain metal 1 are formed.
The invention adds a P-shield area 5 at the bottom of the oxide, and has the advantages that:
1. the problem of high electric field faced by the SiC heterojunction diode is solved;
2. the problems of high field intensity and high impact ionization when the traditional planar SiC MOSFET works in the forward direction are solved, the electric field distribution of the grid oxide is optimized, and the long-term use reliability of the device is improved;
3. the switching speed of the device is improved, and the charge characteristic of the grid electrode is optimized;
4. the thin freewheeling diode oxide 12 is protected, so that the freewheeling diode channel can be played while the tunnel oxide 8 and the freewheeling diode oxide 12 are protected.
In addition, the doping concentration of the P-shield area is adjusted, so that the concentration of the middle part is higher, and the concentrations of the upper end and the lower end are lower. The lower concentration at two ends can ensure that the freewheeling diode can be started before the parasitic diode when the diode works at a reverse voltage; the higher intermediate concentration can ensure that the structure of the invention improves the electric field distribution of the afterflow tube oxide when working in forward high-voltage bias, and simultaneously plays a good role in protecting the grid oxide and preventing the premature breakdown of the oxide and the deterioration of the service performance.
As shown in fig. 8, which is a comparison graph of the voltage-current characteristic curve and the breakdown characteristic curve of the device with the conventional structure and the structure of the present invention in the on state, it can be seen that the on-state current and the forward breakdown voltage of the device with the improved structure of the present application are compared with those of the conventional device in R on The BV breakdown characteristic curve is obviously improved on the basis that the conduction characteristic curve keeps the original level.
Fig. 9 is a comparison graph of simulation results of reverse voltage and current of the conventional structure and the structure of the present invention when the integrated freewheeling diode is in operation, and it can be seen that the reverse current of the structure of the present application at-3V is much larger than that of the conventional structure, and the freewheeling diode is in a fully on state.
FIG. 10 shows the current I in the reverse direction SD ＝100A/cm 2 In the conventional structure and the structure of the invention, the hole concentration inside the device is distributed longitudinally along with the depth change of the device, so that the hole concentration distribution of the drift region of the structure is far smaller than that of the conventional structure, the recombination phenomenon of the drift region of the device is effectively reduced, and the reliability of the device is improved.
FIG. 11 is a graph comparing simulation results of gate charge characteristics of conventional structures and structures of the present invention; it can be seen that the Miller platform of the grid charge curve of the structure is smaller than that of the traditional structure, the switching loss of the device can be reduced, the starting time is shortened, and the switching performance of the device is improved.
FIG. 12 shows the current I in the reverse direction SD ＝100A/cm 2 In time, the voltage condition V of the device of the traditional structure and the structure of the invention DS A comparison graph of the situations; it can be seen that the reverse voltage required by the structure of the present application to reach the target current is about 1.5V, which is less than 2.8V of the conventional structure, and thus the conduction of the body diode of the device is inhibited, and the energy loss of the device in reverse conduction is reduced.
FIG. 13 shows the input capacitance characteristics (C) of the device with the conventional structure and the structure of the present invention ISS ) Output capacitance characteristic (C) OSS ) And transfer capacitance characteristics (C) RSS ) Comparing the simulation results; it can be seen that the CV characteristics of the structure of the present application are significantly better than those of the conventional structure.
Fig. 14 is a concentration distribution diagram of the P-shield region 5, and it can be seen that the concentration distribution of the structure of the present application is characterized by a higher middle region and lower two end regions, which can ensure that the lower threshold voltage of the freewheeling diode can be ensured, and the P-shield region 5 can optimize the electric field distribution of the oxide above the JFET region 4 in the off state of the device.
FIG. 15 shows the current I in the reverse direction SD ＝100A/cm 2 Comparing the structure of the hole concentration distribution in the device with the traditional structure and the structure of the invention (the left graph corresponds to the traditional structure, the right graphCorresponding to the structure proposed by the invention); it can be seen that the hole concentration of the drift region of the structure of the application is lower than that of the traditional structure under the target current, so that the bipolar degradation effect caused by the recombination of electrons and holes in the commercial planar SiC MOSFET is reduced, and the permanent damage failure which can be formed is avoided.
FIG. 16 shows a device of the present invention in a reverse current I SD ＝100A/cm 2 The current trend graph (the left side is the current trend graph corresponding to the traditional structure, and the right side is the current trend graph corresponding to the structure of the invention), it can be seen that reverse current does not flow out through the body diode due to the existence of the freewheeling diode in the structure of the invention, the body diode area of the device is effectively protected, the use reliability of the device is improved, and the service life of the device is prolonged.
Some steps in the embodiments of the present invention may be implemented by software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, which is intended to cover any modifications, equivalents, improvements, etc. within the spirit and scope of the present invention.

Claims (10)

1. A planar SiC MOSFET device integrated with a reverse freewheeling diode is characterized in that a grid electrode of the planar SiC MOSFET device is of a split-grid structure, polycrystalline silicon connected to the grid electrode is divided into a left part and a right part through polycrystalline silicon connected to a source electrode, an additional P-shield area is added to the bottom of an oxide of a freewheeling tube below the polycrystalline silicon connected to the source electrode, and the polycrystalline silicon connected to the source electrode is connected with the P-shield area through the oxide of the freewheeling tube; the thickness of the flow tube oxide under the polysilicon connected to the source is less than the thickness of the tunnel oxide under the polysilicon connected to the gate.
2. The planar SiC MOSFET device according to claim 1, wherein the cell structure of the planar SiC MOSFET comprises a drain metal (1), a first conductivity type substrate layer (2), a first conductivity type epitaxial layer (3), a JFET region (4) and a source metal (13) which are sequentially stacked from bottom to top;
a P-base area (11), a P-plus area (10) and an N-plus area (9) are symmetrically arranged on the left and right above the JFET area (4), and a P-shield area (5) is arranged in the middle above the JFET area (4); wherein, the left P-plus area (10) is positioned at the upper left of the left P-base area (11); the left N-plus area (9) is positioned above the left P-base area (11), the right side and the lower part of the left N-plus area (9) are wrapped by the left P-base area (11), and the left side of the left N-plus area (9) is attached to the left P-plus area (10); a right P-base area (11), a right P-plus area (10) and a right N-plus area (9) are symmetrically arranged with the left side;
the P-shield region (5) is positioned in the middle of the top of the JFET region (4);
the left channel oxide (8) is positioned above the left N-plus region (9), the left P-base region (11) and the JFET region (4); the right side tunnel oxide (8) and the left side tunnel oxide (8) are symmetrically arranged;
the left gate polysilicon (7) is located above the left channel oxide (8); the right gate polysilicon (7) is positioned above the right channel oxide (8);
the left and right follow current pipe oxides (12) are positioned above the P-shield area (5);
the source polycrystalline silicon (6) is positioned above the P-shield area (5) and the follow current tube oxide (12), the bottom of the source polycrystalline silicon penetrates through the follow current tube oxide (12) and is connected with the P-shield area (5), and the top of the source polycrystalline silicon penetrates through the blocking oxide (14) and is connected with the source metal (13);
the blocking oxide (14) is divided into a left part and a right part after being penetrated by the top of the source electrode polycrystalline silicon (6), and the left blocking oxide (14) is positioned above, on the left and on the right of the left grid electrode polycrystalline silicon (7); the right blocking oxide is positioned above, on the left and on the right of the right grid polysilicon (7);
the source metal (13) is positioned above the P-plus region (10), the N-plus region (9), the blocking oxide (14) and the source polysilicon (6).
3. The planar SiC MOSFET device of claim 2, wherein the oxide under the gate polysilicon (7) is a tunnel oxide (8) and the oxide at other locations around is a blocking oxide (14), the blocking oxide (14) having a thickness greater than the thickness of the tunnel oxide (8); the thickness of the tunnel oxide (8) is greater than the thickness of the flow tube oxide (12).
4. The planar SiC MOSFET device of claim 3, wherein the tunnel oxide (8) has a thickness of 40nm to 100nm, and the follow current tube oxide (12) has a thickness of 10nm to 40 nm; the blocking oxide (14) has a thickness of 0.5 to 5 μm.
5. The planar SiC MOSFET device of claim 4, wherein the contact hole length of the source metal (13) and the source polysilicon (6) is between 1 μm and 5 μm.
6. The planar SiC MOSFET device of claim 5, characterized in that the contact hole length of the P-shield region (5) and the source polysilicon (6) is 0.4 μ ι η to 1 μ ι η.
7. The planar SiC MOSFET device of claim 6, characterized in that the P-shield region (5) has a width of 1 μ ι η to 2 μ ι η and a thickness of 0.5 μ ι η to 1 μ ι η; the distance between the P-shield area (5) and the P-base areas (11) on the two sides is 1-5 mu m.
8. The planar SiC MOSFET device of claim 7, wherein the width of the downstream tube oxide (12) side is 0.5 μ ι η to 1 μ ι η.
9. The planar SiC MOSFET device according to claim 8, characterized in that the doping type of the P-shield region (5) is a P-type doping, the doping element is an Al element, and the doping concentration is 1 x 10 17 ～1×10 19 cm -3 And the doping concentration of the middle part is higher than that of the upper end and the lower end.
10. A preparation method of a planar SiC MOSFET device integrated with a reverse freewheeling diode is characterized by comprising the following steps:
providing a first conductive type substrate (2), and growing a first conductive type epitaxial layer (3);
growing a JFET region (4) on the surface of the first conductivity type epitaxial layer (3);
adopting photoresist as a mask, and injecting Al ions into the JFET region (4) by adopting an ion injection process to form a P-base region (11);
adopting photoresist as a mask, and injecting N ions into the P-base area (11) by adopting an ion injection process to form an N-plus area (9);
adopting photoresist as a mask, and injecting Al ions into the JFET region (4) by adopting an ion injection process to form a P-shield region (5);
using photoresist as a mask, reserving a contact hole between source polysilicon (6) and a P-shield area (5) at the top of the MOSFET, and depositing a dielectric material at the top of the MOSFET to form a follow current tube oxide (12); using photoresist as a mask, and depositing a dielectric material on the top of the MOSFET to thicken the dielectric material to form a tunnel oxide (8);
using photoresist as a mask, and depositing grid polysilicon (7) on the surface of the channel oxide (8);
using photoresist as a mask, and depositing source polysilicon (6) on the surface of the oxide (12) of the continuous flow tube;
using photoresist as a mask, and depositing a dielectric material above the N-plus region (9), the P-plus region (10), the gate polysilicon (7) and the channel oxide (8) to form a blocking oxide (14);
etching the blocking oxide (14) by using the photoresist as a mask;
metal is deposited on top of the device as source metal (13) and on the bottom of the device as drain metal (1).
CN202210665711.5A 2022-06-13 2022-06-13 Planar SiC MOSFET integrated with reverse freewheeling diode Pending CN115132823A (en)

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