CN115114067A - Method, system, device and storage medium for preventing I2C from being suspended - Google Patents
Method, system, device and storage medium for preventing I2C from being suspended Download PDFInfo
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Abstract
The invention provides a method, a system, a device and a storage medium for preventing I2C from being suspended, wherein the method comprises the following steps: in response to an I2C master communicating with an I2C slave abnormally, resetting the I2C interface of the I2C master and detecting an I2C bus state; in response to the number of times of resetting the I2C interface of the I2C master device reaching a preset number of times and the I2C bus is still in a suspended state, judging whether the I2C slave device can be reset through a reset signal; in response to being able to reset the I2C slave device with a reset signal, sending a reset signal to the I2C slave device through an I2C input/output expander or a GPIO of the I2C master device; and in response to the I2C slave device not being reset by the reset signal, sending a control signal to a power converter of the I2C slave device through a GPIO of an I2C input/output expander or the I2C master device, turning off the power of the I2C slave device for a preset time and then turning on.
Description
Technical Field
The present invention relates to the field of servers, and more particularly, to a method, system, device, and storage medium for preventing I2C from being suspended.
Background
I2C is a synchronous, multi-controller/multi-target (controller/target), packet-switched, single-ended, serial communication bus invented by philips semiconductors in 1982. It is widely used to connect low-speed peripheral ICs to processors and microcontrollers in short-range on-board communications. I2C is a two-way two-wire system synchronous serial bus, and adopts data line SDA and clock line SCL to constitute a communication line, and each device can realize data transceiving by connecting in parallel to the bus, and the devices are independent from each other and distinguished by unique bus address, and the bus has the advantages of few wiring, simple control mode, high communication speed and the like. The I2C bus is not only simple in connection and control, but also compatible with the system management bus and the power management bus. Therefore, the I2C bus is widely used inside the server for device management.
Part I2C has a self-reset mechanism designed for the slave device itself, when the clock line or data line has not changed over a certain time, the slave device will actively reset its I2C interface to resume normal communication. In current server designs, in order to better monitor the operation of the server, multiple slave devices are connected to each I2C bus to monitor voltage, temperature, and other information. If a slave device on the bus is out of order and I2C is suspended, the whole bus cannot be used, and the normal operation of the server is greatly influenced.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, a system, a computer device, and a computer readable storage medium for preventing I2C from being suspended, in which when there is a slave device failure causing a bus exception, a master device may send a RESET signal to the slave device or cause the slave device to be powered on again to solve the I2C suspension problem caused by the slave device working exception, so as to recover the I2C bus and avoid affecting the normal operation of the system.
In view of the above objects, an aspect of the embodiments of the present invention provides a method for preventing I2C from being suspended, including the following steps: in response to an I2C master communicating with an I2C slave abnormally, resetting the I2C interface of the I2C master and detecting an I2C bus state; in response to the number of times of resetting the I2C interface of the I2C master device reaching a preset number of times and the I2C bus is still in a suspended state, judging whether the I2C slave device can be reset through a reset signal; in response to being able to reset the I2C slave device by a reset signal, sending a reset signal to the I2C slave device through an I2C input/output expander or a GPIO of the I2C master device; and in response to the I2C slave device not being reset by the reset signal, sending a control signal to the power converter of the I2C slave device through the GPIO of the I2C input/output expander or the I2C master device, turning off the power of the I2C slave device for a preset time and then turning on the slave device.
In some embodiments, the method further comprises: in response to an I2C master device communicating with the I2C input/output expander abnormally, pulling down an enable signal of the power supply of the I2C input/output expander through the GPIO of the I2C master device, and pulling up an enable signal of the power supply of the I2C input/output expander after the preset time interval.
In some embodiments, the sending the reset signal to the I2C slave device through the I2C input/output expander or a GPIO of the I2C master device comprises: the I2C master is paused in communication with all connected I2C slaves of the I2C converter and a reset signal is sent to the I2C converter through the I2C input/output extender.
In some embodiments, the method further comprises: in response to the I2C slave device remaining in a suspend state after turning off the power of the I2C slave device for a preset time and then turning on, suspending communication of the I2C master device with all connected I2C slave devices of the I2C converter and sending a reset signal to the I2C converter through an I2C input/output expander.
In another aspect of the embodiments of the present invention, a system for preventing I2C from being suspended is provided, including: the detection module is configured to respond to communication abnormity of the I2C master device and the I2C slave device, reset the I2C interface of the I2C master device and detect the I2C bus state; the judging module is configured to respond to the fact that the number of times of resetting the I2C interface of the I2C master device reaches a preset number of times and the I2C bus is still in a suspended state, and judge whether the I2C slave device can be reset through a reset signal or not; a reset module configured to send a reset signal to the I2C slave device through a GPIO of an I2C input/output expander or the I2C master device in response to the I2C slave device being resettable by a reset signal; and the control module is used for responding to the fact that the I2C slave device cannot be reset through the reset signal, sending a control signal to a power supply converter of the I2C slave device through an I2C input/output expander or GPIO of the I2C master device, and turning off the power supply of the I2C slave device for a preset time and then turning on the power supply.
In some embodiments, the system further comprises an enabling module configured to: in response to the I2C master device communicating with the I2C input/output expander abnormally, pulling down the enable signal of the power supply of the I2C input/output expander through the GPIO of the I2C master device, and pulling up the enable signal of the power supply of the I2C input/output expander after the preset time interval.
In some embodiments, the reset module is configured to: the I2C master is paused in communication with all connected I2C slaves of the I2C converter and a reset signal is sent to the I2C converter through the I2C input/output extender.
In some embodiments, the system further comprises a pause module configured to: in response to the I2C slave device remaining in a suspend state after turning off the power of the I2C slave device for a preset time and then turning on, suspending communication of the I2C master device with all connected I2C slave devices of the I2C converter and sending a reset signal to the I2C converter through an I2C input/output expander.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: when a bus is abnormal due to a slave device failure, the master device can solve the problem of I2C suspension caused by abnormal operation of the slave device by sending a RESET signal to the slave device or powering on the slave device again, so that the I2C bus is recovered, and the influence on the normal operation of the system is avoided.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a method for preventing I2C suspension provided by the present invention;
FIG. 2 is a schematic circuit diagram of a method for preventing I2C from being suspended according to the present invention;
FIG. 3 is a schematic diagram of an embodiment of a system for preventing I2C hang-up provided by the present invention;
FIG. 4 is a schematic diagram of a hardware configuration of an embodiment of a computer apparatus for preventing I2C from being suspended according to the present invention;
FIG. 5 is a schematic diagram of an embodiment of a computer storage medium to prevent I2C suspension provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In a first aspect of embodiments of the present invention, embodiments of a method of preventing I2C suspension are presented. Fig. 1 is a schematic diagram illustrating an embodiment of a method for preventing I2C from being suspended according to the present invention.
As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, in response to the communication abnormality of the I2C master device and the I2C slave device, resetting the I2C interface of the I2C master device and detecting the I2C bus state;
s2, in response to the fact that the number of times of resetting the I2C interface of the I2C master device reaches a preset number of times and the I2C bus is still in a suspended state, judging whether the I2C slave device can be reset through a reset signal or not;
s3, in response to being able to reset the I2C slave device by a reset signal, sending the reset signal to the I2C slave device through a GPIO of an I2C input/output expander or the I2C master device; and
and S4, in response to the I2C slave device cannot be reset through a reset signal, sending a control signal to a power converter of the I2C slave device through an I2C input/output expander or a GPIO of the I2C master device, and turning off the power of the I2C slave device for a preset time and then turning on the slave device.
In the embodiment of the invention, an I2C master device is connected with an I2C I/O EXPANDER (input/output EXPANDER) and other I2C slave devices through an I2C bus; the POWER supply of I2C I/O EXPANDER and other I2C slave devices is connected to POWER SWITCH (Power supply converter), the POWER supply states of I2C I/O EXPANDER and other I2C slave devices can be controlled by controlling the POWER SWITCH, the POWER SWITCH control signal of I2C I/O EXPANDER is connected to GPIO of I2C master device and is directly controlled by I2C master device, the POWER SWITCH control signal of other slave devices is connected to I2C I/O EXPANDER, and the POWER supply states of other I2C slave devices are controlled by I2C I/O EXPANDER through I2C I/O EXPANDER by the I2C master device. For some I2C slaves that can be reset by a reset signal, their reset signals are also connected to the I2C I/O EXPANDER, whose reset is controlled by the I2C master through the I2C I/O EXPANDER.
When the master device detects that the bus between the master device and a certain slave device is hung, the I2C interface of the master device is reset firstly, the I2C bus state is detected continuously, if the bus is still in the hung state, the I2C interface of the master device is reset continuously, and when the reset number of the master device reaches the set number n, the master device judges that the bus is hung up and is caused by the slave device and cannot be hung up through software operation. For a slave device that can be reset by a reset signal, the master device will send a reset signal to the slave device through I2C I/O EXPANDER or through its preset GPIO to reset the slave device. For the slave device without the reset signal, the master device sends a control signal to the power switch of the slave device through the I2C I/O EXPANDER or through a preset GPIO, the power of the slave device is turned off for a period of time and then turned on, and therefore the slave device is enabled to be in a suspended state.
The design of this circuit is described in detail below by way of example:
in the scheme, BMC serves as a main device, and the circuit design is shown in FIG. 2:
A) Channel 0 of I2C SWITCH is connected to slave 0, and when slave 0 detects that its I2C line is hung up for more than a certain time, it will actively reset its I2C interface;
When the BMC finds that the communication line I2C 0 with the I2C I/O EXPANER is hung up and cannot be reset through software, the BMC controls the GPIO0 to pull down the EN signal of the POWER SWITCH 0, cuts off the POWER supply of the I2C I/O EXPANER, controls the GPIO0 to pull up the EN signal of the POWER SWITCH 0 after a certain time interval, restores the POWER supply of the I2C I/O EXPANER, and resets the I2C to restore normal I2C communication.
When the BMC finds that the communication with the slave 0 is disconnected but the communication with the slave 1 is normal, because the slave 0 has its own I2C with a self-recovery mechanism, I2C line hang is not caused by the slave 0, and the BMC determines that the channel 0 abnormality of I2C SWITCH causes the I2C line hang, so the BMC first suspends the communication with all the connected slaves of I2C SWITCH, and then sends a RESET signal to I2C SWITCH through I2C I/O EXPANER to RESET I2C SWITCH.
When the BMC finds that communication with slave 1 is disconnected but communication with slave 0 is normal, because slave 1 has no reset signal design, the BMC first controls the EN signal of POWER SWITCH 1 through I2C I/O EXPANER, letting slave 1 POWER back up to reset the I2C line. If the I2C line is still in a suspended state after the slave 1 is RESET, then it is determined that I2C SWITCH is abnormal, communication with all connected slaves of I2C SWITCH is suspended, and then a RESET signal is sent to I2C SWITCH via I2C I/O EXPANER, resetting I2C SWITCH.
When the BMC finds that the communication with the slave device 2 is disconnected and the BMC cannot reset through software, the BMC pulls down an EN signal of POWER SWITCH 2 through I2C I/O EXPANER, cuts off the POWER supply of the slave device 2, pulls up the EN signal of POWER SWITCH 2 after a certain time interval, restores the POWER supply of the slave device 2, and resets the slave device to restore normal I2C communication.
It should be noted that, the steps in the embodiments of the method for preventing I2C from being suspended may be intersected, replaced, added or deleted, and therefore, these methods for preventing I2C from being suspended should also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.
In view of the above, a second aspect of the embodiments of the present invention provides a system for preventing I2C from being suspended. As shown in fig. 3, the system 200 includes the following modules: the detection module is configured to respond to communication abnormity of the I2C master device and the I2C slave device, reset the I2C interface of the I2C master device and detect the I2C bus state; the judging module is configured to respond to the fact that the number of times of resetting the I2C interface of the I2C master device reaches a preset number of times and the I2C bus is still in a suspended state, and judge whether the I2C slave device can be reset through a reset signal or not; a reset module configured to send a reset signal to the I2C slave device through an I2C input/output expander or a GPIO of the I2C master device in response to the I2C slave device being resettable by a reset signal; and the control module is used for responding to the fact that the I2C slave device cannot be reset through a reset signal, sending a control signal to a power converter of the I2C slave device through an I2C input/output expander or GPIO of the I2C master device, and turning off the power of the I2C slave device for a preset time and then turning on the slave device.
In some embodiments, the system further comprises an enabling module configured to: in response to an I2C master device communicating with the I2C input/output expander abnormally, pulling down an enable signal of the power supply of the I2C input/output expander through the GPIO of the I2C master device, and pulling up an enable signal of the power supply of the I2C input/output expander after the preset time interval.
In some embodiments, the reset module is configured to: the I2C master is paused in communication with all connected I2C slaves of the I2C converter and a reset signal is sent to the I2C converter through the I2C input/output extender.
In some embodiments, the system further comprises a pause module configured to: in response to the I2C slave device remaining in a suspend state after turning off the power of the I2C slave device for a preset time and then turning on, suspending communication of the I2C master device with all connected I2C slave devices of the I2C converter and sending a reset signal to the I2C converter through an I2C input/output expander.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, in response to the communication abnormality of the I2C master device and the I2C slave device, resetting the I2C interface of the I2C master device and detecting the I2C bus state; s2, in response to the fact that the number of times of resetting the I2C interface of the I2C master device reaches a preset number of times and the I2C bus is still in a suspended state, judging whether the I2C slave device can be reset through a reset signal or not; s3, in response to being able to reset the I2C slave device by a reset signal, transmitting the reset signal to the I2C slave device through a GPIO of the I2C input/output expander or the I2C master device; and S4, in response to the I2C slave device can not be reset through a reset signal, sending a control signal to a power converter of the I2C slave device through an I2C input/output expander or a GPIO of the I2C master device, and turning off the power of the I2C slave device for a preset time and then turning on the slave device.
In some embodiments, the steps further comprise: in response to an I2C master device communicating with the I2C input/output expander abnormally, pulling down an enable signal of the power supply of the I2C input/output expander through the GPIO of the I2C master device, and pulling up an enable signal of the power supply of the I2C input/output expander after the preset time interval.
In some embodiments, the sending the reset signal to the I2C slave device through the I2C input/output expander or a GPIO of the I2C master device comprises: the I2C master is paused in communication with all connected I2C slaves of the I2C converter and a reset signal is sent to the I2C converter through the I2C input/output extender.
In some embodiments, the steps further comprise: in response to the I2C slave device remaining in a suspend state after turning off the power of the I2C slave device for a preset time and then turning on, suspending communication of the I2C master device with all connected I2C slave devices of the I2C converter and sending a reset signal to the I2C converter through an I2C input/output expander.
Fig. 4 is a schematic hardware structural diagram of an embodiment of the computer device for preventing I2C from being suspended according to the present invention.
Taking the device shown in fig. 4 as an example, the device includes a processor 301 and a memory 302.
The processor 301 and the memory 302 may be connected by a bus or other means, such as the bus connection shown in fig. 4.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the method of preventing the suspension of I2C, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more methods of preventing I2C suspension corresponding computer instructions 303 are stored in memory 302 that, when executed by processor 301, perform a method of preventing I2C suspension in any of the method embodiments described above.
Any embodiment of a computer device that implements the above-described method of preventing I2C suspension may achieve the same or similar effects as any of the preceding method embodiments to which it corresponds.
The present invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs a method of preventing I2C suspension.
FIG. 5 is a schematic diagram of one embodiment of a computer storage medium for preventing I2C suspension according to the present invention. Taking the computer storage medium as shown in fig. 5 as an example, the computer readable storage medium 401 stores a computer program 402 which, when executed by a processor, performs the method as described above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for preventing I2C from being suspended can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of preventing I2C suspension, comprising the steps of:
in response to an I2C master communicating with an I2C slave abnormally, resetting the I2C interface of the I2C master and detecting an I2C bus state;
in response to the number of times of resetting the I2C interface of the I2C master device reaching a preset number of times and the I2C bus is still in a suspended state, judging whether the I2C slave device can be reset through a reset signal;
in response to being able to reset the I2C slave device with a reset signal, sending a reset signal to the I2C slave device through an I2C input/output expander or a GPIO of the I2C master device; and
in response to the I2C slave device not being reset by the reset signal, a control signal is sent to the power converter of the I2C slave device through the GPIO of the I2C input/output expander or the I2C master device, turning off the power of the I2C slave device for a preset time and then turning on.
2. The method of claim 1, further comprising:
in response to an I2C master device communicating with the I2C input/output expander abnormally, pulling down an enable signal of the power supply of the I2C input/output expander through the GPIO of the I2C master device, and pulling up an enable signal of the power supply of the I2C input/output expander after the preset time interval.
3. The method of claim 1, wherein the sending the reset signal to the I2C slave device through a GPIO of the I2C input/output expander or the I2C master device comprises:
the I2C master is paused in communication with all connected I2C slaves of the I2C converter and a reset signal is sent to the I2C converter through the I2C input/output extender.
4. The method of claim 1, further comprising:
in response to the I2C slave device remaining in a suspend state after turning off the power of the I2C slave device for a preset time and then turning on, suspending communication of the I2C master device with all connected I2C slave devices of the I2C converter and sending a reset signal to the I2C converter through an I2C input/output expander.
5. A system for preventing I2C suspension, comprising:
the detection module is configured to respond to communication abnormity of the I2C master device and the I2C slave device, reset the I2C interface of the I2C master device and detect the I2C bus state;
the judging module is configured to respond to the fact that the number of times of resetting the I2C interface of the I2C master device reaches a preset number of times and the I2C bus is still in a suspended state, and judge whether the I2C slave device can be reset through a reset signal or not;
a reset module configured to send a reset signal to the I2C slave device through an I2C input/output expander or a GPIO of the I2C master device in response to the I2C slave device being resettable by a reset signal; and
and the control module is configured to respond to the I2C slave device being unable to be reset through a reset signal, send a control signal to a power converter of the I2C slave device through a GPIO of an I2C input/output expander or the I2C master device, and turn off the power of the I2C slave device for a preset time and then turn on the slave device.
6. The system of claim 5, further comprising an enabling module configured to:
in response to an I2C master device communicating with the I2C input/output expander abnormally, pulling down an enable signal of the power supply of the I2C input/output expander through the GPIO of the I2C master device, and pulling up an enable signal of the power supply of the I2C input/output expander after the preset time interval.
7. The system of claim 5, wherein the reset module is configured to:
the I2C master is paused in communication with all connected I2C slaves of the I2C converter and a reset signal is sent to the I2C converter through the I2C input/output extender.
8. The system of claim 5, further comprising a pause module configured to:
in response to the I2C slave device remaining in a suspend state after turning off the power of the I2C slave device for a preset time and then turning on, suspending communication of the I2C master device with all connected I2C slave devices of the I2C converter and sending a reset signal to the I2C converter through an I2C input/output expander.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.
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| CN116107788A (en) * | 2023-02-15 | 2023-05-12 | 广州通康创智软件有限公司 | I2C bus fault processing method and device |
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