CN114443394A - Method and device for releasing I2C bus, computer equipment and storage medium - Google Patents
Method and device for releasing I2C bus, computer equipment and storage medium Download PDFInfo
- Publication number
- CN114443394A CN114443394A CN202210050428.1A CN202210050428A CN114443394A CN 114443394 A CN114443394 A CN 114443394A CN 202210050428 A CN202210050428 A CN 202210050428A CN 114443394 A CN114443394 A CN 114443394A
- Authority
- CN
- China
- Prior art keywords
- bus
- slave device
- slave
- master
- master device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000001514 detection method Methods 0.000 claims abstract description 46
- 230000004044 response Effects 0.000 claims abstract description 30
- 238000004590 computer program Methods 0.000 claims description 25
- 230000008439 repair process Effects 0.000 abstract description 11
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 230000009849 deactivation Effects 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 239000012792 core layer Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The application relates to a method, a device, a computer device and a storage medium for I2C bus hang-up, wherein when detecting that level signals of a serial data line (SDA) and a Serial Clock Line (SCL) of an I2C bus are low level, an I2C master device sends access request information to an I2C slave device, the I2C slave device starts a pre-created I2C bus hang-up detection thread, when the I2C master device does not receive response information of the I2C slave device, the I2C master device is reset according to a first preset condition, and the I2C bus hang-up detection thread is used for resetting the I2C slave device, so that a fault module can be quickly reset, repair time is saved, normal operation of devices in an I2C bus is guaranteed, and fault diffusion is prevented.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for I2C bus deadlock release, a computer device, and a storage medium.
Background
The I2C bus is a shared bus system to which multiple I2C devices can be connected, and devices connected to the I2C bus can function as either a master or a slave. The master device generates a synchronous clock signal to control communication, and transmits data by initializing and terminating data transmission, and the slave device waits for a command from the master device and responds to the reception of the command. The I2C bus is widely used in storage devices, and since the I2C protocol is more biased to the timing definition of the physical layer and error handling for the link layer is not much, the problem of I2C bus hang-up often occurs in a system with complicated and diverse I2C devices.
Currently, 1 hardware pin of an I2C master device is usually connected to a reset pin of an I2C slave device, and when an I2C master device fails to access an I2C slave device, the I2C slave device is reset through the reset pin, so that self-healing after the I2C bus is hung up is realized. However, the reset I2C slave device has a long startup time, and cannot repair the fault quickly, which affects the operation of normal services in the I2C slave device, and causes the fault to spread.
Disclosure of Invention
Therefore, it is necessary to provide a method, an apparatus, a computer device, and a storage medium for I2C bus deadlock release, where the method, the apparatus, the computer device, and the storage medium quickly reset a faulty module through an I2C bus deadlock detection thread, thereby saving repair time, ensuring normal service operation in the I2C slave device, and preventing fault diffusion.
In a first aspect, a method for suspending an I2C bus is provided, the method including:
when detecting that the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are low level, the I2C master device sends access request information to the I2C slave device, and the I2C slave device starts a pre-created I2C bus hang-up detection thread;
when the I2C master device does not receive the response information of the I2C slave device, resetting the I2C master device according to a first preset condition;
the I2C slave is reset according to the I2C bus hang detection thread.
In one possible implementation, resetting an I2C slave according to an I2C bus hang detection thread includes:
reading first level signals of SDA and SCL lines of an I2C bus at intervals of T, wherein T is the period of hanging up a detection thread on the I2C bus;
when the first level signal is at a low level, accumulating the times that the first level signal is at the low level to obtain a count value;
when the count value is greater than the preset count value, the I2C slave device's failed module is reset.
In one possible implementation, the first preset condition includes that the number of times the clock signal is sent to the I2C slave device is greater than a preset number of times; when the I2C master device does not receive the response information of the I2C slave device, the I2C master device is reset according to a first preset condition, and the method comprises the following steps:
when the I2C master device does not receive the response information of the I2C slave device, a clock signal is sent to the I2C slave device;
when the number of times of sending the clock signal to the I2C slave device is greater than the preset number of times, resetting the I2C master device;
the drive information of the I2C master is reconfigured.
In one possible implementation, the method further includes:
when the first level signal is high level, the count value is cleared, and the I2C bus hang detection thread is continuously executed.
In one possible implementation, the method further includes:
after resetting the failed module in the I2C slave device, the drive information of the I2C slave device is reconfigured.
In one possible implementation, the preset count value > a preset number times clock signal/T.
In one possible implementation, the method further includes:
when the I2C master receives the response information of the I2C slave, the I2C driver of the I2C master is exited.
In a second aspect, there is provided an I2C bus de-latching apparatus, comprising:
the starting module is used for sending access request information to the I2C slave device by the I2C master device when detecting that the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are low level, and the I2C slave device starts a pre-created I2C bus hang-up detection thread;
the I2C master device is reset according to a first preset condition when the I2C master device does not receive the response information of the I2C slave device;
and the reset module is also used for resetting the I2C slave device according to the I2C bus hang-up detection thread.
In a third aspect, a computer device is provided, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the computer program, the processor implements the method for suspending the I2C bus in the first aspect or any one of the implementations of the first aspect.
In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, implements the method for I2C bus deactivation in the first aspect or any one of the implementations of the first aspect.
According to the method, the device, the computer equipment and the storage medium for disconnecting the I2C bus, when the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are detected to be low level, the I2C master equipment sends access request information to the I2C slave equipment, the I2C slave equipment starts a pre-created I2C bus deadlock detection thread, when the I2C master equipment does not receive response information of the I2C slave equipment, the I2C master equipment is reset according to a first preset condition, the I2C slave equipment is reset according to the I2C bus deadlock detection thread, the fault module can be reset quickly, the repair time is saved, the normal operation of the equipment in the I2C bus is guaranteed, and fault diffusion is prevented.
Drawings
FIG. 1 is a flow chart illustrating a method for suspending an I2C bus in an embodiment of the present application;
FIG. 2 is a physical topology diagram of an I2C bus according to an embodiment of the present application;
FIG. 3 is a block diagram of an embodiment of an I2C bus deadlocking apparatus;
fig. 4 is an internal structural diagram of a computer device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The implementation of each I2C equipment manufacturer is different, the problem that an I2C bus is hung up frequently occurs when complex and various I2C equipment is arranged in a system, in order to face the problem, the site needs to be reserved, the problem is judged to be the I2C equipment by hardware throughput signals, if the problem occurs to the equipment which is operated in the network, the problem is expected to be automatically repaired, the locatability is increased, the problem of single board return location is avoided, and the single board return rate is reduced. By connecting 1 hardware pin of the I2C master device to the reset pin of the I2C slave device, when the I2C master device fails to access the I2C slave device, the I2C slave device is reset through the reset pin, so that a lot of hardware signals need to be connected, and the hardware resources of the I2C master device are wasted. And the starting completion time of different I2C slave devices is different, the waiting time of the I2C master device cannot be determined, and the normal communication of other I2C slave devices cannot be guaranteed. If the I2C slave device is a service chip, the I2C slave device is directly reset, which may also affect the normal operation of the service, resulting in more abnormal operation of the service.
In order to solve the problems in the prior art, embodiments of the present application provide a method, an apparatus, a device, and a computer storage medium for I2C bus deadlock release. The following first describes a method for I2C bus deactivation provided in the embodiments of the present application.
Fig. 1 is a flowchart illustrating a method for I2C bus deactivation according to an embodiment of the present application. As shown in fig. 1, the method may include the steps of:
s110, when detecting that the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are low level, the I2C master device sends access request information to the I2C slave device, and the I2C slave device starts a pre-created I2C bus hang-up detection thread.
As shown in FIG. 2, the I2C bus includes a serial data line SDA and a serial clock line SCL, the devices under the I2C bus include an I2C master device A1 and at least one I2C slave device A2, the SDA and SCL are respectively connected with a pull-up resistor R2 and R1, and the other end of each pull-up resistor is connected with a power supply VCC. The I2C master device and the I2C slave device may be a Micro Controller Unit (MCU) or a Central Processing Unit (CPU), and the MCU includes many functional modules, and different functional modules communicate using different protocols.
When the I2C bus is idle, that is, the I2C master device does not communicate with any I2C slave device, both the SDA and SCL lines are high, and the level signal of the line and is high, when the I2C master device communicates with one of the I2C slave devices, only any 1 line of the SCL or SDA line is not high, and the level signal of the line and of the SDA and SCL line is low. If the I2C slave does not release the bus, communications on the entire I2C bus are suspended, causing the I2C bus to hang up.
When the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are detected to be low level, which indicates that the condition of I2C bus hang-up may occur at the moment, the I2C master device sends access request information to the I2C slave device, tries to access the I2C slave device, and detects whether the I2C bus hang-up is caused by the I2C master device. The I2C slave initiates a pre-created I2C bus deadlock detection thread, which detects whether an I2C bus deadlock is caused by the I2C slave.
And S120, when the I2C master device does not receive the response information of the I2C slave device, resetting the I2C master device according to a first preset condition.
When the I2C master device does not receive the response information of the I2C slave device, the I2C master device fails to access the I2C slave device, the I2C bus hang-up caused by the I2C master device is possible, the I2C bus hang-up caused by the I2C slave device is also possible, the I2C master device continues to be detected according to a first preset condition, and when the I2C bus hang-up caused by the I2C master device is detected, the I2C master device is reset.
S130, according to the I2C bus hang-up detection thread, the I2C slave device is reset.
Since the first preset condition can only determine that the I2C bus deadlock is caused by the I2C master device, but it cannot be determined whether the I2C slave device also causes the I2C bus deadlock, when the I2C master device is reset according to the first preset condition, the I2C bus deadlock detection thread is still started, and when it is detected that the I2C slave device causes the I2C bus deadlock, the I2C slave device is reset. Repair strategies are set for the I2C master device and the I2C slave device, and the condition that the I2C bus is hung up can be repaired more comprehensively and accurately.
In the embodiment of the application, when the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are detected to be low, the I2C master device sends access request information to the I2C slave device, the I2C slave device starts a pre-created I2C bus hang-up detection thread, when the I2C master device does not receive response information of the I2C slave device, the I2C master device is reset according to a first preset condition, the I2C slave device is reset according to the I2C bus hang-up detection thread, a fault module can be reset quickly, repair time is saved, normal operation of devices in the I2C bus is guaranteed, and fault diffusion is prevented.
In some embodiments, resetting an I2C slave according to an I2C bus hang detection thread includes:
reading first level signals of SDA and SCL lines of an I2C bus at intervals of T, wherein T is the period of hanging up a detection thread on the I2C bus;
when the first level signal is at a low level, accumulating the times that the first level signal is at the low level to obtain a count value;
when the count value is greater than the preset count value, the I2C slave device's failed module is reset.
The first level signal is the level signal of SDA and SCL lines of the I2C bus detected by the detecting thread after the I2C bus hang-up detecting thread is started. And detecting a state register of the I2C bus once every T time interval, reading Bit bits of SDA and SCL levels of the I2C bus from the state register, and obtaining level signals of the SDA and SCL lines.
When the first level signal is at a low level, it indicates that the I2C bus is still in a state of being hung dead at this time, but it is not determined whether the I2C bus is hung dead by the I2C slave device or the I2C bus is hung dead by the I2C master device, so when the first level signal is read to be at a low level for the first time, the number of times that the first level signal is at a low level is accumulated to obtain a count value 1, and when the first level signal is read to be at a low level for the first time, the number of times that the first level signal is at a low level is accumulated to obtain a count value 2 until the count value is accumulated to a preset count value.
When the count value is larger than the preset count value, the possibility of the I2C bus deadlock caused by other reasons is eliminated at this time, the I2C bus deadlock is determined to be caused by the I2C slave device, and therefore, the fault module is reset through resetting the I2C slave device core layer. The fault module is a functional module which is defined by an I2C bus protocol in the I2C slave device and communicates through the SDA and the SCL, so that the problem that the I2C bus is hung up is solved, other functional modules in the I2C slave device are not affected, and the fault diffusion is prevented. Since the whole process is completed by software in the I2C slave device, hardware connection with the I2C master device is not needed, hardware resources of the I2C master device are saved, and the reset time of the I2C slave device in a software form is far shorter than that of the whole I2C slave device in a hardware connection, so that the repair time of the I2C slave device is saved.
In some embodiments, the first preset condition comprises a number of times the clock signal is sent to the I2C slave device being greater than a preset number of times; when the I2C master device does not receive the response information of the I2C slave device, the I2C master device is reset according to a first preset condition, and the method comprises the following steps:
when the I2C master device does not receive the response information of the I2C slave device, a clock signal is sent to the I2C slave device;
when the number of times of sending the clock signal to the I2C slave device is greater than the preset number of times, resetting the I2C master device;
the drive information of the I2C master is reconfigured.
When the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are detected to be low level, which indicates that the I2C bus is hung up at the moment, the I2C master device sends access request information to the I2C slave device, wherein the access request information comprises a unique address and an operation instruction corresponding to the I2C slave device which is communicating with the I2C master device, and whether the I2C slave device is in normal operation is detected. When the I2C master device does not receive the response information of the I2C slave device, the I2C master device and the I2C slave device are indicated to be abnormal in communication, and a clock signal is sent to the I2C slave device to repair the slave device I2C slave device. When the number of times of sending the clock signal to the I2C slave device is greater than the preset number of times, it is shown that the I2C master device caused the I2C bus to hang up, the I2C master device is reset by resetting the core layer of the I2C slave device, the SDA and SCL are released, and the level signals of the external pull-up resistors SDA and SCL are pulled to high level. After the I2C master is reset, the drive information of the I2C master is reconfigured to restore the normal function of the I2C master.
In some embodiments, the method further comprises:
when the first level signal is high level, the count value is cleared, and the I2C bus hang detection thread is continuously executed.
When the I2C master fails to access the I2C slave, a clock signal is sent to the I2C slave to try to repair the I2C slave, and each time the I2C master sends the clock signal to the I2C slave, the I2C slave is accessed again, and whether the I2C slave is repaired is detected. If the clock signal sent by the I2C master device repairs the I2C slave device, at this time, the first level signal becomes high level, the I2C bus is released, and the count value is cleared, so that when the count value reaches the preset count value, the I2C slave device is reset, and the normal operation of each functional module in the I2C slave device is affected. At this point, the I2C bus hang detection thread continues to execute, and an exception condition of I2C bus hang is discovered.
In some embodiments, the method further comprises:
after resetting the failed module in the I2C slave device, the drive information of the I2C slave device is reconfigured.
After resetting the failed module in the I2C slave, the drive information of the I2C slave is reconfigured to restore the normal function of the I2C slave.
In some embodiments, the preset count value > a preset number of times x clock signal/T.
The clock signal is a clock pulse of one cycle sent by the I2C master device to the I2C slave device, and comprises 9 CLKs, the product of the preset number of times and the clock signal is the self-detection time of the I2C master device, and the product of the preset count value and the thread period T is the self-detection time of the I2C slave device. When the I2C bus is hung, the I2C master device and the I2C slave device simultaneously detect abnormal conditions and perform self-detection. If the reason is the reason of the I2C master device, the reason of the I2C master device is reset, the reason of the I2C slave device is reset, and the reason of the I2C slave device is reset, in order to ensure that the I2C master device is normal when detecting whether the reason is the reason of the I2C slave device, the I2C master device needs to detect whether the reason is the reason of the I2C master device firstly and then detect whether the reason is the reason of the I2C slave device. Therefore, the time for the I2C master to self-detect must be less than the time for the I2C slave to self-detect.
In some embodiments, the method further comprises:
when the I2C master receives the response information of the I2C slave, the I2C driver of the I2C master is exited.
When the I2C master device receives the response information of the I2C slave device, it indicates that the I2C master device successfully accesses the I2C slave device, the I2C master device operates normally, the I2C slave device is successfully repaired, it is not necessary to prepare for configuring the drive information after the I2C master device is reset, the I2C driver of the I2C master device is exited, and the operating space of the I2C master device is reduced.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 1 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
In some embodiments, as shown in fig. 3, there is provided an I2C bus deadlocking apparatus, including: a start module 310 and a reset module 320, wherein:
the starting module 310 is configured to, when detecting that a level signal of the serial data line SDA and the serial clock line SCL of the I2C bus is low, send access request information to the I2C slave device by the I2C master device, and start a pre-created I2C bus hang-up detection thread by the I2C slave device;
a reset module 320, configured to reset the I2C master device according to a first preset condition when the I2C master device does not receive the response information of the I2C slave device;
the reset module 320 is further configured to reset the I2C slave device according to the I2C bus hang detection thread.
In the embodiment of the application, the fault module can be quickly reset, the repair time is saved, the normal operation of equipment in the I2C bus is ensured, and the fault diffusion is prevented.
In some embodiments, the reset module 320 is specifically configured to:
reading first level signals of SDA and SCL lines of an I2C bus at intervals of T, wherein T is the period of hanging up a detection thread on the I2C bus;
when the first level signal is at a low level, accumulating the times that the first level signal is at the low level to obtain a count value;
when the count value is greater than the preset count value, the I2C slave device's failed module is reset.
In some embodiments, the first preset condition comprises a number of times the clock signal is sent to the I2C slave device being greater than a preset number of times; the reset module 320 is specifically configured to:
when the I2C master device does not receive the response information of the I2C slave device, a clock signal is sent to the I2C slave device;
when the number of times of sending the clock signal to the I2C slave device is greater than the preset number of times, resetting the I2C master device;
the drive information of the I2C master is reconfigured. In some embodiments, the apparatus further comprises:
and the zero clearing module 370 is configured to clear the count value when the first level signal is at a high level, and continue to execute the I2C bus deadlock detection thread.
In some embodiments, the configuration module 360 is also used to reconfigure the drive information of the I2C slave device after resetting the failed module in the I2C slave device.
In some embodiments, the preset count value > a preset number of times x clock signal/T.
In some embodiments, the exit module 380 is configured to exit the I2C driver of the I2C master device when the I2C master device receives the response information of the I2C slave device.
For specific limitation of the I2C bus deactivation apparatus, reference may be made to the above limitation on the I2C bus deactivation method, and details thereof are not repeated here. The modules in the above-mentioned I2C bus off-hook device can be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In some embodiments, a computer device is provided, which may be a server, the internal structure of which may be as shown in fig. 4. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing the I2C bus hang-off data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of I2C bus deactivation.
Those skilled in the art will appreciate that the architecture shown in fig. 2 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In some embodiments, there is provided a computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the following steps when executing the computer program:
when detecting that the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are low level, the I2C master device sends access request information to the I2C slave device, and the I2C slave device starts a pre-created I2C bus hang-up detection thread;
when the I2C master device does not receive the response information of the I2C slave device, resetting the I2C master device according to a first preset condition;
the I2C slave is reset according to the I2C bus hang detection thread.
In some embodiments, the processor, when executing the computer program, further performs the steps of: resetting the I2C slave according to the I2C bus hang detection thread, comprising: reading first level signals of SDA and SCL lines of an I2C bus at intervals of T, wherein T is the period of hanging up a detection thread on the I2C bus; when the first level signal is at a low level, accumulating the times that the first level signal is at the low level to obtain a count value; when the count value is greater than the preset count value, the I2C slave device's failed module is reset.
In some embodiments, the processor, when executing the computer program, further performs the steps of: the first preset condition comprises that the number of times of sending the clock signal to the I2C slave device is more than a preset number of times; when the I2C master device does not receive the response information of the I2C slave device, the I2C master device is reset according to a first preset condition, and the method comprises the following steps: when the I2C master device does not receive the response information of the I2C slave device, a clock signal is sent to the I2C slave device; when the number of times of sending the clock signal to the I2C slave device is greater than the preset number of times, resetting the I2C master device; the drive information of the I2C master is reconfigured.
In some embodiments, the processor, when executing the computer program, further performs the steps of: when the first level signal is high level, the count value is cleared, and the I2C bus hang detection thread is continuously executed.
In some embodiments, the processor, when executing the computer program, further performs the steps of: after resetting the failed module in the I2C slave, the drive information of the I2C slave is reconfigured.
In some embodiments, the processor, when executing the computer program, further performs the steps of: the preset count value > the preset number of times × the clock signal/T.
In some embodiments, the processor, when executing the computer program, further performs the steps of: when the I2C master receives the response information of the I2C slave, the I2C driver of the I2C master is exited.
In some embodiments, there is provided a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:
when detecting that the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are low level, the I2C master device sends access request information to the I2C slave device, and the I2C slave device starts a pre-created I2C bus hang-up detection thread;
when the I2C master device does not receive the response information of the I2C slave device, resetting the I2C master device according to a first preset condition;
the I2C slave is reset according to the I2C bus hang detection thread.
In some embodiments, the computer program when executed by the processor further performs the steps of: resetting the I2C slave according to the I2C bus hang detection thread, comprising: reading first level signals of SDA and SCL lines of an I2C bus at intervals of T, wherein T is the period of hanging up a detection thread on the I2C bus; when the first level signal is at a low level, accumulating the times that the first level signal is at the low level to obtain a count value; when the count value is greater than the preset count value, the I2C slave device's failed module is reset.
In some embodiments, the computer program when executed by the processor further performs the steps of: the first preset condition comprises that the number of times of sending the clock signal to the I2C slave device is more than a preset number of times; when the I2C master device does not receive the response information of the I2C slave device, the I2C master device is reset according to a first preset condition, and the method comprises the following steps: when the I2C master device does not receive the response information of the I2C slave device, a clock signal is sent to the I2C slave device; when the number of times of sending the clock signal to the I2C slave device is greater than the preset number of times, resetting the I2C master device; the drive information of the I2C master is reconfigured.
In some embodiments, the computer program when executed by the processor further performs the steps of: when the first level signal is high level, the count value is cleared, and the I2C bus hang detection thread is continuously executed.
In some embodiments, the computer program when executed by the processor further performs the steps of: after resetting the failed module in the I2C slave device, the drive information of the I2C slave device is reconfigured.
In some embodiments, the computer program when executed by the processor further performs the steps of: the preset count value > the preset number of times × the clock signal/T.
In some embodiments, the computer program when executed by the processor further performs the steps of: when the I2C master receives the response information of the I2C slave, the I2C driver of the I2C master is exited.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for I2C bus de-hang, the method comprising:
when detecting that the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are low level, the I2C master device sends access request information to the I2C slave device, and the I2C slave device starts a pre-created I2C bus hang-up detection thread;
when the I2C master device does not receive the response information of the I2C slave device, resetting the I2C master device according to a first preset condition;
resetting the I2C slave according to the I2C bus hang detection thread.
2. The method of claim 1, wherein resetting the I2C slave device by the I2C bus hang detection thread comprises:
reading a first level signal of an SDA line and an SCL line of the I2C bus every T time interval, wherein T is a period of hanging a detection thread on the I2C bus;
when the first level signal is at a low level, accumulating the times that the first level signal is at the low level to obtain a count value;
resetting a failed module in the I2C slave device when the count value is greater than a preset count value.
3. The method of claim 1, wherein the first preset condition comprises a number of clock signals sent to the I2C slave device being greater than a preset number; when the I2C master device does not receive the response information of the I2C slave device, resetting the I2C master device according to a first preset condition comprises:
when the I2C master device does not receive the acknowledge information of the I2C slave device, sending a clock signal to the I2C slave device;
resetting the I2C master device when the number of times the clock signal is transmitted to the I2C slave device is greater than a preset number of times;
reconfiguring drive information of the I2C master device.
4. The method of claim 2, further comprising:
when the first level signal is at a high level, the count value is cleared, and the I2C bus hang-up detection thread is continuously executed.
5. The method of claim 2, further comprising:
after resetting the failed module in the I2C slave device, drive information for the I2C slave device is reconfigured.
6. The method of claim 3, wherein the predetermined count value > a predetermined number of times clock signal/T.
7. The method of claim 3, further comprising:
when the I2C master receives the response information of the I2C slave, the I2C driver of the I2C master is exited.
8. An I2C bus deadlocking apparatus, comprising:
the starting module is used for sending access request information to the I2C slave equipment by the I2C master equipment when detecting that the level signals of the serial data line SDA and the serial clock line SCL of the I2C bus are low level, and the I2C slave equipment starts a pre-created I2C bus hang-up detection thread;
a reset module, configured to reset the I2C master device according to a first preset condition when the I2C master device does not receive the response information of the I2C slave device;
the reset module is further configured to reset the I2C slave device according to the I2C bus deadlock detection thread.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1 to 7 are implemented when the computer program is executed by the processor.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210050428.1A CN114443394A (en) | 2022-01-17 | 2022-01-17 | Method and device for releasing I2C bus, computer equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210050428.1A CN114443394A (en) | 2022-01-17 | 2022-01-17 | Method and device for releasing I2C bus, computer equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114443394A true CN114443394A (en) | 2022-05-06 |
Family
ID=81368414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210050428.1A Withdrawn CN114443394A (en) | 2022-01-17 | 2022-01-17 | Method and device for releasing I2C bus, computer equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114443394A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115114067A (en) * | 2022-06-27 | 2022-09-27 | 苏州浪潮智能科技有限公司 | Method, system, device and storage medium for preventing I2C from being suspended |
| CN115129516A (en) * | 2022-06-30 | 2022-09-30 | 苏州浪潮智能科技有限公司 | PCIe device I2C hang-up problem processing method and related assembly |
| CN115658409A (en) * | 2022-11-11 | 2023-01-31 | 苏州浪潮智能科技有限公司 | Abnormity detection method, device, host equipment, system and storage medium |
| CN116107788A (en) * | 2023-02-15 | 2023-05-12 | 广州通康创智软件有限公司 | I2C bus fault processing method and device |
| CN116820840A (en) * | 2023-07-03 | 2023-09-29 | 白盒子(上海)微电子科技有限公司 | I2C bus hang-up automatic recovery method, device, equipment and medium |
| WO2024082801A1 (en) * | 2022-10-21 | 2024-04-25 | 荣耀终端有限公司 | Reset method and electronic device |
| CN118112309A (en) * | 2024-04-30 | 2024-05-31 | 苏州元脑智能科技有限公司 | Fault detection equipment, and fault detection method and device |
-
2022
- 2022-01-17 CN CN202210050428.1A patent/CN114443394A/en not_active Withdrawn
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115114067A (en) * | 2022-06-27 | 2022-09-27 | 苏州浪潮智能科技有限公司 | Method, system, device and storage medium for preventing I2C from being suspended |
| CN115114067B (en) * | 2022-06-27 | 2024-06-28 | 苏州浪潮智能科技有限公司 | Method, system, equipment and storage medium for preventing I2C from being suspended |
| CN115129516A (en) * | 2022-06-30 | 2022-09-30 | 苏州浪潮智能科技有限公司 | PCIe device I2C hang-up problem processing method and related assembly |
| WO2024082801A1 (en) * | 2022-10-21 | 2024-04-25 | 荣耀终端有限公司 | Reset method and electronic device |
| CN117950472A (en) * | 2022-10-21 | 2024-04-30 | 荣耀终端有限公司 | Reset method and electronic equipment |
| CN115658409A (en) * | 2022-11-11 | 2023-01-31 | 苏州浪潮智能科技有限公司 | Abnormity detection method, device, host equipment, system and storage medium |
| CN116107788A (en) * | 2023-02-15 | 2023-05-12 | 广州通康创智软件有限公司 | I2C bus fault processing method and device |
| CN116107788B (en) * | 2023-02-15 | 2024-06-11 | 广州通则康威科技股份有限公司 | I2C bus fault processing method and device |
| CN116820840A (en) * | 2023-07-03 | 2023-09-29 | 白盒子(上海)微电子科技有限公司 | I2C bus hang-up automatic recovery method, device, equipment and medium |
| CN118112309A (en) * | 2024-04-30 | 2024-05-31 | 苏州元脑智能科技有限公司 | Fault detection equipment, and fault detection method and device |
| CN118112309B (en) * | 2024-04-30 | 2024-08-23 | 苏州元脑智能科技有限公司 | Fault detection equipment, and fault detection method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114443394A (en) | Method and device for releasing I2C bus, computer equipment and storage medium | |
| EP1588260B1 (en) | Hot plug interfaces and failure handling | |
| US6505298B1 (en) | System using an OS inaccessible interrupt handler to reset the OS when a device driver failed to set a register bit indicating OS hang condition | |
| CN100361118C (en) | Multiple-CPU system and its control method | |
| CN110908841A (en) | I2C communication abnormity recovery method and device | |
| CN112199240B (en) | Method for switching nodes during node failure and related equipment | |
| JP2006191338A (en) | Gateway apparatus for diagnosing fault of device in bus | |
| US7971098B2 (en) | Bootstrap device and methods thereof | |
| US7219264B2 (en) | Methods and systems for preserving dynamic random access memory contents responsive to hung processor condition | |
| US7996715B2 (en) | Multi nodal computer system and method for handling check stops in the multi nodal computer system | |
| CN104809013A (en) | Embedded system starting method and device | |
| US5712967A (en) | Method and system for graceful recovery from a fault in peripheral devices using a variety of bus structures | |
| CN115904520A (en) | Configuration storage method based on PCIE topological state change and related equipment | |
| CN116820827B (en) | Control method and system of substrate management controller of node server | |
| CN106411643B (en) | BMC detection method and device | |
| CN115904793B (en) | Memory transfer method, system and chip based on multi-core heterogeneous system | |
| CN101645057A (en) | Method and device for preventing CPU local bus from suspension | |
| EP1222543B1 (en) | Method and device for improving the reliability of a computer system | |
| CN112433968A (en) | Controller sharing synchronization method and device | |
| CN117234787B (en) | Method and system for monitoring running state of system-level chip | |
| JP3266841B2 (en) | Communication control device | |
| JP3313667B2 (en) | Failure detection method and method for redundant system | |
| US10983879B1 (en) | System and method for managing recovery of multi-controller NVMe drives | |
| CN113515397B (en) | IPMI command processing method, server, and non-transitory computer readable storage medium | |
| JP4137450B2 (en) | Data processing device that can continue processing with backup data |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20220506 |
|
| WW01 | Invention patent application withdrawn after publication |