CN115101539A - Display substrate, preparation method thereof and display device - Google Patents
Display substrate, preparation method thereof and display device Download PDFInfo
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- CN115101539A CN115101539A CN202210752747.7A CN202210752747A CN115101539A CN 115101539 A CN115101539 A CN 115101539A CN 202210752747 A CN202210752747 A CN 202210752747A CN 115101539 A CN115101539 A CN 115101539A
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- 239000000758 substrate Substances 0.000 title claims abstract description 223
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 283
- 238000000034 method Methods 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 25
- 238000002161 passivation Methods 0.000 claims description 16
- 238000005260 corrosion Methods 0.000 abstract description 7
- 230000007797 corrosion Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 372
- 238000010586 diagram Methods 0.000 description 17
- 238000005530 etching Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/40—OLEDs integrated with touch screens
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Abstract
The embodiment of the application provides a display substrate and a preparation method thereof, and a display device, and belongs to the field of display devices, wherein the display substrate comprises a display area and a wiring area, and the display substrate comprises: a substrate; a first gate layer disposed on one side of the substrate; the source and drain metal layer is arranged on one side, away from the substrate, of the first gate layer and comprises a first metal layer, a second metal layer and a third metal layer which are arranged in a stacked mode; wherein an orthographic projection of the first metal layer and/or the third metal layer on the substrate does not overlap with the termination region. According to the display substrate, the preparation method thereof and the display device, the height of the wiring area can be reduced, and the occurrence of metal cracks and corrosion can be reduced.
Description
Technical Field
The embodiment of the application relates to the technical field of display devices, in particular to a display substrate, a preparation method of the display substrate and a display device.
Background
The OLED products are further developed toward narrow bezel, high frequency and large size. In order to solve the above problems, new metal routing needs to be added to implement narrow-frame output, and delay time and voltage drop of transmission signals are reduced.
However, when a new metal layer is added for routing, the wiring area of the display substrate is also exposed to increased risks, and after the height of the wiring area is increased, the problem that the edge of the wiring area is easy to crack is caused.
Disclosure of Invention
The embodiment of the application aims to provide a display substrate, a preparation method thereof and a display device, and aims to reduce the height of a wiring area and reduce the occurrence of metal cracks and corrosion.
A first aspect of embodiments of the present application provides a display substrate, which includes a display area and a wiring area, the display substrate including:
a substrate;
a first gate layer disposed on one side of the substrate;
the source and drain metal layer is arranged on one side, away from the substrate, of the first gate layer and comprises a first metal layer, a second metal layer and a third metal layer which are arranged in a stacked mode;
wherein an orthographic projection of the first metal layer and/or the third metal layer on the substrate does not overlap with the termination region.
Optionally, the first metal layer is used as a source/drain of the display substrate and is connected to an active layer of the display substrate;
the third metal layer is used as a first switching electrode of the display substrate and is used for communicating the first metal layer with the second metal layer;
the second metal layer is used as a second switching electrode of the display substrate and is used for communicating the third metal layer with a pixel electrode of the display substrate.
Optionally, when an orthographic projection of the first metal layer on the substrate overlaps with the wiring region, the display substrate further includes:
a passivation layer disposed between the first metal layer and the second metal layer, an orthographic projection of the passivation layer on the substrate at least partially overlapping an orthographic projection of the first metal layer on the substrate.
Optionally, the display substrate further comprises:
and the touch metal layer is arranged on one side of the source drain metal layer, which is deviated from the first gate layer, and the orthographic projection of the touch metal layer on the substrate is overlapped with the wiring region.
Optionally, the display substrate further comprises:
and the insulating layer is arranged between the first gate layer and the source drain metal layer, and the orthographic projection of the insulating layer on the substrate is overlapped with the wiring region.
Optionally, the display substrate further comprises:
the flat layer is arranged on one side, away from the first gate layer, of the source drain metal layer, the flat layer is located between the touch metal layer and the source drain metal layer, and the orthographic projection of the flat layer on the substrate is overlapped with the wiring area.
Optionally, the display substrate further comprises:
the touch control insulating layer is arranged between the touch control metal layer and the flat layer, and the orthographic projection of the touch control insulating layer on the substrate is overlapped with the wiring area.
Optionally, within the termination region, an orthographic projection of the planar layer on the substrate at least partially overlaps an orthographic projection of the second metal layer on the substrate.
Optionally, in the wiring region, an orthogonal projection of the touch insulating layer on the substrate at least partially overlaps an orthogonal projection of the second metal layer on the substrate.
Optionally, in the wiring region, the touch metal layer is in direct contact with at least part of the source/drain metal layer.
Optionally, in the wire region, the source-drain metal layer is in direct contact with at least part of the first gate layer.
Optionally, in the wire connection region, an orthographic projection of the source-drain metal layer on the substrate covers an orthographic projection of the first gate layer on the substrate.
Optionally, within the termination region, the second metal layer is in direct contact with at least part of the first gate layer;
alternatively, the second metal layer is in direct contact with at least part of the first metal layer;
alternatively, the second metal layer is in direct contact with at least a portion of the third metal layer.
A second aspect of embodiments of the present application provides a display device, including the display substrate as provided in the first aspect of embodiments of the present application.
A third aspect of the embodiments of the present application provides a method for manufacturing a display substrate, where the display substrate includes a display area and a wiring area, the method including:
providing a substrate;
forming a first gate layer on the substrate;
forming a source drain metal layer on one side of the first gate layer, which is far away from the substrate, wherein the source drain metal layer comprises a first metal layer, a third metal layer and a second metal layer which are stacked;
wherein an orthographic projection of the first metal layer and/or the third metal layer on the substrate does not overlap with the termination region.
Has the advantages that:
the application provides a display substrate, a manufacturing method thereof and a display device, wherein the display substrate comprises a substrate, a first grid layer and a source drain metal layer, the source drain metal layer comprises a first metal layer, a third metal layer and a second metal layer which are arranged in a stacked mode, orthographic projection of the first metal layer and/or the third metal layer on the substrate is enabled to be free of overlapping with a wiring area of the display substrate, namely the number of the source drain metal layers located in the wiring area is reduced, the height of the wiring area of the display substrate can be reduced, and the metal cracks and corrosion of the wiring area can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic plan view illustrating a display substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic side view of a display substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a display substrate including two layers of metal traces in a wiring region according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another display substrate including two layers of metal traces in a wiring region according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a display substrate including a layer of metal traces in a wiring region according to an embodiment of the present application;
FIG. 6 is a flowchart illustrating a method for fabricating a display substrate according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram illustrating a substrate manufactured in a manufacturing method of a display substrate according to an embodiment of the present application;
fig. 8 is a schematic structural diagram illustrating a first gate layer in a method for manufacturing a display substrate according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram illustrating a completed insulating layer in a method for manufacturing a display substrate according to an embodiment of the present application;
FIG. 10 is a schematic structural diagram illustrating a first metal layer formed in a method for manufacturing a display substrate according to an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram illustrating a method for manufacturing a display substrate according to an embodiment of the present application, in which an insulating layer is etched;
fig. 12 is a schematic structural diagram illustrating a third metal layer completed in a method for manufacturing a display substrate according to an embodiment of the present application;
fig. 13 is a schematic structural diagram illustrating a second metal layer completed in a method for manufacturing a display substrate according to an embodiment of the present application;
fig. 14 is a schematic structural diagram illustrating a flat layer and a touch insulating layer formed in a manufacturing method of a display substrate according to an embodiment of the present disclosure;
fig. 15 is a schematic structural diagram illustrating a touch metal layer manufactured in a manufacturing method of a display substrate according to an embodiment of the disclosure;
fig. 16 is a schematic structural diagram illustrating a passivation layer manufactured in a manufacturing method of a display substrate according to an embodiment of the disclosure;
fig. 17 is a schematic structural diagram illustrating a passivation layer and a third metal layer formed in a method for manufacturing a display substrate according to an embodiment of the present disclosure;
fig. 18 is a schematic structural diagram illustrating a process of completing etching of a passivation layer and a first metal layer in a method for manufacturing a display substrate according to an embodiment of the present disclosure;
fig. 19 is a schematic structural diagram illustrating a third metal layer completed in a method for manufacturing a display substrate according to an embodiment of the present application.
Description of the reference numerals: 10. a substrate; 101. a polyimide layer; 102. a buffer layer; 11. a first gate layer; 12. an insulating layer; 13. a source drain metal layer; 131. a first metal layer; 132. a second metal layer; 133. a third metal layer; 14. a passivation layer; 15. a planarization layer; 16. touch control insulating layer; 17. touch-controlling the metal layer; 18. an active layer; 19. a second gate layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the related art, the display panel with three metal traces includes a first metal layer, a third metal layer and a second metal layer, wherein the first metal layer (SD1) is electrically connected to an active layer of the display panel and serves as a source and a drain of a thin film transistor, and the third metal layer (SDM) and the second metal layer (SD2) serve as transfer electrodes, respectively, so that the first metal layer is connected to a pixel electrode of a light emitting layer of a display substrate, thereby controlling light emission of the pixel electrode.
The newly-added metal routing layer can cause that the number of film layers stacked in the wiring area of the display substrate is large, the height of the wiring area is increased, meanwhile, the protruding positions in the wiring area are too many, and in the later process, the positions are easy to crack or be corroded. Moreover, because the wiring areas are too high in height, the situation that the material of the planarization film layer is left between the wiring areas is possible, so that water vapor can easily circulate between the wiring areas, and the risk of reliability is increased.
In view of this, in the display substrate, the manufacturing method thereof and the display device provided in the embodiments of the present application, the display substrate including the substrate 10, the first gate layer 11 and the source/drain metal layer 13 is provided, where the source/drain metal layer 13 includes the first metal layer 131, the third metal layer 133 and the second metal layer 132 which are stacked, and an orthographic projection of the first metal layer 131 and/or the third metal layer 133 on the substrate 10 is not overlapped with a wiring region of the display substrate, that is, by reducing the number of the source/drain metal layers 13 located in the wiring region, the height of the wiring region of the display substrate can be reduced, and thus, the occurrence of metal cracks and corrosion in the wiring region can be reduced.
Referring to fig. 1, a display substrate according to an embodiment of the present disclosure includes a display area, a bending area, and a wiring area. The display region is a region of the display substrate for emitting light and displaying content, light provided by the light emitting layer is emitted from the display region, the wiring region is used for connecting with an ic (integrated Circuit chip) and supplying power to the entire display substrate, and the wiring region is generally provided in plurality. Meanwhile, as shown in fig. 2, after the display substrate is bent, the wiring region is located on the back surface of the display substrate.
Referring to fig. 3, a schematic structural diagram of a display substrate in a wiring region disclosed in an embodiment of the present application is shown, where the display substrate includes, from bottom to top, a substrate 10, a first gate layer 11, and a source-drain metal layer 13 in sequence.
Specifically, the substrate 10 may be a flexible substrate or a rigid substrate. When the substrate 10 is a flexible substrate, the display panel can have the properties of being bendable or bendable; when the substrate 10 is a rigid substrate, the rigidity requirement of the display panel can be met; the properties of a particular substrate 10 are determined according to the actual requirements of the product.
In addition, the substrate 10 may include a single-layer structure or a multi-layer structure. Illustratively, as shown in fig. 7, the substrate 10 may include a polyimide layer 101 and a buffer layer 102, which are sequentially stacked; in other embodiments, the substrate 10 may include a plurality of polyimide layers 101 and buffer layers 102 stacked in sequence. The buffer layer 102 may be made of silicon nitride or silicon oxide, so as to achieve the effect of blocking water and oxygen and blocking alkali ions. It should be noted that the structure of the substrate 10 is not limited thereto, and may be determined according to actual requirements in a specific application.
Referring to fig. 3, the first gate layer 11 is disposed on one side of the substrate 10, and before forming the first gate layer 11, an active layer and an insulating layer 12 are typically formed on the substrate 10, and in addition, in the display substrate, the display substrate may further include a second gate layer and an insulating layer disposed between the first gate layer 11 and the second gate layer. The related structures are all structures existing in the related art, and are not described in detail in the embodiments of the present application. Wherein, the orthographic projections of the active layer and the second gate layer on the substrate 10 are not overlapped with the wiring region.
A source drain metal layer 13 is provided on the side of the first gate layer 11 facing away from the substrate 10. Specifically, in the embodiment of the present application, the source-drain metal layer 13 includes a first metal layer 131, a second metal layer 132, and a third metal layer 133, where the third metal layer 133 is disposed between the first metal layer 131 and the second metal layer 132. The first metal layer 131 is connected to the active layer of the display substrate as the source and drain of the thin film transistor, the third metal layer 133 is connected to the first metal layer 131 as the first transfer electrode of the display substrate, and the second metal layer 132 is connected to the pixel electrode of the display substrate as the second transfer electrode of the display substrate and the third metal layer 133, thereby realizing the light emission control of the pixel electrode.
Further, in order to reduce the height of the terminal area, as shown in fig. 3 to 5, the orthographic projection of the first metal layer 131 and/or the third metal layer 133 on the substrate 10 has no overlap with the terminal area. That is, the distribution of the source drain metal layer 13 in the wiring region of the display substrate includes three cases in total. The first case, as shown in fig. 3, is that the orthographic projection of the first metal layer 131 on the substrate 10 has no overlap with the terminal area; the second case, shown with reference to fig. 4, is that the orthographic projection of the third metal layer 133 on the substrate 10 does not overlap with the terminal area; in the third case, referring to fig. 5, the orthographic projections of the first metal layer 131 and the third metal layer 133 on the substrate 10 are both non-overlapped with the terminal area.
By enabling the orthographic projection of the first metal layer 131 and/or the third metal layer 133 on the substrate 10 to be not overlapped with the wiring region of the display substrate, namely by reducing the number of the source drain electrode metal layers 13 positioned in the wiring region, the height of the wiring region of the display substrate can be reduced, and the occurrence of metal cracks and corrosion in the wiring region can be reduced.
Next, the formation processes of these three cases will be explained in the embodiments of the present application.
When the orthographic projection of the first metal layer 131 on the substrate 10 does not overlap the terminal area, that is, the orthographic projection of the third metal layer 133 and the second metal layer 132 on the substrate 10 overlaps the terminal area.
Specifically, when the display substrate is manufactured, after the first gate layer 11 is formed on the substrate 10, the first metal layer 131 is formed on the side of the first gate layer 11 away from the substrate 10, then the first metal layer 131 within the range of the wiring region is completely etched, so that the first metal layer 131 within the range of the wiring region is not reserved, then the third metal layer 133 and the second metal layer 132 are sequentially formed on the first metal layer 131, and the third metal layer 133 and the second metal layer 132 within the range of the wiring region are reserved, so that the first metal layer 131 does not exist within the range of the wiring region, the number of stacked film layers in the wiring region is reduced, and the overall height of the wiring region is reduced.
It should be noted that, referring to fig. 3, before forming the first metal layer 131, an insulating layer 12 is usually formed on a side of the first gate layer 11 away from the substrate 10, that is, in the overall structure, the insulating layer 12 is located between the first gate layer 11 and the source-drain metal layer 13. In addition, in the range of the wiring region, the insulating layer 12 corresponding to the position of the first gate layer 11 needs to be etched, so that the third metal layer 133 in the source-drain metal layer 13 is in direct contact with at least part of the first gate layer 11 to form an electrical connection. At the same time, second metal layer 132 is also in direct contact with at least a portion of third metal layer 133 to form an electrical connection.
When the orthographic projection of the third metal layer 133 on the substrate 10 does not overlap the terminal area, that is, the orthographic projection of the first metal layer 131 and the second metal layer 132 on the substrate 10 overlaps the terminal area.
Specifically, referring to fig. 4, in the preparation of the display substrate, after the first gate layer 11 is formed, a first metal layer 131 is formed on a side of the first gate layer 11 away from the substrate 10, then a passivation layer 14 is formed on a side of the first metal layer 131 away from the first gate layer 11, the passivation layer 14 is reserved in the wire region, then a third metal layer 133 is formed on a side of the passivation layer 14 away from the first metal layer 131, and the third metal layer 133 in the wire region is etched, so that the first metal layer 131 is not damaged by an etching gas of the third metal layer 133 in the etching process of the third metal layer 133 due to the protection of the passivation layer 14, and finally a second metal layer 132 is formed on a side of the third metal layer 133 away from the first metal layer 131. Meanwhile, the first metal layer 131 is in direct contact with at least a portion of the first gate layer 11 to form an electrical connection.
It should be noted that, when etching the third metal layer 133 in the line region, the passivation layer 14 corresponding to the position of the first gate layer 11 needs to be etched away, so that the second metal layer 132 formed subsequently can be directly contacted with the first metal layer 131 for electrical connection.
When the orthographic projections of the first metal layer 131 and the third metal layer 133 on the substrate 10 do not overlap with the terminal area, only the orthographic projection of the second metal layer 132 on the substrate 10 overlaps with the terminal area.
Specifically, referring to fig. 5, after forming a first gate layer 11 on a substrate 10, an insulating layer 12 is formed on the first gate layer 11, a first metal layer 131 is formed on the insulating layer 12, the first metal layer 131 in the wiring region is completely etched, a third metal layer 133 is formed on the first metal layer 131, the third metal layer 133 in the wiring region is completely etched, the insulating layer 12 in the wiring region at a position corresponding to the first gate layer 11 is etched, the first gate layer 11 is exposed, a second metal layer 132 is formed, and the second metal layer 132 in the wiring region is remained, so that the second metal layer 132 is in direct contact with the first gate layer 11 to achieve electrical connection.
The number of stacked film layers in the wiring area is reduced through the embodiment, so that the height of the wiring area is reduced, the metal cracks and corrosion of the wiring area in the subsequent process are reduced, meanwhile, after the height of the wiring area is reduced, the residue between the wiring areas is reduced, and the reliability failure risk is reduced. In the above embodiment, the number of masks in the whole manufacturing process is not changed, and thus the manufacturing cost is not increased.
In an optional implementation manner, the present application embodiment further provides a display substrate, in which the display substrate further includes a touch metal layer 17 and a touch insulating layer 16, and an orthographic projection of the touch metal layer 17 and the touch insulating layer 16 on the substrate 10 has an overlap with the wiring region.
Specifically, referring to fig. 3, before forming the touch insulating layer 16, a planarization layer 15 is further disposed on a side of the source/drain metal layer 13 away from the first gate layer 11, an orthogonal projection of the planarization layer 15 on the substrate 10 overlaps with the wiring region, and an orthogonal projection of the planarization layer 15 located in the wiring region on the substrate 10 at least partially overlaps with an orthogonal projection of the second metal layer 132 on the substrate 10.
The touch insulating layer 16 is disposed on a side of the planarization layer 15 away from the source-drain metal layer 13, an orthographic projection of the touch insulating layer 16 on the substrate 10 overlaps the wiring region, and an orthographic projection of the touch insulating layer 16 in the wiring region on the substrate 10 at least partially overlaps an orthographic projection of the second metal layer 132 on the substrate 10.
The flat layer 15 and the touch insulating layer 16 can isolate water vapor in the wiring region, and the water vapor is prevented from invading between the source drain metal layers 13 in the wiring region.
The touch metal layer 17 is disposed on a side of the touch insulating layer 16 away from the planarization layer 15, that is, a side of the source/drain metal layer 13 away from the first gate layer 11, an orthographic projection of the touch metal layer 17 on the substrate 10 overlaps with the wiring region, and an orthographic projection of the touch metal layer 17 on the substrate 10 covers the first gate layer 11. Meanwhile, the touch metal layer 17 directly contacts the second metal layer 132 in the source/drain metal layer 13, so that the touch metal layer 17 is communicated with the source/drain metal layer 13 and the first gate layer 11, thereby achieving electrical connection.
Based on the same inventive concept, embodiments of the present application disclose a display device including a display substrate as provided in any of the above embodiments of the present application.
Specifically, the display device may include a computer display, a television, a billboard, a laser printer with a display function, a telephone, a mobile phone, a Personal Digital Assistant (PDA), a laptop computer, a Digital camera, a camcorder, a viewfinder, a vehicle, a large-area wall, a screen of a theater, a stadium sign, or the like.
Fig. 6 shows a flow chart of steps of a method of manufacturing a display substrate. Referring to fig. 6, an embodiment of the present application discloses a method for manufacturing a display substrate, where the display substrate includes a display area and a wiring area, the method including:
step 201: a substrate 10 is provided.
Specifically, the step of completing the fabrication of the substrate 10 may include the step of completing the polyimide layer 101 and the buffer layer 102, as shown in fig. 7.
Step 202: a first gate layer 11 is formed on a substrate 10.
Specifically, the step before forming the first gate layer 11 may further include a step of forming the active layer 18, wherein an orthographic projection of the active layer 18 on the substrate 10 does not overlap with the wiring region, as shown in fig. 8.
Step 203: and forming a source-drain metal layer 13 on the side of the first gate layer 11, which is away from the substrate 10, wherein the source-drain metal layer 13 comprises a first metal layer 131, a third metal layer 133 and a second metal layer 132 which are stacked, and an orthographic projection of the first metal layer 131 and/or the third metal layer 133 on the substrate 10 is not overlapped with the wiring region.
Specifically, the step before forming the source-drain metal layer 13 may further include a step of forming the insulating layer 12, as shown in fig. 9. Meanwhile, the step after the source-drain metal layer 13 is formed further includes a step of forming a planarization layer 15, a touch insulating layer 16 and a touch metal layer 17, wherein orthographic projections of the planarization layer 15, the touch insulating layer 16 and the touch metal layer 17 on the substrate 10 are overlapped with the wiring region, as shown in fig. 15 and 16.
Further, the orthographic projection of the first metal layer 131 and/or the orthographic projection of the third metal layer 133 on the substrate 10 does not overlap with the wiring region includes three cases, the first case is that the orthographic projection of the first metal layer 131 on the substrate 10 does not overlap with the wiring region, the second case is that the orthographic projection of the third metal layer 133 on the substrate 10 does not overlap with the wiring region, and the third case is that the orthographic projection of the first metal layer 131 and the orthographic projection of the third metal layer 133 on the substrate 10 do not overlap with the wiring region.
Specifically, in the case where the orthographic projection of the first metal layer 131 on the substrate 10 does not overlap with the terminal area, the preparation method includes:
step 2031: after forming the first metal layer 131 on the side of the first gate layer 11 facing away from the substrate 10, the first metal layer 131 located in the wiring region is etched.
Specifically, before forming the first metal layer 131, the insulating layer 12 is formed on the side of the first gate layer 11 away from the substrate 10, then the first metal layer 131 is formed on the insulating layer 12, and then the first metal layer 131 in the wire region is etched, and at the same time, the insulating layer 12 in the wire region is etched, so that an orthographic projection of the insulating layer 12 on the substrate 10 overlaps with an orthographic projection of the first gate layer 11 on the substrate 10, as shown in fig. 10 to 12.
Step 2032: and sequentially forming a third metal layer 133 and a second metal layer 132 on the side of the first metal layer 131, which faces away from the substrate 10, wherein orthographic projections of the third metal layer 133 and the second metal layer 132 on the substrate 10 are overlapped with the wiring regions.
Specifically, in the wiring region, the third metal layer 133 is directly connected to the first gate layer 11 to electrically connect the source-drain metal layer 13 to the first gate layer 11, as shown in fig. 13.
In the case where the orthographic projection of the third metal layer 133 on the substrate 10 does not overlap with the terminal area, the preparation method comprises:
step 2033: forming a first metal layer 131 on a side of the first gate layer 11 facing away from the substrate 10;
step 2034: forming a passivation layer 14 on a side of the first metal layer 131 facing away from the first gate layer 11;
step 2035: after the third metal layer 133 is formed on the side of the passivation layer 14 facing away from the first metal layer 131, the third metal layer 133 located in the termination region is etched.
Specifically, due to the protection of the passivation layer 14, the first metal layer 131 is not damaged by the etching gas of the third metal layer 133 during the etching of the third metal layer 133, as shown in fig. 17 and 18.
Step 2036: a second metal layer 132 is formed on a side of the third metal layer 133 opposite to the first metal layer 131, and orthographic projections of the first metal layer 131 and the second metal layer 132 on the substrate 10 have an overlap with the wiring region.
In the case where the orthographic projections of the first metal layer 131 and the third metal layer 133 on the substrate 10 are not overlapped with the terminal areas, the preparation method includes:
step 2037: after forming the first metal layer 131 on the side of the first gate layer 11 facing away from the substrate 10, the first metal layer 131 located in the wiring region is etched, as shown in fig. 10.
Step 2038: after the third metal layer 133 is formed on the side of the first metal layer 131 facing away from the substrate 10, the third metal layer 133 in the termination area is etched, as shown in fig. 19.
Step 2039: a second metal layer 132 is formed on the side of the third metal layer 133 facing away from the substrate 10, and an orthographic projection of the second metal layer 132 on the substrate 10 overlaps the terminal area.
Specifically, in the step of etching the first metal layer 131, the insulating layer 12 on the first gate layer 11 is not etched, as shown in fig. 10 and 11, and after the third metal layer 133 is formed, the third metal layer 133 and the insulating layer 12 are etched so that an orthographic projection of the insulating layer 12 on the substrate 10 overlaps with an orthographic projection of the first gate layer 11 on the substrate 10, as shown in fig. 19 and 11.
The display substrate manufactured by the manufacturing method reduces the number of stacked film layers in the wiring area, so that the height of the wiring area is reduced, the conditions of metal cracks and corrosion in the subsequent process of the wiring area are favorably reduced, meanwhile, after the height of the wiring area is reduced, the residue in the wiring area is favorably reduced, and the reliability failure risk is reduced. In the above embodiment, the number of masks in the whole manufacturing process is not changed, and thus the manufacturing cost is not increased.
It should be noted that, in this specification, each embodiment is described in a progressive manner, and each embodiment focuses on differences from other embodiments, and portions that are the same as and similar to each other in each embodiment may be referred to.
It should also be noted that, in this document, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application. Moreover, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions or neither should the relative importance be understood or implied. Also, the terms "include", "including" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or terminal device including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article, or terminal device. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or terminal equipment comprising the element.
The technical solutions provided in the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the descriptions of the above examples are only used to help understanding the present application, and the content of the present specification should not be construed as limiting the present application. While various modifications of the illustrative embodiments and applications will be apparent to those skilled in the art based upon this disclosure, it is not necessary or necessary to exhaustively enumerate all embodiments, and all obvious variations and modifications can be resorted to, falling within the scope of the disclosure.
Claims (15)
1. A display substrate comprising a display area and a wiring area, the display substrate comprising:
a substrate;
a first gate layer disposed on one side of the substrate;
the source and drain metal layer is arranged on one side, away from the substrate, of the first gate layer and comprises a first metal layer, a third metal layer and a second metal layer which are arranged in a stacked mode;
wherein an orthographic projection of the first metal layer and/or the third metal layer on the substrate does not overlap with the wiring region.
2. The display substrate of claim 1, wherein:
the first metal layer is used as a source electrode/drain electrode of the display substrate and is connected with an active layer of the display substrate;
the third metal layer is used as a first switching electrode of the display substrate and is used for communicating the first metal layer with the second metal layer;
the second metal layer is used as a second switching electrode of the display substrate and is used for communicating the third metal layer with a pixel electrode of the display substrate.
3. The display substrate of claim 1, wherein an orthographic projection of the first metal layer on the substrate overlaps the wire region, the display substrate further comprising:
a passivation layer disposed between the first metal layer and the second metal layer, an orthographic projection of the passivation layer on the substrate at least partially overlapping an orthographic projection of the first metal layer on the substrate.
4. The display substrate of claim 1, further comprising:
and the touch metal layer is arranged on one side of the source drain metal layer, which is deviated from the first gate layer, and the orthographic projection of the touch metal layer on the substrate is overlapped with the wiring region.
5. The display substrate of claim 4, further comprising:
and the insulating layer is arranged between the first gate layer and the source drain metal layer, and the orthographic projection of the insulating layer on the substrate is overlapped with the wiring region.
6. The display substrate of claim 5, further comprising:
the flat layer is arranged on one side, away from the first gate layer, of the source drain metal layer, the flat layer is located between the touch metal layer and the source drain metal layer, and the orthographic projection of the flat layer on the substrate is overlapped with the wiring area.
7. The display substrate of claim 6, further comprising:
the touch control insulating layer is arranged between the touch control metal layer and the flat layer, and the orthographic projection of the touch control insulating layer on the substrate is overlapped with the wiring area.
8. The display substrate of claim 7, wherein:
within the termination region, an orthographic projection of the planar layer on the substrate at least partially overlaps an orthographic projection of the second metal layer on the substrate.
9. The display substrate of claim 7, wherein:
in the wiring area, the orthographic projection of the touch insulating layer on the substrate is at least partially overlapped with the orthographic projection of the second metal layer on the substrate.
10. The display substrate of claims 1-9, wherein:
in the wiring area, the touch metal layer is in direct contact with at least part of the source drain metal layer.
11. The display substrate of claim 10, wherein:
in the wiring region, the source drain metal layer is in direct contact with at least part of the first gate layer.
12. The display substrate of claim 11, wherein:
in the wiring region, the orthographic projection of the source drain metal layer on the substrate covers the orthographic projection of the first gate layer on the substrate.
13. The display substrate according to claim 11, wherein:
within the termination region, the second metal layer is in direct contact with at least a portion of the first gate layer;
alternatively, the second metal layer is in direct contact with at least part of the first metal layer;
alternatively, the second metal layer is in direct contact with at least a portion of the third metal layer.
14. A display device, characterized in that:
comprising a display substrate according to any one of claims 1-13.
15. A method of manufacturing a display substrate including a display area and a wiring area, the method comprising:
providing a substrate;
forming a first gate layer on the substrate;
forming a source drain metal layer on one side of the first gate layer, which is far away from the substrate, wherein the source drain metal layer comprises a first metal layer, a third metal layer and a second metal layer which are stacked;
wherein an orthographic projection of the first metal layer and/or the third metal layer on the substrate does not overlap with the termination region.
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| CN202210752747.7A CN115101539A (en) | 2022-06-29 | 2022-06-29 | Display substrate, preparation method thereof and display device |
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| CN202210752747.7A CN115101539A (en) | 2022-06-29 | 2022-06-29 | Display substrate, preparation method thereof and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115509050A (en) * | 2022-10-09 | 2022-12-23 | 厦门天马微电子有限公司 | Display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115509050A (en) * | 2022-10-09 | 2022-12-23 | 厦门天马微电子有限公司 | Display panel and display device |
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