CN115084113A - Semiconductor circuit with double-layer structure and electric control board - Google Patents
Semiconductor circuit with double-layer structure and electric control board Download PDFInfo
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- CN115084113A CN115084113A CN202210699367.1A CN202210699367A CN115084113A CN 115084113 A CN115084113 A CN 115084113A CN 202210699367 A CN202210699367 A CN 202210699367A CN 115084113 A CN115084113 A CN 115084113A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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Abstract
The invention relates to a semiconductor circuit with a double-layer structure and an electric control board, wherein the semiconductor circuit comprises a first circuit substrate assembly, a second circuit substrate assembly and a sealing layer which are arranged up and down, a plurality of fixing columns are arranged between the first circuit substrate assembly and the second circuit substrate assembly, the first circuit substrate assembly comprises a first substrate, a plurality of first electronic elements and a first pin group, and the second circuit substrate assembly comprises a second substrate, a plurality of second electronic elements and a second pin group. Through two-layer circuit substrate subassembly about inside sets up, the circuit substrate subassembly of relative individual layer like this for electronic component can set up on this two-layer base plate, thereby the effectual surface area of reducing circuit substrate subassembly, thereby single circuit board relatively, the volume of further effectual reduction circuit board is favorable to the miniaturization of whole controller very much, and the cost has been saved in the correspondence.
Description
Technical Field
The invention relates to a semiconductor circuit with a double-layer structure and an electric control board, belonging to the technical field of semiconductor circuit application.
Background
A semiconductor circuit is a power-driven type product that combines power electronics and integrated circuit technology. The outer surface of a semiconductor circuit is generally encapsulated with a resin material formed by injection molding to form a sealing layer, and a circuit board and an electronic component formed on the basis of a substrate are sealed, and leads are protruded from one side or both sides of the sealing layer. The circuit board of the traditional semiconductor circuit is of a single-layer structure, and the pins are bent and formed in the same direction, so that the size of the semiconductor circuit is large, and when the circuit board is applied to a controller of a product, the size of the control circuit board is also large, and the circuit board is not beneficial to miniaturization and high in cost.
Disclosure of Invention
The invention aims to solve the technical problems that the volume of the conventional semiconductor circuit is large, and the size of an applied control circuit board is large and is not beneficial to miniaturization due to the fact that pins face one direction.
Specifically, the invention discloses a semiconductor circuit with a double-layer structure, which comprises a first circuit substrate assembly, a second circuit substrate assembly and a sealing layer which are arranged up and down, wherein a plurality of fixing columns are arranged between the first circuit substrate assembly and the second circuit substrate assembly, wherein,
the first circuit substrate assembly includes:
the first substrate comprises a mounting surface and a heat dissipation surface, wherein the mounting surface is provided with a first circuit wiring layer;
a plurality of first electronic elements provided on the first circuit wiring layer;
the first pin group is arranged on at least one side of the first substrate, and one end of each pin of the first pin group is connected with the first circuit wiring layer;
the second circuit substrate assembly includes:
a second substrate, a second circuit wiring layer being provided on a surface of the second substrate;
a plurality of second electronic elements provided on the second circuit wiring layer;
the second pin group is arranged on at least one side of the second substrate, and one end of each pin of the second pin group is connected with the second circuit wiring layer;
the overall heat generation of the first electronic elements is larger than that of the second electronic elements, and the bending directions of the first pin group and the second pin group are opposite.
The sealing layer covers the first circuit substrate assembly and the second circuit substrate assembly, the first pin group and the second pin group are respectively exposed from the side face of the sealing layer, and the heat dissipation surface of the first substrate is exposed from the surface of the sealing layer.
Optionally, the thermal conduction efficiency of the first substrate is higher than the thermal conduction efficiency of the second substrate.
Optionally, the first substrate is a metal substrate, and the second substrate is a glass fiber board.
Optionally, the first lead group and the second lead group are arranged side by side, the first lead group is bent upwards, and the second lead group is bent downwards.
Optionally, the first lead group and the second lead group are arranged side by side left and right.
Alternatively, the first pin group and the second pin group are two independent groups and are arranged up and down in the thickness direction of the semiconductor circuit.
Optionally, the fixing posts are disposed relatively close to the side edges of the first substrate and the second substrate.
Optionally, the second electronic element comprises a driving chip and a resistance-capacitance element.
Optionally, the first electronic component operates in a high voltage environment and the second electronic component operates in a low voltage environment.
The invention also provides an electric control board, the electric control board is provided with the semiconductor circuit, the electric control board further comprises an upper electric control board and a lower electric control board which are arranged up and down, the semiconductor circuit is arranged between the upper electric control board and the lower electric control board, and a first pin group and a second pin group of the semiconductor circuit are respectively connected with the upper electric control board and the lower electric control board.
The semiconductor circuit comprises a first circuit substrate assembly, a second circuit substrate assembly and a sealing layer, wherein the first circuit substrate assembly, the second circuit substrate assembly and the sealing layer are arranged up and down, a plurality of fixing columns are arranged between the first circuit substrate assembly and the second circuit substrate assembly, the first circuit substrate assembly comprises a first substrate, a plurality of first electronic elements and a first pin group, and the second circuit substrate assembly comprises a second substrate, a plurality of second electronic elements and a second pin group. Through two-layer circuit substrate subassembly about inside sets up, the circuit substrate subassembly of relative individual layer like this for electronic component can set up on this two-layer base plate, thereby the effectual surface area of reducing circuit substrate subassembly, thereby single circuit board relatively, the volume of further effectual reduction circuit board is favorable to the miniaturization of whole controller very much, and the cost has been saved in the correspondence.
Description of the drawings:
fig. 1 is a cross-sectional view of a prior art semiconductor circuit along the thickness direction;
FIG. 2 is a perspective view of a semiconductor circuit according to an embodiment of the present invention;
FIG. 3 is a perspective view of a semiconductor circuit according to another embodiment of the present invention;
fig. 4 is a cross-sectional view of the semiconductor circuit shown in fig. 2 in a thickness direction;
fig. 5 is a cross-sectional view of the semiconductor circuit shown in fig. 3 in a thickness direction;
FIG. 6 is a perspective view of an electrical control panel of an embodiment of the present invention;
fig. 7 is a perspective view of the electrical control panel of fig. 6 in another view orientation.
Reference numerals:
the semiconductor circuit comprises a semiconductor circuit 100, a first circuit substrate assembly 110, a first substrate 111, an IGBT (insulated gate bipolar transistor) 112, an auxiliary radiator 113, a first bonding wire 114, a green oil layer 115, an insulating layer 116, a first circuit wiring layer 117, a resistor 118, a second circuit substrate assembly 120, a second substrate 121, a resistor 122, a driving chip 123, a second bonding wire 124, a fixed column 130, a sealing layer 140, a first pin group 150, a second pin group 160, an upper electronic control board 300, a metal radiator 310, an inductor 320, an electrolytic capacitor 330, a lower electronic control board 400 and an MCU 410.
Detailed Description
It is to be noted that the embodiments and features of the embodiments may be combined with each other without conflict in structure or function. The present invention will be described in detail below with reference to examples.
The semiconductor circuit provided by the invention is a circuit module which integrates a power switch device, a high-voltage driving circuit and the like together and is sealed and packaged on the outer surface, and is widely applied to the field of power electronics, such as the fields of frequency converters of driving motors, various inversion voltages, variable frequency speed regulation, metallurgical machinery, electric traction, variable frequency household appliances and the like. The semiconductor circuit herein may be referred to by various other names, such as Modular Intelligent Power System (MIPS), Intelligent Power Module (IPM), or hybrid integrated circuit, Power semiconductor Module, Power Module, etc.
As shown in fig. 2 to 5, the semiconductor circuit 100 includes a first circuit board assembly 110, a second circuit board assembly 120 and a sealing layer 140 disposed on top of and below the first circuit board assembly 110, wherein a plurality of fixing posts 130 are disposed between the first circuit board assembly 110 and the second circuit board assembly 120, wherein the first circuit board assembly 110 includes a first substrate 111, a plurality of first electronic components, and a first pin group 150, and the second circuit board assembly 120 includes a second substrate 121, a plurality of second electronic components, and a second pin group 160. The first substrate 111 comprises a mounting surface and a heat dissipation surface, the mounting surface is provided with a first circuit wiring layer 117, a plurality of first electronic elements are arranged on the first circuit wiring layer 117, the first pin group 150 is arranged on at least one side of the first substrate 111, and one end of each pin of the first pins is connected with the first circuit wiring layer 117; the surface of the second substrate 121 is provided with a second circuit wiring layer, a plurality of second electronic elements are arranged on the second circuit wiring layer, the second pin group 160 is arranged on at least one side of the second substrate 121, one end of each pin of the second pin group 150 is connected with the second circuit wiring layer, the overall heat generation of the plurality of first electronic elements is larger than the heat generation of the plurality of second electronic elements, and the bending directions of the first pin group 150 and the second pin group 160 are opposite. The sealing layer 140 covers the first circuit board assembly 110 and the second circuit board assembly 120, the first lead group 150 and the second lead group 160 are exposed from the side surface of the sealing layer 140, respectively, and the heat dissipation surface of the first substrate 111 is exposed from the surface of the sealing layer 140.
As shown in fig. 1, the related art semiconductor circuit includes a circuit board assembly 230, the circuit board assembly 230 generally includes a substrate, a circuit layer disposed on a surface of the substrate, and an electronic component mounted on the circuit layer, the circuit board assembly 230 is half-or fully-coated with a sealing layer 220, a lead 210 is disposed on one side of the circuit board assembly 230 and connected to the circuit wiring layer, and most of the lead 210 is exposed from the sealing layer 220. As can be seen from fig. 1, the circuit substrate assembly 230 is a single-layer structure, so that electronic components can be disposed on only one side of the substrate, which results in a larger substrate area if more electronic components need to be mounted, thereby increasing the volume of the corresponding semiconductor circuit, and the pins 210 are bent upward, when the semiconductor circuit is applied to a specific circuit board of a controller, the semiconductor circuit can be mounted on only one surface of the circuit board, i.e., all circuit wires of the controller can be disposed on only one circuit board, and when the controller circuit is more complex, the area of the circuit board needs to be occupied, so that the conventional semiconductor circuit 100 is not favorable for the application scenario of a miniaturized controller, and the cost is also increased.
Compared with the prior art, the semiconductor circuit 100 of the present invention has a circuit substrate assembly with upper and lower layers inside the semiconductor circuit 100, this allows for a single layer of circuit substrate assembly, so that electronic components may be disposed on both layers of substrate, thereby effectively reducing the surface area of the circuit substrate assembly to half of a single-layer circuit substrate assembly theoretically, only slightly increasing the thickness compared with the semiconductor circuit in the prior art, and the first lead group 150 and the second lead group 160 of the circuit substrate assembly located at the upper and lower layers are bent in opposite directions, so that when the two groups of pins are arranged on the circuit board of the controller, the two groups of pins can be respectively connected on the two layers of circuit boards which are arranged up and down, therefore, compared with a single circuit board, the size of the circuit board is further effectively reduced, the miniaturization of the whole controller is greatly facilitated, and the cost is correspondingly saved. The first electronic component on the upper first circuit board assembly 110 generates heat more than the second electronic component on the second circuit board assembly 120, and the heat dissipation surface of the substrate in the first circuit board assembly 110 is exposed to the sealing layer 140, thereby contributing to heat dissipation of the first electronic component having a large heat generation amount. So that the operating temperature of the semiconductor circuit 100 is kept within the safe value, thereby improving the operating reliability thereof.
In some embodiments of the present invention, the first substrate 111 may be made of a metal material, and specifically may be a rectangular plate made of aluminum of 1100, 52, etc. The first substrate 111 may also be another insulating material such as ceramic. If the first substrate 111 is a metal material, as shown in fig. 4 and 5, an insulating layer 116 may be further included between the first substrate 111 and the first circuit wiring layer 117 to achieve electrical isolation between the first substrate 111 and the first circuit wiring layer 117, wherein the insulating layer 116 is made of a resin material such as epoxy resin, and fillers such as alumina and aluminum carbide are filled inside the resin material to improve thermal conductivity. In order to increase the thermal conductivity, the shape of these fillers may be angular, and in order to avoid the risk of the fillers damaging the contact surfaces of the electronic components arranged on the surface thereof, the fillers may be spherical, angular, or a mixture of angular and spherical. The first circuit wiring layer 117 may be formed by etching a copper foil or by printing a paste-like conductive medium, which may be a conductive material such as graphene, solder paste, or silver paste. The surface of the first circuit wiring layer 117 is provided with a plurality of component mounting locations for mounting a plurality of first electronic components, where the first electronic components include components with large heat generation, such as power devices, the power devices include switching tubes, such as IGBT tubes 112(Insulated Gate Bipolar transistors) or MOS (metal oxide semiconductor), in this embodiment, the IGBT tubes 112 also include fast recovery diodes, and the power consumed by the operation thereof is large and large, and therefore the first substrate 111 is made of a material with high heat transfer efficiency, such as aluminum, so as to improve the heat transfer efficiency of the first electronic components. The first electronic component may further include a component generating a small amount of heat, such as a low-power resistor 118 and a capacitor.
In some embodiments of the present invention, the second substrate 121 may be made of an insulating material, for example, the second substrate 121 is a glass fiber board, and a second circuit wiring layer (not shown) formed of a metal material such as copper foil is disposed on a surface thereof. A plurality of component mounting sites are also provided on the surface of the second circuit wiring layer for mounting a second electronic component. Wherein the second electronic component generates heat more than the first electronic component, typically low power components such as driver chip 123, resistor 122 and capacitor. Since the power consumption of the second electronic component is much lower than that of some components with large heat generation, such as power devices, in the first electronic component, for example, the power of the power devices may exceed 30W, and the power of the driving chip 123 is less than 1W, the heat generation thereof is significantly reduced, and the heat dissipation thereof need not be considered during the operation thereof, so that the second substrate 121 may be made of a material with lower heat conduction efficiency than the first substrate 111, such as a glass fiber board, to reduce the cost.
Further, an auxiliary heat sink 113 is also provided between the first circuit wiring layer 117 and the first electronic component. Because some of the first electronic components generate a large amount of heat and consume a high amount of power, better heat transfer to the electronic components is achieved. The auxiliary heat sink 113 is preferably provided between these electronic components such as the power devices, which generate a large amount of heat, and the first circuit wiring layer 117.
In some embodiments of the present invention, the leads of the first lead group 150 and the second lead group 160 are generally made of copper or other metals, the copper surface is formed with a nickel-tin alloy layer by electroless plating and electroplating, the thickness of the alloy layer is generally 5 μm, and the plating layer can protect the copper from corrosion and oxidation and can improve solderability. The material of the pin can adopt a C194(-1/2H) plate (chemical composition: Cu (97.0), Fe (2.4), P (0.03) and Zn (0.12)) or a KFC (-1/2H) plate (chemical composition: Cu (99.6), Fe (0.1 (0.05-0.15) and P (0.025-0.04)), the C194 or KFC plate with the thickness of 0.5mm is processed through a stamping or etching process, the nickel plating thickness is 0.1-0.5um firstly, and the tin plating thickness is 2-5um secondly, so that the processing of the pin is completed.
Further, in some embodiments of the present invention, a green oil layer 115 may be further coated on the surface of the first circuit wiring layer 117 and/or the second circuit wiring layer on which no electronic component is disposed, so as to prevent the circuit wiring layers from being oxidized by contamination, and also to enhance the withstand voltage between the wirings of these circuit wiring layers.
In some embodiments of the present invention, as shown in fig. 4 and 5, the semiconductor circuit 100 further includes a plurality of bonding wires, and each bonding wire includes a first bonding wire 114 disposed on the first circuit substrate assembly 110 and a second bonding wire 124 disposed on the first circuit substrate assembly 120, the first bonding wires 114 being disposed on the first circuit substrate assembly 110 and the second circuit substrate assembly 120, respectively, for connecting the plurality of first electronic components, the first circuit wiring layer 117, and the first pin group 150; the second bonding wires 124 connect the plurality of second electronic components, the second circuit wiring layer, and the second lead group 160. For example, the first bonding wire 114 may connect between the first electronic components, or may connect between the first electronic components and the trace on the first circuit wiring layer 117, between the pad on the first circuit wiring layer 117 and the pin of the first pin group 150, and the second bonding wire 124 may connect between the second electronic components, or may connect between the second electronic components and the trace on the second circuit wiring layer, or may connect between the pad on the second circuit wiring layer and the pin of the second pin group 160. The bonding wires are typically gold wires, copper wires, hybrid gold-copper wires, 38 μm or less fine bonding wires of 38 μm, 100 μm or more coarse bonding wires of 100 μm.
In some embodiments of the present invention, as shown in fig. 2 to 5, the first lead group 150 and the second lead group 160 are disposed side by side, and the first lead group 150 is bent upward and the second lead group 160 is bent downward. The first lead group 150 and the second lead group 160 are arranged along a straight line because the leads are correspondingly disposed on one side or both sides of the first substrate 111 and the second substrate 121, respectively. The lead groups are disposed on one side of the first substrate 111 and the second substrate 121 in the scheme shown in the above figure. Specifically, there are two ways of arranging the first lead group 150 and the second lead group 160 in the figures, and in the schemes shown in fig. 2 and fig. 5, the first lead group 150 and the second lead group 160 are arranged side by side, i.e. in a straight line, except that the bending directions of the leads are opposite. In the solution shown in fig. 3 and 4, the first lead group 150 and the second lead group 160 are disposed side by side in the thickness direction of the semiconductor circuit 100, and the lead bending directions of the two are opposite to each other, and the two lead groups are spaced apart by a certain distance, which is generally smaller than and solves the distance between the first substrate 111 and the second substrate 121. Both of these ways are preferred embodiments of the first pin group 150 and the second pin group 160 side by side.
In some embodiments of the present invention, as shown in fig. 4 and 5, the fixing posts 130 are disposed relatively close to the sides of the first and second substrates 111 and 121. The fixing posts 130 may be made of metal and used for supporting the first substrate 111 and the second substrate 121, and at least two fixing posts 130 are respectively disposed at two opposite sides close to the first substrate 111 and the second substrate 121, so as to occupy as few areas of the surfaces of the first substrate 111 and the second substrate 121 where electronic components are disposed as possible, thereby facilitating wiring of circuit wiring layers and placing of corresponding electronic components.
In some embodiments of the present invention, the electronic components respectively disposed on the first substrate 111 and the second substrate 121 operate in different voltage environments, that is, the first electronic component operates in a high voltage environment, and the second electronic component operates in a low voltage environment. Because the first electronic component is a high-power-consumption component, which generates a large amount of heat, such as the IGBT112, it is generally applied to an inverter circuit, and operates in a high-voltage environment, such as a dc voltage, which may reach 300V, and the second electronic component is mainly a driving circuit for driving these power devices of the first electronic component, and is mainly composed of the driving chip 123, and operates in a low-voltage environment, such as a working voltage, which is only 5V, so that the high-voltage and low-voltage operating circuits are correspondingly isolated by the first substrate 111 and the second substrate 121, thereby reducing the interference of the high-voltage circuit with the ground voltage circuit, and improving the operating reliability of the entire circuit while improving the density of the electronic components of the unit volume of the semiconductor circuit 100.
Further, in some embodiments of the present invention, the sealing layer 140 is formed of resin, and is molded using thermosetting resin by a transfer molding method or thermoplastic resin by an injection molding method. The sealing layer 140 is half-coated, that is, the sealing layer covers both surfaces of the mounting surface of the first substrate 111 and the second substrate 121, the heat dissipation surface of the first substrate 111 is exposed from the sealing layer 140, and most of the lengths of the first lead group 150 and the second lead group 160 are exposed from the sealing layer 140. When the semiconductor circuit 100 is mounted in an application, a heat sink may be further disposed on the heat dissipation surface of the first substrate 111, such that the surface of the heat sink is in close contact with the heat dissipation surface, thereby better dissipating heat generated by the power device disposed on the first substrate 111 through the heat sink.
The present invention further provides an electric control board, as shown in fig. 6 and 7, the electric control board is provided with the semiconductor circuit 100 having the double-layer structure mentioned in the above embodiment, the electric control board further includes an upper electric control board 300 and a lower electric control board 400 which are disposed up and down, the semiconductor circuit 100 is disposed between the upper electric control board 300 and the lower electric control board 400, and the first pin and the second pin of the semiconductor circuit 100 are respectively connected to the upper electric control board 300 and the lower electric control board 400.
Specifically, the first pin group 150 of the semiconductor circuit 100 is bent upward and connected to the first circuit substrate assembly 110, and the first pin group 150 is electrically connected to the first PCB in the upper electronic control board 300; the second lead group 160 is bent downward and connected to the second circuit substrate assembly 120, and the second lead group 160 is electrically connected to the second PCB in the lower electronic control board 400. The first electronic component on the first circuit substrate assembly 110 is at least partially a power device with a large heat generation amount, such as an IGBT112, which operates in a high voltage environment, such as 300V, and the second electronic component on the second circuit substrate assembly 120 generates much lower heat than the power device, and operates in a second voltage environment, such as 5V, so that the upper electronic control board 300 and the lower electronic control board 400 connected to each other also operate in the high voltage environment and the low voltage environment, respectively, so that the whole electronic control board realizes the isolation of the high voltage circuit area and the low voltage circuit area through the two electronic control boards, thereby reducing the interference to the low voltage circuit. Moreover, the semiconductor circuit 100 based on the two complete pin group structures is correspondingly installed in the two electric control boards which are overlapped up and down, so that the occupied area of the whole electric control board is effectively reduced, and the miniaturization of the electric control board is facilitated.
Further, the upper electronic control board 300 is further provided with a metal heat sink 310, and the heat sink is disposed on the heat dissipation surface of the first substrate 111 of the semiconductor circuit 100, and the two are closely attached to each other, so as to enhance heat dissipation of the semiconductor circuit 100. Other electronic components working in a high-voltage environment, such as related components of a PFC circuit, a switching power supply circuit, and the like, are further disposed on the upper electronic control board 300, and the specific electronic components include an inductor 320, an electrolytic capacitor 330, and the like. The lower electronic control board 400 is further provided with other electronic components operating in a low-voltage environment, such as the MCU410 in fig. 6 and other low-voltage integrated circuits.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be interconnected within two elements or in a relationship where two elements interact with each other unless otherwise specifically limited. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. A semiconductor circuit of a double-layer structure comprising a first circuit substrate assembly, a second circuit substrate assembly and a sealing layer disposed one above the other, wherein a plurality of fixing posts are disposed between the first circuit substrate assembly and the second circuit substrate assembly, wherein,
the first circuit substrate assembly includes:
the first substrate comprises a mounting surface and a heat dissipation surface, wherein the mounting surface is provided with a first circuit wiring layer;
a plurality of first electronic elements provided on the first circuit wiring layer;
the first pin group is arranged on at least one side of the first substrate, and one end of each pin of the first pin group is connected with the first circuit wiring layer;
the second circuit substrate assembly includes:
a second substrate, a surface of which is provided with a second circuit wiring layer;
a plurality of second electronic elements provided in the second circuit wiring layer;
a second pin group, wherein the second pin group is arranged on at least one side of the second substrate, and one end of each pin of the second pin group is connected with the second circuit wiring layer;
the overall heat generation of the plurality of first electronic elements is larger than the heat generation of the plurality of second electronic elements, and the bending directions of the first pin group and the second pin group are opposite.
The sealing layer covers the first circuit substrate assembly and the second circuit substrate assembly, the first pin group and the second pin group are respectively exposed from the side face of the sealing layer, and the heat dissipation face of the first substrate is exposed from the surface of the sealing layer.
2. The semiconductor circuit according to claim 1, wherein a thermal conduction efficiency of the first substrate is higher than a thermal conduction efficiency of the second substrate.
3. The semiconductor circuit according to claim 2, wherein the first substrate is a metal substrate and the second substrate is a glass fiber board.
4. The semiconductor circuit according to claim 1, wherein the first lead group and the second lead group are arranged side by side, and the first lead group is bent upward and the second lead group is bent downward.
5. The semiconductor circuit according to claim 4, wherein the first pin group and the second pin group are arranged side by side in the left-right direction.
6. The semiconductor circuit according to claim 4, wherein the first pin group and the second pin group are independent two groups and are arranged up and down in a thickness direction of the semiconductor circuit.
7. The semiconductor circuit of claim 1, wherein the fixed posts are disposed relatively close to sides of the first and second substrates.
8. The semiconductor circuit according to claim 3, wherein the second electronic component comprises a driver chip and a resistance-capacitance element.
9. The semiconductor circuit according to claim 3, wherein the first electronic component operates in a high voltage environment and the second electronic component operates in a low voltage environment.
10. An electric control board, characterized in that the electric control board is provided with the semiconductor circuit according to any one of claims 1 to 9, the electric control board further comprises an upper electric control board and a lower electric control board which are arranged up and down, the semiconductor circuit is arranged between the upper electric control board and the lower electric control board, and the first pin group and the second pin group of the semiconductor circuit are respectively connected with the upper electric control board and the lower electric control board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210699367.1A CN115084113A (en) | 2022-06-20 | 2022-06-20 | Semiconductor circuit with double-layer structure and electric control board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210699367.1A CN115084113A (en) | 2022-06-20 | 2022-06-20 | Semiconductor circuit with double-layer structure and electric control board |
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| Publication Number | Publication Date |
|---|---|
| CN115084113A true CN115084113A (en) | 2022-09-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210699367.1A Pending CN115084113A (en) | 2022-06-20 | 2022-06-20 | Semiconductor circuit with double-layer structure and electric control board |
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| CN (1) | CN115084113A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117320316A (en) * | 2023-11-28 | 2023-12-29 | 江苏永鼎股份有限公司 | Chip mounting equipment and mounting method |
-
2022
- 2022-06-20 CN CN202210699367.1A patent/CN115084113A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117320316A (en) * | 2023-11-28 | 2023-12-29 | 江苏永鼎股份有限公司 | Chip mounting equipment and mounting method |
| CN117320316B (en) * | 2023-11-28 | 2024-04-09 | 江苏永鼎股份有限公司 | Chip mounting equipment and mounting method |
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