CN115083487B

CN115083487B - Memory device, storage method, reading apparatus and reading method

Info

Publication number: CN115083487B
Application number: CN202211015082.8A
Authority: CN
Inventors: 吴臻志; 祝夭龙
Original assignee: Beijing Lynxi Technology Co Ltd
Current assignee: Beijing Lynxi Technology Co Ltd
Priority date: 2022-08-23
Filing date: 2022-08-23
Publication date: 2022-12-06
Anticipated expiration: 2042-08-23
Also published as: CN115083487A

Abstract

The disclosure provides a storage device, a storage method, a reading device and a reading method, and belongs to the technical field of computers. The memory device includes: at least two binary storage units for storing a sign value and an exponent value of floating point data; at least one multivalued storage unit for storing valid digital values of floating point data. The overall accuracy of the memory device can be improved according to the embodiment of the disclosure.

Description

Memory device, storage method, reading apparatus and reading method

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a memory device, a storage method, a reading apparatus, and a reading method.

Background

With the rapid development of computer technology, a novel Non-Volatile memory (NVM) has the advantages of high speed, high density and Non-volatility, and provides a hardware basis with higher performance for neural network calculation; in the nonvolatile memory, multi-value data can be stored in a single storage unit in the memory through a multi-value storage technology, so that the storage density of the nonvolatile memory is improved.

When multi-value data is stored in a single memory cell, written data often deviates from expected data to some extent, so that the written data is not expressed accurately, and the overall precision of the memory is affected.

Disclosure of Invention

The present disclosure provides a memory device, a storage method, a reading apparatus, and a reading method, which can improve the overall accuracy of the memory device.

In a first aspect, the present disclosure provides a memory device comprising: at least two binary storage units for storing a sign value and an exponent value of floating point data; at least one multivalued storage unit for storing valid digital values of the floating point data.

In a second aspect, the present disclosure provides a data storage method, including: storing the sign value and the exponent value of the floating point data to at least two binary storage units in a predetermined storage device; storing the valid digital values of the floating point data to at least one multivalued storage location in the predetermined storage device.

In a third aspect, the present disclosure provides a data storage method, including: the valid digital values of the floating-point data are stored to a multivalued storage unit in a predetermined storage device.

In a fourth aspect, the present disclosure provides a data storage method, including: storing a sign value and an exponent value of floating point data to at least two binary storage units in a given storage device is provided by the present disclosure.

In a fifth aspect, the present disclosure provides a reading apparatus for reading a memory cell array; the memory cell array includes: at least one word line, a plurality of bit lines, at least one group of memory cells and a gate; the reading device comprises a numerical value judging module and a register; wherein the at least one word line is arranged in sequence along a first direction; the plurality of bit lines are arranged in a cross mode with the at least one word line along a second direction, and the second direction is perpendicular to the first direction; the group of memory cells comprises at least two binary memory cells and at least one multi-valued memory cell, each memory cell in the same group of memory cells is respectively positioned at the intersection position of the same word line and different bit lines, and two ends of each memory cell are respectively connected with the corresponding word line and the corresponding bit line; the gate is connected to each word line, and the gate is configured to: determining a selected word line and a selected bit line according to a read address in a received read instruction, and selecting a binary memory cell and a multi-value memory cell connected to an intersection of the selected word line and the selected bit line as a selected binary memory cell and a selected multi-value memory cell; the numerical value judging module is used for judging the sign value and the exponent value of the floating point data stored in the selected binary storage unit, judging the effective numerical value of the floating point data stored in the selected multi-value storage unit, and sending the sign value, the exponent value and the effective numerical value to the register; and the register is used for splicing the received symbolic value, the exponent value and the effective digital value to obtain read floating point data.

In a sixth aspect, the present disclosure provides a data reading method comprising: determining a selected word line and a selected bit line in a memory cell array according to a read address in a received read instruction through a gate, and selecting a binary memory cell and a multi-value memory cell connected to the intersection of the selected word line and the selected bit line as a selected binary memory cell and a selected multi-value memory cell; judging the sign value and the exponent value of the floating point data stored in the selected binary storage unit through a numerical value judging module, judging the effective numerical value of the floating point data stored in the selected multi-value storage unit, and sending the sign value, the exponent value and the effective numerical value to a specified register; and splicing the received symbolic value, the exponent value and the effective digital value through the register to obtain read floating point data.

In the memory device provided by the present disclosure, at least two binary storage units store a sign value and an exponent value of floating point data, and at least one multivalued storage unit stores a valid digital value of the floating point data; because the small floating change of the effective digital value of the floating point data can not influence the overall precision of the floating point data, and the small error of the sign value and the exponent value of the floating point data can cause the precision of the floating point data to obviously change, the storage structure of the storage device stores the effective digital value of the floating point data through the multi-value storage unit, saves the storage space, stores the sign value and the exponent value of the floating point data through the binary storage unit, is favorable for reducing the influence of the inaccurate characteristic of multi-value storage on the overall precision of the floating point data, and improves the overall precision of the storage device.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a data structure of a floating point number according to an exemplary embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a memory device provided by an embodiment of the present disclosure;

fig. 3 is a flowchart of a data storage method according to an embodiment of the present disclosure;

FIG. 4 illustrates a flow diagram of a data storage method of an embodiment of the present disclosure;

FIG. 5 is a flow chart illustrating a data storage method according to an embodiment of the disclosure;

FIG. 6 is a schematic diagram of a memory device according to an embodiment of the present disclosure;

FIG. 7 shows a schematic structural diagram of a reading apparatus according to an embodiment of the disclosure;

FIG. 8 shows a more detailed structural schematic diagram of a reading device of an embodiment of the present disclosure;

FIG. 9 is a flowchart illustrating a data reading method according to an embodiment of the disclosure;

fig. 10 illustrates a flowchart of a data reading method of an exemplary embodiment of the present disclosure;

FIG. 11 is a block diagram of a data storage device provided by an embodiment of the present disclosure;

fig. 12 is a block diagram of an electronic device provided in an embodiment of the present disclosure.

Detailed Description

To facilitate a better understanding of the technical aspects of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, wherein various details of the embodiments of the present disclosure are included to facilitate an understanding, and they should be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, … … specify the presence of features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the disclosed embodiments, neuromorphic computation aims at achieving Artificial Intelligence (AI) by mimicking the mechanisms of neurons and synapses that make up the human brain. The synapse device can adjust the self connection weight through the neural transmission signal to realize adaptivity, thereby quickly completing the brain-like calculation, being suitable for processing the informatization problem and/or the unstructured information, and having outstanding potential in the aspect of realizing the hardware of the neural network.

The novel synapse devices may for example comprise one or more of the following non-volatile memory devices: memristors (memrisors), phase Change Memories (PCMs), resistive Random Access Memories (RRAMs).

The memristor is a resistance switch which dynamically changes the internal resistance state based on the history of memorizing applied voltage or current, has ultra-small size, extremely fast erasing speed, ultra-high erasing service life, multi-resistance state switch characteristics and good Complementary Metal-Oxide-Semiconductor (CMOS) compatibility, has the advantages of multi-valued characteristics, reliability and the like, has application potential as a synapse device, and can be used for constructing a large-scale neural network.

PCM utilizes non-volatile solid-state memory technology, with reversible, thermally-assisted switching of phase change materials between states having different resistances. The basic memory cell can be programmed to a number of different states or levels exhibiting different resistance characteristics, and the programmable cell states can be used to represent different data values, thereby allowing information to be stored.

RRAM is a memory device that can store various information by using a nonvolatile memory technology, in which the resistance of a material is changed between a high resistance state and a low resistance state according to a difference in voltage applied to a Metal Oxide (Metal Oxide), thereby opening or blocking a current flow path.

The nonvolatile memory has higher integration density, has higher access speed and lower power consumption compared with a Flash memory (Flash) device, and is more suitable for data access close to a processor; also, the memory cell of the above nonvolatile memory can represent multi-values using resistance variable characteristics, instead of binary values of 0 and 1 of the conventional memory cell. Based on the advantages of the nonvolatile memory such as multi-valued characteristics and reliability, the novel synapse device is considered as one of devices for improving the calculation energy efficiency of the neural network, and can be used for constructing a large-scale neural network.

It should be understood that the novel synapse device described above may also be other non-volatile memories; in practical application, the method can be selected and used according to actual needs.

In the embodiment of the disclosure, the multivalued memory cell can express different amplitudes (representing different storage data) on one memory cell of the memory through different resistance values. At present, because the amplitude expression of the synapse device is not completely accurate, the written amplitude often has certain deviation from the expected amplitude, and resistance change drift can occur along with temperature and time, and the phenomenon of inaccurate expression is more obvious especially when more multi-level resistance values need to be expressed on one memory cell.

In some embodiments, memory cells in a memory device may correspond to multiple resistance states, each corresponding to a non-overlapping range of resistances. That is, the value of the data stored in the memory cell is determined by the resistance state corresponding to the resistance range in which the resistance of the memory cell is located. In the disclosed embodiments, a plurality may represent greater than or equal to two.

In the disclosed embodiment, the binary memory cell may be a memory cell for storing two values of 0 and 1.

For a binary memory cell, the memory cell has two memory states which are respectively identified by logic '1' and '0', and the memory capacity of each binary memory cell is 1bit; taking a binary memory cell as an example of a resistive memory cell, the memory cell can correspond to two resistance states, namely a first resistance state and a second resistance state. The resistance range corresponding to the first resistance state may be, for example, greater than or equal to the predetermined resistance r11 and less than or equal to the predetermined resistance r12, and the resistance range corresponding to the second resistance state may be, for example, greater than the predetermined resistance r12 and less than or equal to the predetermined resistance r13; the predetermined resistance r13 is greater than the predetermined resistance r12, and the predetermined resistance r12 is greater than the predetermined resistance r11.

If the resistance value of the storage unit is in the resistance value range corresponding to the first resistance value state, the value of the data stored in the storage unit is in the first resistance value state; and if the resistance value of the storage unit is in the resistance value range corresponding to the second resistance value state, the value of the data stored in the storage unit is in the second resistance value state. Specifically, if the first resistance state and the second resistance state are 0 and 1, the specific value of the data stored in the memory cell can be determined.

In this example, the ranges of the resistance value ranges corresponding to each resistance value state may be the same or different in size (i.e., the resistance value ranges may be arranged at equal intervals or at unequal intervals). That is, in the above example, the predetermined resistance value r12 may be an intermediate value between the predetermined resistance value r11 and the predetermined resistance value r13, or may be another value between the predetermined resistance value r11 and the predetermined resistance value r 13.

In the disclosed embodiments, the multivalued memory cell may be a memory cell that utilizes a resistance variable feature to characterize multiple values.

In some embodiments, the multi-value storage unit can record one multi-value data on one storage unit of the memory, and can convert the multi-value data into binary data with more than one bit, thereby increasing the storage density of the memory and improving the storage capacity.

For a multivalued memory cell, the memory cell may correspond to multiple (greater than two) resistance states, each resistance state corresponding to a non-overlapping resistance range; the maximum value of the resistance range corresponding to the kth resistance state is larger than the maximum value of the resistance range corresponding to the kth-1 resistance state, and k is an integer larger than 2. The ranges of the resistance value ranges corresponding to each resistance value state may be the same or different (i.e., the resistance value ranges are arranged at equal intervals or at unequal intervals). The method for determining the specific value of the data stored in the multi-value memory cell according to the resistance value of the memory cell is the same as the method for determining the specific value of the data stored in the memory cell according to the resistance value of the memory cell in the binary memory cell, and is not described herein again.

In some embodiments, the number of resistance value ranges in a memory cell may be referred to as an order, and the data stored by the memory cell may be referred to as a corresponding order precision to be expressed. When the problem of write bias on a storage unit in a synapse device described in the above embodiment occurs, since a binary storage unit can express 2-order precision, that is, the value of the storage unit is only 0 and 1, the error probability is extremely small; when a multi-valued memory cell is to express, for example, 16-order precision, the number 10 is expected to be expressed, and the number that may be read is one of 8,9, 10, 11; it can be seen that when more levels of resistance are expressed on the memory cell, the more significant the phenomenon of inaccurate expression is.

In the related art, electronic synapse devices can implement the function of simulating biological synapses to change weights under impulse stimulation, currently, based on such synapse device neural networks, a definite integer weight precision, for example, 4-Bit (Bit) integer, is usually adopted to express a 16-order precision, and a complementary unit pair is adopted to realize positive and negative weight expression, that is, a pair of units respectively represents positive/negative weights, and a differential value is read out as a weight value. Neither of these approaches can achieve a wider range of synaptic representations, such as data precision in floating point number format.

In the disclosed embodiment, a number can be represented in a computer by scientific notation. Any number can be expressed as:

floating point number format of (2). Wherein, N represents any number, S is a sign bit, the value of 0 or 1 is selected to determine the sign of a number, 0 represents positive, and 1 represents negative; r is a base number, which means that the decimal number R is 10 and the binary number R is 2; e is an index, expressed as an integer; m is a significant number, represented by a decimal number, and may also be referred to as a mantissa or decimal number.

As a specific example, 8.25 is 82.5 in decimal; wherein the sign bit S takes a value of 0, the radix R takes a value of 10, the exponent bit e takes a value of-1, and the significant digit M takes a value of 82.5;8.25 binary representation is 1000.01 for use in a computer

Further expressed in a floating-point number format in binary, namely: 1.00001 book

The sign bit S takes a value of 0, the radix R takes a value of 2, the exponent e takes a value of 0, and the significant digit M takes a value of 1.00001. Thus, in a computer a binary digit is represented by a floating-point number, since the radix is already possibleThe determination is 2, so that only the values of the sign bit, the exponent bit, and the significand bit in the floating point number need to be determined.

In some embodiments, the sign bit S, the exponent bit e, and the significand bit M may be referred to as a sign field, an exponent field, and a significand field; the value of the sign bit S, the value of the exponent bit e, and the value of the significand bit M may be referred to as a sign value, an exponent value, and a significand value.

FIG. 1 illustrates a floating point number data structure of an exemplary embodiment. In fig. 1, a floating point number is identified by 16 bits (Bit), and the sign Bit, exponent Bit, and significand Bit of the floating point number may be padded into bits in the data structure according to a predetermined rule.

As shown in fig. 1, in some alternative embodiments, the region of the data structure used to fill in the symbol values may be referred to as the symbol field, the region used to fill in the exponent values may be referred to as the symbol field, and the region used to fill in the significant digit values may be referred to as the significant digit field. And under the condition that the sign bit S occupies 1bit, the exponent e occupies 8 bits and the effective number occupies 7 bits according to the preset rule, filling the sign bit, the exponent bit and the effective number bit in the floating point number into corresponding bit bits in the data structure according to the preset rule, and thus obtaining the data structure of the 16-bit floating point number.

In the disclosed embodiments, the data format of Floating Point numbers includes, but is not limited to, floating Point (Float) formats such as Float16, float32, and Truncated Floating Point (BF 16) formats. The truncated floating-point number is also referred to as Brain Float (Brain Float).

For example, in fig. 1, the 16-Bit (Bit) floating point number is in BF16 floating point format, and the number in BF16 floating point format may be expressed as: 1 sign bit, 8 exponent bits, and 7 significand bits.

It should be understood that the data format of the floating point number may also be a floating point format such as a single precision floating point number, a double precision floating point number, a half precision floating point number, and so on. The single-precision floating-point number format (denoted as FP 32) can occupy 4 bytes, and has 32 bits, wherein 1bit is a sign bit, 8 bits are exponent bits, and 23 bits are mantissa bits; the double precision floating point number format (denoted FP 64) may occupy 8 bytes, with 1bit being the sign bit, the exponent bit being 11 bits, and the significand being 52 bits, thus greatly expanding the range and size of numbers it can represent. The half precision floating point number format (FP 32) occupies two bytes, and 16 bytes are total, wherein 1bit is a sign bit, 5 bits are exponent bits, and 10 bits are valid digit bits; compared with FP32, the memory consumption of FP16 is only 1/2, therefore FP16 is a data format more suitable for AI calculation at the mobile terminal side.

In some embodiments, the BF16 floating point format is a truncated 16-bit version of a 32-bit single precision floating point format that retains 8 exponent bits, but reduces the precision of significant digits to 8 bits to save memory, bandwidth, and processing resources; the BF16 floating point format is primarily applicable to machine learning and near sensor computing applications. In some embodiments, the single-precision and double-precision floating point values may be converted to BF16 floating point format for accelerating machine learning and near sensor computation operations.

As can be seen from the data format of the floating point number, in the floating point format of the data, the more exponent bits, the fewer mantissa bits, the larger the range of representation, but the lower the precision; conversely, the smaller the exponent bits, the larger the mantissa bits, the smaller the range of representation, but the better the accuracy. Thus, the floating-point number format described above, such as float16, float32, bfloat16, FP32, FP64, or FP16, the number in the floating-point number format being used to represent the total number of digits of the number represented by the floating-point number format, with most of the digits being assigned to the mantissa, thereby providing greater precision.

The embodiment of the disclosure provides a storage device and a data storage method, which are used for storing floating point data and improving the overall precision of the storage device.

The data storage method according to the embodiment of the present disclosure may be executed by an electronic device such as a terminal device or a server, the terminal device may be a User Equipment (UE), a mobile device, a User terminal, a cellular phone, a cordless phone, a Personal Digital Assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, or the like, and the method may be implemented by a processor calling a computer-readable program instruction stored in a memory. Alternatively, the method may be performed by a server.

Fig. 2 is a schematic structural diagram of a memory device according to an embodiment of the present disclosure.

As shown in fig. 2, the memory device includes: at least two binary storage units 210 for storing a sign value and an exponent value of floating point data; at least one multi-valued storage unit 220 for storing valid digital values of floating point data.

The storage device provided by the embodiment of the disclosure is provided, wherein at least two binary storage units are used for storing a symbolic value and an exponent value of floating point data, and at least one multi-value storage unit is used for storing an effective digital value of the floating point data; because the small floating change of the effective digital value of the floating point data can not influence the overall precision of the floating point data, and the small error of the symbolic value and the exponential value of the floating point data can cause the precision of the floating point data to obviously change, the storage structure of the storage device stores the effective digital value of the floating point data through the multi-value storage unit so as to save the storage space, stores the symbolic value and the exponential value of the floating point data through the binary storage unit, is favorable for reducing the influence of the inaccurate characteristic of multi-value storage on the overall precision of the floating point data, and improves the overall precision of the storage device.

In some embodiments, each multivalued memory cell includes a variable resistance resistor for storing a valid digital value.

In this embodiment, the information storage form of the multivalued memory cell may be a resistance-variable storage; that is, by adjusting the resistance value of the multivalue memory cell, the effective digital value stored by the multivalue memory cell is represented by the adjusted resistance value; the information storage form of the binary memory unit can be resistive memory or non-resistive memory.

For example, if the information storage form of the binary memory cell is resistive random access memory, it indicates that 0 and 1 binary values can be expressed on one binary memory cell by different resistance values, so as to indicate the symbol value or the index value stored in the binary memory cell by the adjusted resistance value.

Illustratively, the information storage form of the binary memory cell may be non-resistance change type storage, for example, phase change type storage or magnetic change type storage. Phase-change memory may be a memory technology that stores information by using a difference in conductivity after conversion between crystalline and amorphous states of a material; magneto-rheological storage may be a storage technology that utilizes magnetization states to store information.

It should be understood that in some alternative embodiments, the information storage form of the multivalue memory cell may also be a non-resistance change type memory. That is to say, the information storage form of the multi-value memory cell and the information storage form of the binary memory cell may have more flexible combination modes, and at least one of the multi-value memory cell and the binary memory cell may be a non-resistance change type memory or a resistance change type memory, and may be specifically set according to actual needs.

In some embodiments, the numerical range of valid digital values that the at least one multi-valued storage unit is capable of storing is less than or equal to a numerical threshold, the numerical threshold corresponding to a read order of the resistance value of the at least one multi-valued storage unit, and the read order of the resistance value being determined according to a precision requirement of the floating point data.

In this embodiment, when the multi-value storage unit is used to store the valid digital value of the floating point data, the reading order of the resistance value of the multi-value storage unit can be determined according to the precision requirement of the floating point data, and the numerical range of the valid digital value stored in the multi-value storage unit can be further determined. Therefore, the numerical range of the effective numerical value that the multivalued storage unit can store can be set appropriately according to the precision requirement of the floating point data to be stored.

In the embodiment of the disclosure, the multi-value memory cell has more resistance states than the binary memory cell, and the more resistance states of the variable resistance of the memory cell, the smaller the width of the resistance interval to which the resistance value corresponding to each resistance state belongs, when the memory cell is subjected to temperature and time and subjected to resistive drift (resistance value change), the greater the probability that the resistance value of the memory cell exceeds the resistance interval to which the resistance value corresponding to the current resistance state belongs, and the greater the probability that the resistance value of the memory cell changes once the resistance state of the memory cell changes, the greater the probability that the value stored in the memory cell changes along with the resistance state. Based on the above, it can be known that, compared with a binary memory cell, a multi-value memory cell has a weaker resistance state interference resistance and a poorer stability of stored data.

When a value is stored through the binary storage unit, the resistance value state of the variable resistance value is only two, the width of the resistance value interval to which the resistance value corresponding to each resistance value state belongs is relatively large, and when the binary storage unit stores the value, the error possibility of the adjusted resistance value of the binary storage unit is low due to the fact that the width of the corresponding resistance value interval is relatively large, so that the accuracy of storing the value through the variable resistance value on the binary storage unit is high, and data storage through the binary storage unit can be generally regarded as accurate storage.

Correspondingly, when a numerical value is stored through the multi-value storage unit, because the resistance value states of the variable resistance values of the multi-value storage unit are more, the width of the resistance value interval to which the resistance value corresponding to each resistance value state belongs is smaller, and when the numerical value is stored through the multi-value storage unit, because the width of the corresponding resistance value interval is relatively smaller, the error possibility of the adjusted resistance value of the multi-value storage unit is higher, therefore, the data storage through the multi-value storage unit can be regarded as approximate storage, and when the numerical value is stored through the variable resistance values on the multi-value storage unit, the phenomenon of inaccurate numerical value expression is more obvious.

Through the analysis, compared with the storage stability and the numerical expression accuracy of the multi-value storage unit, the data storage with high stability and higher accuracy can be realized by adopting the binary storage unit.

In some embodiments, the at least two binary memory cells include: 1 symbol value storage unit and k exponent value storage units, k being an integer greater than or equal to 1; the sign value storage unit is used for storing the sign value of the floating point data; the exponent value storage unit is used for storing an exponent value of floating point data.

In this embodiment, since the sign value of the floating point data is 0 or 1, in at least two binary storage units of the storage device, the storage of the sign value can be realized by 1 binary storage unit, and then the storage of the exponent value of the floating point data is realized by other binary storage units in the storage device, so that the high-stability and accurate storage of the sign value and the exponent value in the floating point format data based on the binary storage units is realized.

In some embodiments, the memory device is a synapse device, and the number of multivalued memory cells in the synapse device is 1. In this embodiment, only one multivalued storage unit in a predetermined storage device can be used to store valid data in floating point data, thereby achieving approximate value storage and saving storage space.

According to the storage device of the embodiment of the present disclosure, a sign value and an exponent value of floating point data are stored through at least two binary storage units, and a valid digital value of the floating point data is stored through at least one multivalued storage unit; because the small floating change of the effective digital value of the floating point data can not influence the overall precision of the floating point data, and the small error of the sign value and the exponent value of the floating point data can cause the precision of the floating point data to obviously change, the storage structure of the storage device stores the effective digital value of the floating point data through the multi-value storage unit, saves the storage space, stores the sign value and the exponent value of the floating point data through the binary storage unit, is favorable for reducing the influence of the inaccurate characteristic of multi-value storage on the overall precision of the floating point data, and improves the overall precision of the storage device.

Fig. 3 is a flowchart of a data storage method according to an embodiment of the present disclosure. Referring to fig. 3, the method includes the following steps.

And S310, storing the sign value and the exponent value of the floating point data into at least two binary storage units in a preset storage device.

In some embodiments, the data to be stored may be encoded in a floating point format in advance to obtain a sign value, an exponent value, and an effective digital value in the floating point format of the data; and a binary storage unit is adopted to store the sign value at the sign bit and the exponent value at the exponent bit in the floating-point format data, so that high stability and more accurate binary storage are realized.

S320, storing the effective digital value of the floating point data to at least one multivalued storage unit in a predetermined storage device.

In this step, a significant digital value is obtained from the floating-point format data, and in the floating-point format data, the significant digital value may be a value located in a significant digital bit of the floating-point format; the valid digital value is stored to a multivalued memory cell in a predetermined memory device.

The memory device of the embodiment of the present disclosure may include a binary memory cell, or may include a multi-value memory cell, where the multi-value memory cell may be a part of a plurality of memory cells included in a predetermined memory device.

In the embodiment of the disclosure, since the small floating change of the effective digital value of the floating point does not affect the overall precision of the floating point, the requirement of the effective digital value on the storage precision is low, and the single multi-value storage unit is considered to be larger than the numerical value range which can be stored by the single binary storage unit, so that the effective digital value of the floating point data is stored by using the multi-value storage units with a small number, so as to approximately store the effective digital value of the floating point data, and save the storage space of a predetermined storage device; and because the precision of the floating point data is obviously changed due to tiny errors of the symbol value and the exponent value of the floating point data, and the symbol value and the exponent value have higher requirements on storage precision, the symbol value and the exponent value are stored by using a binary storage unit in a preset storage device, so that the influence of inaccurate characteristics of multi-value storage on the overall precision of the floating point data can be reduced, and the overall precision of the storage device is improved.

The predetermined storage device in the embodiment of the present disclosure may be any nonvolatile storage device included in the synapse device described in the above embodiment, and is not described herein again.

In some embodiments, step S320 may specifically include the following steps.

S11, determining the excitation parameters corresponding to the effective digital values for the multi-valued memory cells.

In this step, the excitation parameter may be at least one of a pulse parameter, a voltage, a current, a magnetic field, for example. The pulse parameter may be, for example, at least one of the following parameter items: pulse amplitude, width, falling edge, and interval between pulses.

As an example, applying a predetermined voltage, current, and/or applied magnetic field to a memory cell may change the resistance of the memory cell; alternatively, a pulse corresponding to the specified pulse parameter may be applied to the memory cell to change the resistance of the memory cell. For example, applying a forward pulse and a reverse pulse to a memory cell to change the resistance of the memory cell.

And S12, adjusting the resistance value of the multivalue memory cell according to the corresponding excitation parameter, and expressing the effective digital value through the adjusted resistance value.

Through the above steps S11 and S12, in writing the valid digital value into the multivalued memory cell, the stimulus is applied to the multivalued memory cell in the memory device by the selected stimulus parameter for changing the resistance value of the multivalued memory cell, so that the valid digital value is represented by the changed resistance value. The value of the data stored in the memory cell is determined by the resistance state corresponding to the resistance range in which the resistance of the memory cell is located. When the resistance value of the multi-value storage unit reaches the resistance value state corresponding to the expected resistance value range, the current excitation can be stopped, the writing operation is ended, the expected effective digital value in the multi-value storage unit is obtained, and the storage of the effective digital value in the floating point format data through the multi-value storage unit in the preset storage device is achieved.

In some embodiments, each multivalued memory cell includes a resistance variable in resistance value; step S320 may specifically include: according to the precision requirement of floating point data, determining the reading order of the resistance value of each multivalued storage unit; determining the numerical range of the effective numerical value which can be stored by each multivalued storage unit according to the reading order; in the case where the numerical range of the valid numerical values of the floating point data is smaller than or equal to the numerical range of the valid numerical values that can be stored, the valid numerical values of the floating point data are stored to at least one multivalued storage unit in a predetermined storage device.

In this embodiment, when the multi-value storage unit is used to store the effective digital value of the floating point data, the reading order of the resistance value of the multi-value storage unit can be determined according to the precision requirement of the floating point data, and the numerical range of the effective digital value stored in the multi-value storage unit can be further determined, so that the effective digital value smaller than or equal to the numerical range of the effective digital value that can be stored, and the storage of the effective digital value that meets the precision requirement of the floating point data can be completed.

In some embodiments, the multi-valued memory cell includes different resistance value ranges, each resistance value range including at least one resistance value; the valid digital value corresponds to a resistance value within a resistance value interval in the multivalued memory cell.

In this embodiment, the resistance value ranges may not overlap, and different resistance value ranges represent different resistance value ranges corresponding to different data values to be stored in the multi-valued memory cell; the resistance value intervals can be equally spaced (the absolute value of the difference between the initial resistance value and the final resistance value of the resistance value interval is equal), or unequally spaced (the absolute value of the difference between the initial resistance value and the final resistance value of the resistance value interval is unequal), and the resistance value intervals can be specifically set by self-definition according to actual needs.

In some embodiments, in the predetermined memory device, the number of multivalued memory cells is less than a predetermined cell number threshold; the numerical range of the effective digital value which can be stored by the multi-value storage unit is less than or equal to a numerical threshold, the numerical threshold corresponds to the reading order of the resistance value of at least one multi-value storage unit, and the reading order of the resistance value is determined according to the precision requirement of floating point data.

In this embodiment, the memory device may include a plurality of memory cells therein, and the predetermined cell number threshold may be used to define a maximum number of multivalued memory cells in the memory device; illustratively, the predetermined cell count threshold may be an integer greater than 1. In the embodiment of the present disclosure, since the multivalued memory cell deviates from the expected stored data when different data is expressed by different resistance values on one cell, the multivalued memory cell realizes storage of unstable approximate values (hereinafter also referred to as approximate storage). In some embodiments, the smaller the number of multivalued memory cells in the memory device, the more a portion of the memory space occupied by the approximate memory in the memory device can be saved, so that stable storage of precise values (hereinafter also referred to as precise storage) can be achieved using another portion of the memory space.

In the embodiment of the present disclosure, for example, if the value range of the valid digital value that can be stored in the multi-value storage unit is 128, the multi-value storage unit may be referred to as a 128-value unit, and it is understood that the multi-value storage unit may store 128 different values (or 128 different values). It can be seen that, the larger the numerical range of the effective digital value stored in the multi-valued storage unit is, the larger the range that the effective digital value can represent is, and the smaller the corresponding data precision is; the smaller the numerical range of the significant digit value stored in the multivalued memory cell, the smaller the range that the significant digit bit can represent, and the higher the corresponding data accuracy.

In the embodiment of the disclosure, when a data write operation in a floating point format is performed, a stimulus may be applied to a selected memory cell through a write circuit to change a resistance value of the memory cell. The method can realize the writing operation of the effective numerical value in the floating point format data when the selected storage unit is a multi-value storage unit, and can realize the writing operation of the symbolic value and the exponent value in the floating point format data when the selected storage unit is a binary storage unit.

In some embodiments, the predetermined storage device includes 1 binary storage unit for storing the symbol value and k binary storage units for storing the exponent value, k being an integer greater than or equal to 1; the step of storing the sign value and the exponent value of the floating point data in at least two binary storage units in a predetermined storage device in S310 may specifically include: storing the symbol value to a symbol value storage unit; and storing the exponent value to an exponent value storage unit.

In this embodiment, in the binary memory cells of the predetermined memory device, since the symbol value is 0 or 1, the storage of the symbol value can be realized by 1 binary memory cell; thus, 1 binary storage cell of the plurality of binary storage cells is used to store a symbol value, and the other binary storage cells of the plurality of binary storage cells are used to store an exponent value; the high-stability and accurate storage of the symbol value and the exponent value in the floating-point format data based on the binary storage unit is realized.

In some embodiments, the predetermined memory device is a synapse device, and the number of multivalued memory cells in the synapse device is 1.

In this embodiment, when the predetermined storage device stores the floating-point format data, the effective digital value of the floating-point format data is stored by using the multi-value storage unit, and the number of the multi-value storage units is 1, that is, only one storage unit in the predetermined storage device is used for multi-value storage of the floating-point format data, thereby saving the storage space and realizing the approximate value storage.

In the data storage method in the embodiment of the disclosure, when the predetermined storage device stores the floating-point format data, the valid digital value of the floating-point format data is stored by using the multi-value storage unit, and the number of the multi-value storage units is 1, that is, only one storage unit in the predetermined storage device is used for multi-value storage of the floating-point format data, thereby saving the storage space and realizing the approximate value storage. And a binary storage unit is adopted to perform high-stability and accurate storage on the symbol value and the index value in the symbol domain and the exponent domain. Because the small floating change of the effective digit field can not affect the overall precision of the floating point number, and the small error of the sign field and the exponent field can cause the obvious change of the floating point data, the storage structure can save space, is favorable for reducing the probability that the inaccurate characteristic of multi-value storage affects the overall precision of the floating point number, and improves the overall precision of the storage device.

The steps of the above methods are divided for clarity, and the implementation may be combined into one step or split some steps, and the steps are divided into multiple steps, so long as the same logical relationship is included, which are all within the protection scope of the present patent; it is within the scope of the patent to add insignificant modifications to the algorithms or processes or to introduce insignificant design changes to the core design without changing the algorithms or processes.

Fig. 4 shows a schematic flow chart of a data storage method according to an embodiment of the present disclosure. As shown in fig. 4, the data storage method includes: s410, storing the effective digital value of the floating point data to at least one multivalued storage unit in a predetermined storage device.

In this embodiment, storing, by at least one multivalued storage element of the storage device, a valid digital value of the floating point data; because the overall precision of the floating point data cannot be influenced by the tiny floating change of the effective digital value of the floating point data, the storage structure of the storage device saves the storage space by storing the effective digital value of the floating point data through a multi-value storage unit.

In some embodiments, the data storage method further comprises: storing the sign value and the exponent value of the floating point data to at least two binary storage units in a predetermined storage device.

In the embodiment, the precision of the floating point data is obviously changed due to tiny errors of the sign value and the exponent value of the floating point data, the effective digital value of the floating point data is stored through the multi-value storage unit, the storage space is saved, the sign value and the exponent value of the floating point data are stored through the binary storage unit, the influence of inaccurate characteristics of multi-value storage on the overall precision of the floating point data is favorably reduced, and the overall precision of the storage device is improved.

In some embodiments, S410 may specifically include: determining an excitation parameter for the multi-valued memory cell corresponding to the valid digital value; and adjusting the resistance value of the multivalue memory cell according to the corresponding excitation parameter, and expressing the effective digital value through the adjusted resistance value.

The specific processing procedure of step S410 can be referred to the specific processing procedure of steps S11 to S12 in the foregoing embodiment.

According to the data storage method of the embodiment of the disclosure, at least one multi-value storage unit is used for storing the effective digital value of the floating point data, so as to approximately store the effective digital value of the floating point data, and the storage space of a preset storage device is saved; the sign value and the exponent value are stored by using at least two binary storage units in a predetermined storage device, so that the influence of inaccurate characteristics of multi-value storage on the overall precision of the floating point number can be reduced, and the overall precision of the storage device is improved.

It should be clear that the invention is not limited to the specific process steps described in the above embodiments and shown in the figures. For convenience and brevity of description, detailed descriptions of known methods are omitted herein, and specific working processes of the above-described embodiments may refer to specific details of corresponding processes of the foregoing data storage methods and embodiments of the storage device, which are not described herein again.

Fig. 5 shows a schematic flow chart of a data storage method according to an embodiment of the present disclosure. As shown in fig. 5, the data storage method includes: and S510, storing the sign value and the exponent value of the floating point data into at least two binary storage units in a preset storage device.

In the embodiment, the precision of the floating point data is obviously changed due to tiny errors of the sign value and the exponent value of the floating point data, and the sign value and the exponent value of the floating point data are stored through the binary storage unit, so that the overall precision of the storage device is improved.

According to the data storage method of the embodiment of the disclosure, at least one multi-value storage unit can be used for storing the effective digital value of the floating point data, so that the effective digital value of the floating point data is approximately stored, and the storage space of a preset storage device is saved; the sign value and the exponent value are stored by using at least two binary storage units in a predetermined storage device, so that the influence of inaccurate characteristics of multi-value storage on the overall precision of the floating point number can be reduced, and the overall precision of the storage device is improved.

It should be clear that the invention is not limited to the specific process steps described in the above embodiments and shown in the figures. For convenience and simplicity of description, detailed descriptions of known methods are omitted here, and specific working processes of the above-described embodiments may refer to corresponding processes of the foregoing data storage methods and specific details of the memory device embodiments, which are not described herein again.

Fig. 6 illustrates a schematic structural diagram of a memory device according to an exemplary embodiment of the present disclosure.

In some embodiments, the memory device is configured to store data in a floating point format. As shown in fig. 6, the memory device includes 9 binary memory cells and 1 multivalued memory cell. The 9 binary storage units include 1 symbol value for storing floating-point format data, 8 binary storage units for storing exponent values in floating-point format data, and 1 multi-value storage unit for storing effective digital values in floating-point format data.

Illustratively, the value range of the valid digital value that can be stored in the multi-value storage unit in fig. 6 is 128, then the multi-value storage unit may be referred to as a 128-value unit, it is understood that the multi-value storage unit can store 128 different values; a value range of a valid digital value that can be stored in a multi-value storage cell is 2, the multi-value storage cell may be referred to as a binary cell, and it is understood that the multi-value storage cell may store two different values).

In fig. 6, for each memory cell in the memory device, when a data write operation in a floating point format is performed, a stimulus is applied to a selected memory cell by a write circuit to change the resistance value of the memory cell. For a binary memory cell, namely, expressing two values of 0 and 1 on one memory cell through different resistance values so as to realize high-stability and accurate data storage; for a multi-value storage unit, namely more than two numerical values are expressed on one unit through different resistance values, approximate value storage is realized, so that the storage space is saved, and the overall precision of the storage space for storing floating point format data is improved.

It should be noted that the structure of the memory device shown in fig. 6 is only schematically illustrated, and is not to be understood as a limitation to the protection scope of the memory device structure in the embodiment of the present disclosure. In practical application scenarios, the number of binary memory cells and the number of multi-valued memory cells in the memory device can be set according to practical needs.

Fig. 7 shows a schematic structural diagram of a reading apparatus according to an embodiment of the present disclosure. As shown in fig. 7, in the embodiment of the present disclosure, a reading device is used to read the memory cell array 710. In fig. 7, a memory cell array 710 includes: at least one word line 711, a plurality of bit lines 712, at least one group of memory cells 713, and a gate 714.

The reading device comprises a numerical value judging module 720 and a register 730; wherein at least one word line 711 is sequentially arranged along a first direction; the plurality of bit lines 712 are arranged to cross the at least one word line 711 in a second direction, which is perpendicular to the first direction.

The at least one group of memory cells 713 includes at least two binary memory cells 7131 and at least one multi-value memory cell 7132, each memory cell in the same group of memory cells is located at an intersection of a same word line and a different bit line, and two ends of each memory cell are connected to the corresponding word line and the corresponding bit line.

A gate 714 is connected to each word line 711, and the gate 714 is used to: a selected word line 711 and a selected bit line 712 are determined according to a read address in a received read instruction, and a binary memory cell 7131 and a multi-value memory cell 7132 connected to an intersection of the selected word line 711 and the selected bit line 712 are selected as a selected binary memory cell 7131 and a selected multi-value memory cell 7132.

A numerical value judging module 720, configured to judge the sign value and the exponent value of the floating point data stored in the selected binary storage unit 7131, judge the valid numerical value of the floating point data stored in the selected multi-value storage unit 7132, and send the sign value, the exponent value, and the valid numerical value to the register 730.

And a register 730, configured to concatenate the received sign value, the exponent value, and the valid digital value to obtain read floating point data.

In some embodiments, the size of the register may be selected according to actual needs, and for example, a 16-bit register indicates that the register can accommodate 2 bytes of data.

According to the reading device disclosed by the embodiment of the disclosure, when data is read, the symbol value and the exponent value are read from the binary storage unit for storing the symbol value and the binary storage unit for storing the exponent value respectively, the effective digital value is read from the multi-value storage unit, and then splicing is performed to obtain the data in the floating point format to be read in the storage instruction.

Fig. 8 shows a more detailed structural schematic diagram of a reading apparatus of an embodiment of the present disclosure. The same or equivalent structures in fig. 8 and 7 are given the same reference numerals.

As shown in fig. 8, in the reading apparatus, the numerical value determining module 720 includes: at least two comparators 721 and at least one analog-to-digital converter 722.

The at least two comparators 721 include: a first comparator (not shown) corresponding to a first cell in the selected binary memory cell 7131 and register 730 storing the symbol value and at least one second comparator (not shown), each corresponding to a second cell in the binary memory cell 7131 and register 730 storing the exponent value; each analog-to-digital converter 722 corresponds to a selected multi-value memory cell 7132 and a third cell in register 730.

The first comparator and each second comparator are respectively used for comparing the target resistance value of the corresponding selected binary memory cell 7131 with a preset resistance value threshold, and determining the value of the data stored in the corresponding selected binary memory cell 7131 according to the comparison result, so as to obtain the output value of the first comparator and the output value of each second comparator.

Each analog-to-digital converter 722 is configured to compare the target resistance value of the corresponding selected multi-value memory cell 7132 with resistance values in preset different resistance value intervals to determine a resistance value interval corresponding to the target resistance value of the selected multi-value memory cell 7132, and obtain an output value of each analog-to-digital converter 722 according to the corresponding resistance value interval.

A register 730, configured to receive an output value of the first comparator through the first unit to obtain a symbol value; obtaining an index value through the output value of the corresponding second comparator received by each second unit; valid digital values are obtained through the output values of each analog-to-digital converter 722 respectively corresponding to the output values received by each third unit, so that the sign value, the exponent value and the valid digital values are spliced to obtain read floating point data.

In some embodiments, the first comparator and the second comparator have the same structure, the first comparator is configured to compare the target resistance value of the selected binary storage unit 7131 storing the sign value with a preset resistance value threshold to determine the sign value of the floating point data; the second comparator compares the target resistance value of the selected binary storage unit 7131 storing the exponent value with a predetermined resistance value threshold to determine the sign value of the floating point data.

According to the reading apparatus of the embodiment of the present disclosure, it is possible to realize reading of an effective numerical value of floating-point format data stored by a multi-value storage unit in a predetermined storage device and reading of a sign value and an exponent value of floating-point format data stored by a binary storage unit; in a memory array included in the memory system, each predetermined memory device can store valid digital values in floating-point format data in a multi-value storage form only through part of memory cells, thereby saving memory space; and because the small floating change of the effective digital value does not affect the overall precision of the floating point number, and the small error of the symbol value and the exponent value can cause the precision of the floating point number to obviously change, the requirement on the storage precision is higher, so that the symbol value and the exponent value are stored by using a binary storage unit in a preset storage device, the influence of the inaccurate characteristic of multi-value storage on the overall precision of the floating point number is reduced, and the overall precision of the storage device is improved.

Fig. 9 shows a flow chart of a data reading method according to an embodiment of the disclosure. As shown in fig. 9, the data reading method may include the following steps.

S910, determining a selected word line and a selected bit line in the memory cell array according to a read address in the received read instruction through a gate, and selecting a binary memory cell and a multilevel memory cell connected to an intersection of the selected word line and the selected bit line as a selected binary memory cell and a selected multilevel memory cell.

In some embodiments, the memory cells to be read include: at least two binary storage units for storing the symbol value and the exponent value, and at least one multivalued storage unit for storing the valid digital value.

In this step, the received read command includes a read address; when the memory device receives a read instruction of data, a word line to be selected and a bit line to be selected may be determined based on a read address included in the read instruction to determine a binary memory cell and a multivalued memory cell in a memory device to be read.

And S920, judging the sign value and the exponent value of the floating point data stored in the selected binary storage unit through the numerical value judging module, judging the effective numerical value of the floating point data stored in the selected multi-value storage unit, and sending the sign value, the exponent value and the effective numerical value to a specified register.

In some embodiments, each multi-value memory cell comprises a resistor with a variable resistance value, and the different resistance value intervals to which the resistance value of each multi-value memory cell belongs correspond to different effective digital values to be stored by the multi-value memory cell; therefore, when data of the multi-value storage unit is read, the specific value of the corresponding effective digital value can be determined by acquiring the resistance value of the storage unit and determining the resistance value interval where the value is taken.

In the step, the numerical judgment module comprises at least two comparators and at least one analog-to-digital converter; comparing the target resistance value of the selected binary storage unit storing the sign value with a preset resistance value threshold value through one of at least two comparators to determine the sign value of the floating point data; comparing a target resistance value of the selected binary storage unit storing the exponent value with a preset resistance value threshold through at least one second comparator of the at least two comparators to determine a sign value of the floating point data; and determining a resistance value interval corresponding to the target resistance value of the selected multivalued storage unit storing the effective digital value through the analog-to-digital converter so as to determine the effective digital value of the floating point data.

And S930, splicing the received symbolic value, the exponent value and the effective digital value through a register to obtain read floating point data.

According to the data reading method of the embodiment of the present disclosure, it is possible to realize reading of an effective digital value in floating-point format data stored by a multivalued storage unit in a predetermined storage device, and reading of a sign value and an exponent value of the floating-point format data stored by a binary storage unit; in a memory array included in the memory system, each predetermined memory device can store valid digital values in floating-point format data in a multi-value storage form only through part of memory cells, thereby saving memory space; and because the small floating change of the effective digital value does not affect the overall precision of the floating point number, and the small error of the symbol value and the exponent value can cause the precision of the floating point number to obviously change, the requirement on the storage precision is higher, so that the symbol value and the exponent value are stored by using a binary storage unit in a preset storage device, the influence of the inaccurate characteristic of multi-value storage on the overall precision of the floating point number is reduced, and the overall precision of the storage device is improved.

In some embodiments, in each of predetermined storage devices included in the storage system, each of the predetermined storage devices includes a plurality of binary storage units, wherein 1 binary storage unit is used for storing a sign value, and the other binary storage units are used for storing an exponent value, so that high-stability accurate storage of the sign value and the exponent value in the floating-point format data based on the binary storage units is realized; correspondingly, when data are read, the symbol value and the exponent value are read from the binary storage unit for storing the symbol value and the binary storage unit for storing the exponent value respectively, effective digital values are read from the multi-value storage unit, and then splicing is carried out to obtain the data in the floating point format to be read in the storage instruction.

For ease of understanding, a specific flow of the data reading method of the embodiment of the present disclosure is described below by a specific example. Fig. 10 illustrates a flowchart of a data reading method of an exemplary embodiment of the present disclosure. As shown in fig. 10, in some embodiments, the data reading method includes the following steps.

S1010, receiving the data reading instruction through the gate, and acquiring a reading address included in the data reading instruction.

In this step, the read address is used to indicate a word line to be selected and a bit line to be selected in the memory cell array, and the memory cell to be read can be determined according to the word line to be selected and the bit line to be selected.

S1020, a word line to be selected and a bit line to be selected are determined by a read address of the data, and an intersection of the selected word line and the bit line is a memory cell to be read in the memory array.

In this step, the intersections of the selected word line and the selected bit line are determined, and the memory cell at each intersection is taken as the memory cell to be read. Specifically, the memory array may be composed of a plurality of memory cell arrangements, the memory cell array including at least one group of memory cells; through the word line to be selected, which group of memory cells in the memory cell array the memory cell to be read is in can be determined; the specific position of the memory cell to be read in the group of memory cells can be further determined through the bit line to be selected; so that the memory cell at the intersection of the word line to be selected and the bit line to be selected is taken as the memory cell to be read.

In this step, each read memory cell can be selected in this way and then read; or the memory cells being read may be selected and read simultaneously. The specific mode may be preset according to an actual reading requirement, and the embodiment of the present disclosure is not particularly limited.

And S1030, determining the value of the selected storage unit in the storage array through the comparator.

In this step, for a selected binary memory cell in the memory array, the resistance value of the binary memory cell is first obtained, and the resistance value is compared with the resistance values included in two resistance value ranges corresponding to the binary memory cell to determine the resistance value range to which the resistance value belongs, and then the value (0 or 1) corresponding to the resistance value range to which the resistance value belongs is determined, so as to obtain the data value stored in the binary memory cell.

For a selected multi-value storage unit in the storage array, firstly, the resistance value of the multi-value storage unit is obtained, the resistance value is compared with the resistance value contained in each resistance value interval in more than two resistance value intervals corresponding to the multi-value storage unit to determine the resistance value interval to which the resistance value belongs, and then, the value corresponding to the resistance value interval to which the resistance value belongs is judged numerically to obtain the data value stored by the multi-value storage unit.

And S1040, splicing the data reading results in each selected storage unit, and sending the spliced results to a register to obtain floating point format data in the register.

According to the data reading method, reading of an effective digital value in floating-point format data stored by a multi-value storage unit in a predetermined storage device can be realized; because the small floating change of the effective digital domain does not affect the overall precision of the floating point number, and the requirement of the effective digital value on the storage precision is lower, the storage space is saved in consideration of the fact that a single multi-value storage unit has a larger numerical value range than a single binary storage unit can store, in a storage array contained in the storage system, the effective digital value in the floating point format data can be stored in a multi-value storage form only through part of the storage units in each preset storage device; and because the precision of the floating point data is obviously changed due to tiny errors of the symbol value and the exponent value of the floating point data, and the symbol value and the exponent value have higher requirements on storage precision, when the data are stored, the symbol value and the exponent value are stored by using a binary storage unit in a preset storage device, so that the influence of inaccurate characteristics of multi-value storage on the overall precision of the floating point data is reduced, and the overall precision of the storage device is improved.

It is understood that the above-mentioned method embodiments of the present disclosure can be combined with each other to form a combined embodiment without departing from the logic of the principle, which is limited by the space, and the detailed description of the present disclosure is omitted. Those skilled in the art will appreciate that in the above methods of the specific embodiments, the specific order of execution of the steps should be determined by their function and possibly their inherent logic.

Fig. 11 is a block diagram of a data storage device according to an embodiment of the present disclosure. Referring to fig. 11, the disclosed embodiment provides a data storage device, and the data storage device 1100 includes the following modules.

A first storage module 1110 for storing the sign value and the exponent value of the floating point data to at least two binary storage units in a predetermined storage device; the second storage module 1120 is configured to store the valid digital values of the floating point data to at least one multivalued storage location in a predetermined storage device.

In some embodiments, a second storage module 1120, specifically for determining the excitation parameters for the multivalued storage cells corresponding to the valid digital values; and adjusting the resistance value of the multivalue memory cell according to the corresponding excitation parameter, and expressing the effective digital value through the adjusted resistance value.

In some embodiments, each multivalued memory cell includes a resistance variable in resistance value; the second storage module 1120 is specifically configured to determine, according to a precision requirement of floating point data, a reading order of a resistance value of each multi-valued storage unit; determining the numerical range of the effective numerical value which can be stored by each multivalued storage unit according to the reading order; in the case where the numerical range of the valid numerical values of the floating point data is smaller than or equal to the numerical range of the valid numerical values that can be stored, the valid numerical values of the floating point data are stored to at least one multivalued storage unit in a predetermined storage device.

In some embodiments, the at least two binary memory cells comprise: 1 symbol value storage unit and k exponent value storage units, k being an integer greater than or equal to 1; a second storage module 1120, specifically configured to store the symbol value to a symbol value storage unit; and storing the exponent value to an exponent value storage unit.

According to the data storage device of the embodiment of the disclosure, since the overall precision of the floating point number is not affected by the tiny floating change of the effective digital value of the floating point number, the requirement of the effective digital value on the storage precision is low, and the single multi-value storage unit is considered to be larger than the numerical value range which can be stored by the single binary storage unit, so that the effective digital value of the floating point data is stored by using the multi-value storage units with a small number, the effective digital value of the floating point data is approximately stored, and the storage space of a predetermined storage device is saved; and because the precision of the floating point data is obviously changed due to tiny errors of the symbol value and the exponent value of the floating point data, and the symbol value and the exponent value have higher requirements on storage precision, the symbol value and the exponent value are stored by using a binary storage unit in a preset storage device, so that the influence of inaccurate characteristics of multi-value storage on the overall precision of the floating point data can be reduced, and the overall precision of the storage device is improved.

The disclosed embodiments also provide a data storage device, which includes: and a second storage module for storing the valid digital value of the floating point data to at least one multivalued storage location in a predetermined storage device.

In some embodiments, the data storage device further comprises: a first storage module to store the sign value and the exponent value of the floating point data to at least two binary storage locations in a predetermined storage device.

In some embodiments, the second storage module is specifically configured to: determining an excitation parameter for the multi-valued memory cell corresponding to the valid digital value; and adjusting the resistance value of the multivalue memory cell according to the corresponding excitation parameter, and expressing the effective digital value through the adjusted resistance value.

It should be clear that the invention is not limited to the specific process steps described in the above embodiments. For convenience and simplicity of description, detailed descriptions of known methods are omitted here, and specific working processes of the above-described embodiments may refer to corresponding processes of the foregoing data storage methods and specific details of the memory device embodiments, which are not described herein again.

According to the data storage apparatus of the embodiment of the present disclosure, a small fluctuation change in the effective digital value of the floating point number does not affect the overall precision of the floating point number, the requirement of the effective digital value on the storage precision is low, and the effective digital value of the floating point data is stored using a small number of multivalued storage units in consideration of the fact that a single multivalued storage unit can store a larger numerical value range than a single binary storage unit, so as to approximately store the effective digital value of the floating point data, thereby saving the storage space of a predetermined storage device.

The disclosed embodiments also provide a data storage device, which includes: a first storage module to store the sign value and the exponent value of the floating point data to at least two binary storage units in a predetermined storage device.

According to the data storage device disclosed by the embodiment of the disclosure, the precision of the floating point data is obviously changed due to tiny errors of the sign value and the exponent value of the floating point data, and the sign value and the exponent value of the floating point data are stored through the binary storage unit, so that the overall precision of the storage device is improved.

Referring to fig. 12, an embodiment of the present disclosure provides an electronic device including: at least one processor 1201; at least one memory 1202, and one or more I/O interfaces 1203 connected between the processor 1201 and the memory 1202; wherein the memory 1202 stores one or more computer programs executable by the at least one processor 1201, the one or more computer programs being executable by the at least one processor 1201 to enable the at least one processor 1201 to perform the data storage methods described above.

The disclosed embodiments also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor/processing core, implements the data storage method described above. The computer readable storage medium may be a volatile or non-volatile computer readable storage medium.

The disclosed embodiments also provide a computer program product comprising computer readable code or a non-volatile computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, the processor in the electronic device performs the above-mentioned data storage method or data reading method.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable storage media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).

The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data, as is well known to those skilled in the art. Computer storage media includes, but is not limited to, random Access Memory (RAM), read Only Memory (ROM), erasable Programmable Read Only Memory (EPROM), static Random Access Memory (SRAM), flash memory or other memory technology, portable compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer. In addition, communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).

The computer program product described herein may be embodied in hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK), or the like.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A storage system, comprising: a memory cell array and a reading device;

the memory cell array includes: at least one word line, a plurality of bit lines, at least one group of memory cells and a gate;

wherein the at least one word line is arranged in sequence along a first direction; the plurality of bit lines are arranged in a cross mode with the at least one word line along a second direction, and the second direction is perpendicular to the first direction; the at least one group of memory cells comprises at least two binary memory cells and at least one multi-valued memory cell, each memory cell in the same group of memory cells is respectively positioned at the intersection position of the same word line and different bit lines, and two ends of each memory cell are respectively connected with the corresponding word line and the corresponding bit line; the gate is connected to each word line, and the gate is configured to: determining a selected word line and a selected bit line according to a read address in a received read instruction, and selecting a binary memory cell and a multi-value memory cell connected to an intersection of the selected word line and the selected bit line as a selected binary memory cell and a selected multi-value memory cell;

the reading apparatus includes: a numerical value judging module and a register;

the numerical value judging module is used for judging a sign value and an exponent value of floating point data stored in the selected binary storage unit, judging an effective numerical value of the floating point data stored in the selected multi-value storage unit, and sending the sign value, the exponent value and the effective numerical value to the register; the register is used for splicing the received symbolic value, the received exponent value and the received effective digital value to obtain read floating point data;

and wherein the numerical judgment module comprises: at least two comparators and at least one analog-to-digital converter;

the at least two comparators comprise: a first comparator corresponding to a selected binary storage location storing a sign value and a first location in said register, and at least one second comparator, each corresponding to a binary storage location storing an exponent value and a second location in said register; each analog-to-digital converter corresponds to a selected multivalued memory cell and a third cell in the register; the first comparator and each second comparator are respectively used for comparing the target resistance value of the corresponding selected binary memory cell with a preset resistance value threshold, and determining the value of the data stored in the corresponding selected binary memory cell according to the comparison result to obtain the output value of the first comparator and the output value of each second comparator; each analog-to-digital converter is used for comparing the target resistance value of the corresponding selected multivalued memory cell with the resistance values in preset different resistance value intervals to determine the resistance value interval corresponding to the target resistance value of the selected multivalued memory cell, and obtaining the output value of each analog-to-digital converter according to the corresponding resistance value interval;

the register is used for receiving the output value of the first comparator through the first unit to obtain a symbol value; obtaining an index value through the output value of the corresponding second comparator received by each second unit; and obtaining an effective digital value through the output value of each analog-to-digital converter respectively corresponding to each third unit, so as to splice the symbolic value, the exponent value and the effective digital value to obtain read floating point data.

2. The storage system of claim 1,

at least two binary storage units for storing a sign value and an exponent value of floating point data;

at least one multivalued storage unit for storing valid digital values of the floating point data.

3. The storage system of claim 1,

each multivalued memory cell includes a variable resistance for storing the valid digital value.

4. The storage system of claim 1,

the numerical range of the effective digital value which can be stored by the at least one multi-value storage unit is smaller than or equal to a numerical threshold, the numerical threshold corresponds to the reading order of the resistance value of the at least one multi-value storage unit, and the reading order of the resistance value is determined according to the precision requirement of the floating point data.

5. The storage system of claim 1,

the at least two binary memory cells include: 1 symbol value storage unit and k exponent value storage units, k being an integer greater than or equal to 1;

the sign value storage unit is used for storing the sign value of the floating point data;

the exponent value storage unit is to store an exponent value of the floating point data.

6. The storage system of claim 1,

the two binary memory cells and the at least one multivalue memory cell are used as synapse devices, and the number of multivalue memory cells in the synapse devices is 1.

7. A reading device for reading a memory cell array; wherein the memory cell array comprises: at least one word line, a plurality of bit lines, at least one group of memory cells and a gate; the reading device comprises a numerical value judging module and a register;

wherein the at least one word line is arranged in sequence along a first direction; the plurality of bit lines are arranged in a cross mode with the at least one word line along a second direction, and the second direction is perpendicular to the first direction; the at least one group of memory cells comprises at least two binary memory cells and at least one multi-valued memory cell, each memory cell in the same group of memory cells is respectively positioned at the intersection position of the same word line and different bit lines, and two ends of each memory cell are respectively connected with the corresponding word line and the corresponding bit line; the gate is connected to each word line, and the gate is configured to: determining a selected word line and a selected bit line according to a read address in a received read instruction, and selecting a binary memory cell and a multi-value memory cell connected to an intersection of the selected word line and the selected bit line as a selected binary memory cell and a selected multi-value memory cell; the numerical value judging module is used for judging the sign value and the exponent value of the floating point data stored in the selected binary storage unit, judging the effective numerical value of the floating point data stored in the selected multi-value storage unit, and sending the sign value, the exponent value and the effective numerical value to the register; the register is used for splicing the received symbolic value, the received exponent value and the received effective digital value to obtain read floating point data;

and wherein the numerical judgment module comprises: at least two comparators and at least one analog-to-digital converter; the at least two comparators comprise: a first comparator corresponding to a selected binary storage location storing a sign value and a first location in said register, and at least one second comparator, each corresponding to a binary storage location storing an exponent value and a second location in said register; each analog-to-digital converter corresponds to a selected multivalued memory cell and a third cell in the register; the first comparator and each second comparator are respectively used for comparing the target resistance value of the corresponding selected binary memory cell with a preset resistance value threshold, and determining the value of the data stored in the corresponding selected binary memory cell according to the comparison result to obtain the output value of the first comparator and the output value of each second comparator; each analog-to-digital converter is used for comparing the target resistance value of the corresponding selected multivalued memory cell with the resistance values in preset different resistance value intervals to determine the resistance value interval corresponding to the target resistance value of the selected multivalued memory cell, and obtaining the output value of each analog-to-digital converter according to the corresponding resistance value interval;