CN115083462B - Digital in-memory computing device based on Sram - Google Patents
Digital in-memory computing device based on Sram Download PDFInfo
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- CN115083462B CN115083462B CN202210822856.1A CN202210822856A CN115083462B CN 115083462 B CN115083462 B CN 115083462B CN 202210822856 A CN202210822856 A CN 202210822856A CN 115083462 B CN115083462 B CN 115083462B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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Abstract
The invention relates to a digital memory computing device based on Sram. The digital in-memory computing device includes: the system comprises a Sram weight array module, an input port, an AND gate array module, a counting array module and a digital weighing configuration module. The Sram weight array module is used for storing and calculating weights; the input port is used for acquiring input data; the AND gate array module is used for obtaining a calculation result based on the calculation weight and the input data; the counting array module counts the calculation result to obtain a counting result; the digital weighing configuration module is used for generating a final calculation result based on the counting result, so that the parallelism of the neural network during acceleration can be improved on the basis of not excessively increasing the area.
Description
Technical Field
The invention relates to the technical field of electronic components, in particular to a Sram-based digital in-memory computing device.
Background
As the demand for edge computing increases, the von neumann architecture also gradually reaches the bottleneck. At this time, the concept of memory computing appears, and the memory computing realizes the multiply-accumulate computing in the array by adding a computing structure to the original memory array, thereby greatly reducing the power consumption. However, the existing memory computing has the defects of low parallelism and the like when the neural network is accelerated.
Disclosure of Invention
To address the above-identified deficiencies in the prior art, the present invention provides a Sram-based digital in-memory computing device.
In order to achieve the purpose, the invention provides the following scheme:
a Sram-based digital in-memory computing device, comprising:
the Sram weight array module is used for storing and calculating the weight;
an input port for acquiring input data;
the AND gate array module is respectively connected with the Sram weight array module and the input port and is used for obtaining a calculation result based on the calculation weight and the input data;
the counting array module is connected with the AND gate array module and is used for counting the calculation result to obtain a counting result;
and the digital weighing configuration module is connected with the counting array module and is used for generating a final calculation result based on the counting result.
Preferably, the Sram weight array module includes N × M Sram bitcells.
Preferably, the Sram weight array module isiM Sram bitcells of the line are used for storing the firstiThe number of bits of the individual weights is,i=1,2，...，N。
preferentially, N =16.
Preferably, the and gate array module includes 1 × M and gates.
Preferably, the count array module comprises 1 × M counters.
Preferentially, M =16.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a Sram-based digital memory computing device, which comprises: the system comprises a Sram weight array module, an input port, an AND gate array module, a counting array module and a digital weighing configuration module. The Sram weight array module is used for storing and calculating weights; the input port is used for acquiring input data; the AND gate array module is used for obtaining a calculation result based on the calculation weight and the input data; the counting array module performs counting operation on the calculation result to obtain a counting result; the digital weighing configuration module is used for generating a final calculation result based on the counting result, and further improving the parallelism of the neural network during acceleration on the basis of not increasing the area excessively.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required in the embodiments will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a Sram-based digital memory computing apparatus according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The invention aims to provide a digital memory computing device based on Sram, which can improve the parallelism of a neural network during acceleration on the basis of not increasing the area too much.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The invention provides a Sram-based digital memory computing device, which comprises: the system comprises a Sram weight array module, an input port, an AND gate array module, a counting array module and a digital weighing configuration module. And the AND gate array module is respectively connected with the Sram weight array module and the input port. And the counting array module is connected with the AND gate array module. The digital weighing configuration module is connected with the counting array module. The Sram weight array module is used for storing and calculating weights. The input port is used to obtain input data. And the AND gate array module is used for obtaining a calculation result based on the calculation weight and the input data. Counting array moduleAnd the block is used for counting the calculation result to obtain a counting result. The digital weighing configuration module is used for generating a final calculation result based on the counting result. The Sram weight array module comprises N multiplied by M Sram bitcells. Fourth in Sram weight array ModuleiM Sram bitcells of the line are used for storing the firstiThe number of bits of the individual weights is,i1, 2., N. The AND gate array module comprises 1 XM AND gates. The count array module includes 1 × M counters.
The specific working principle of the digital memory computing device based on Sram provided by the invention is described below by taking an example that the Sram weight array module includes 16 × 16 Sram bit cells, and the number of the Sram bit cells can be selected according to actual requirements in the actual application process.
As shown in fig. 1, each box in the Sram weight array module is a Sram bitcell, and the weights are stored in the manner shown in fig. 1: w1 is stored in the first row, and the 16 Sram bitcells in the first row store 16 bits of W1 (i.e., wi [ j ], i =1,2,.. Ang., N, j =0,1,2,. Ang., M), respectively. The bit line and the input data are each anded (i.e., multiplied). The result of the calculation is given to a counter, which increments by 1 if the result of the counter is 1.
In this embodiment, the computing process of the digital memory computing device adopts the idea of time division multiplexing: firstly writing the weight into the array according to the mode, then calculating, firstly opening one row in each calculation period, and carrying out the read operation of the Sram, wherein the data of the row can be reflected on a bit line, and after the data on the bit line and the input data are summed, if the result is 1, the data accumulation of the bit is added with 1. The next row is opened in the next cycle, and if the result is 1, the accumulation is performed again, and if the result is 0, the accumulation is not performed. Thus, 16 cycles later, the respective cumulative sum for each bit is completed. Finally, according to the weight of the high and low bits, a digital weight configuration module (digital weight configuration module) combines the data to form a final result.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (5)
1. A Sram-based digital in-memory computing device, comprising:
the Sram weight array module is used for storing and calculating the weight;
an input port for acquiring input data;
the AND gate array module is respectively connected with the Sram weight array module and the input port and is used for obtaining a calculation result based on the calculation weight and the input data;
the counting array module is connected with the AND gate array module and is used for counting the calculation result to obtain a counting result;
the digital weighing configuration module is connected with the counting array module and is used for generating a final calculation result based on the counting result;
the Sram weight array module comprises N multiplied by M Sram bitcells; the fourth in the Sram weight array moduleiM Sram bitcells of the row are used for storing the firstiThe number of bits of the individual weights,i=1,2，...，N。
2. the Sram-based digital in-memory computing device of claim 1, wherein N =16.
3. The Sram-based digital in-memory computing device of claim 1, wherein the AND gate array module comprises 1 x M AND gates.
4. The Sram-based digital in-memory computing device of claim 1, wherein the count array module comprises 1 x M counters.
5. A Sram-based digital in-memory computing device according to claim 3 or 4, wherein M =16.
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