CN113035251A - Digital memory computing array device - Google Patents
Digital memory computing array device Download PDFInfo
- Publication number
- CN113035251A CN113035251A CN202110555001.2A CN202110555001A CN113035251A CN 113035251 A CN113035251 A CN 113035251A CN 202110555001 A CN202110555001 A CN 202110555001A CN 113035251 A CN113035251 A CN 113035251A
- Authority
- CN
- China
- Prior art keywords
- bit
- gate
- tube
- exclusive
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/498—Computations with decimal numbers radix 12 or 20. using counter-type accumulators
- G06F7/4983—Multiplying; Dividing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
The invention relates to a digital memory computing array device, which comprises 256 rows by 64 columns of memory computing modules, wherein each memory computing module comprises a bit unit, a tube T7, a tube 8 and an exclusive OR gate, and the tube T7 and the tube 8 form a transmission gate; the weight storage point Q of the bit cell is connected with the input end of the transmission gate, the output end of the transmission gate is connected with the first input end of the exclusive-nor gate, the second input end of the exclusive-nor gate is connected with an input signal, the output of the exclusive-nor gate is used as the output of the bit cell, the gate of the transistor T7 is connected with the control signal RE, and the gate of the transistor T8 is connected with the control signal REN; the input signal input by each bit unit and the weight storage point Q carry out exclusive OR operation through an exclusive OR gate; every time a row of bit units is calculated, 1bit output of the 256 bit units is accumulated to output a 9bit multiply-accumulate result. The invention improves the calculation precision.
Description
Technical Field
The invention relates to the technical field of memory computing, in particular to a digital memory computing array device.
Background
Deep Convolutional Neural Networks (DCNNs) continue to demonstrate improved inference accuracy, and deep learning is moving towards edge computing. This development has driven the work of low-resource machine learning algorithms and their accelerated hardware. The most common operation in DCNNs is Multiplication and Accumulation (MAC), which controls power and delay. The MAC operation has high regularity and parallelism, and is therefore very suitable for hardware acceleration. However, the amount of memory access severely limits the energy efficiency of conventional digital accelerators. Therefore, memory Computing (CIM) is increasingly attractive for DCNN acceleration.
The existing memory array is basically based on a calculation mode of an analog domain, and calculation operation is divided into two types of current domain calculation based on a resistance voltage divider, a discharge rate and the like and charge domain calculation based on charge sharing, a capacitance voltage divider and the like. Analog domain computing is susceptible to environmental effects such as temperature and noise.
Disclosure of Invention
The invention aims to provide a digital memory computing array device, which realizes multiplication and accumulation by using a digital method and improves the computing precision.
In order to achieve the purpose, the invention provides the following scheme:
a digital memory computing array device comprises a row decoding and input driving module, a column control module for controlling and computing a bit line of a write weight, and a 256-row and 64-column memory computing module, wherein each memory computing module comprises a bit unit, a tube T7, a tube T8 and an exclusive-nor gate, the tube T7 and the tube T8 form a transmission gate, and the bit unit is an SRAM memory cell;
the column control module for bit line control and calculation of the write weight is used for providing a control signal RE and a control signal REN for each column; the row decoding and input driving module is used for providing input signals for each row;
the weight storage point Q of the bit cell is connected with the input end of a transmission gate, the output end of the transmission gate is connected with the first input end of the exclusive-OR gate, the second input end of the exclusive-OR gate is connected with the input signal, the output of the exclusive-OR gate is used as the output of the bit cell, the grid of a tube T7 is connected with a control signal RE, and the grid of a tube T8 is connected with a control signal REN;
the input signal input by each bit unit and the weight storage point Q carry out exclusive OR operation through an exclusive OR gate;
every time a row of bit units is calculated, 1bit output of the 256 bit units is accumulated to output a 9bit multiply-accumulate result.
Optionally, the bitcell is a 6T SRAM memory cell.
Optionally, the 1-bit output of the 256-bit unit is accumulated by an 8-stage adder tree to output a 9-bit multiply-accumulate result.
Optionally, the column control module for bit line control and calculation of the write weight is further configured to control each column of bit cells to provide a bit line and a bit line bar.
Optionally, the row decoding and input driving module is further used for controlling word lines of the bit cells in each row.
Optionally, the transistor T7 is an NMOS transistor, and the transistor T8 is a PMOS transistor.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention relates to a digital memory computing array device.A transmission gate is formed by a pipe T7 and a pipe T8 in each bit unit, and the multiplication and accumulation of a digital method are realized by carrying out the same or same operation on input signals and weight values, so that the loss of computing precision is not caused.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of a digital memory computing array device according to the present invention;
FIG. 2 is a schematic diagram of a bitcell structure of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a digital memory computing array device, which realizes multiplication and accumulation by using a digital method and improves the computing precision.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic structural diagram of a digital memory array computing device according to the present invention, and as shown in fig. 1, the digital memory array computing device includes a row decoding and input driving module, a column control module for controlling and computing a bit line of a write weight, and a 256-row × 64-column memory computing module, each memory computing module includes a bit cell, a transistor T7, a transistor T8, and an exclusive nor gate, the transistor T7 and the transistor T8 form a transmission gate, and the bit cell is an SRAM memory cell.
The column control module for bit line control and calculation of the write weight is used for providing a control signal RE and a control signal REN for each column; the row decoding and input driving module is used for providing input signals for each row.
As shown in fig. 2, the weight storage node Q of the bit cell is connected to the input terminal of the transmission gate, the output terminal of the transmission gate is connected to the first input terminal of the exclusive or gate, the second input terminal of the exclusive or gate is connected to the input signal, the output of the exclusive or gate is used as the output of the bit cell, the gate of the transistor T7 is connected to the control signal RE, and the gate of the transistor T8 is connected to the control signal REN.
The input signal input by each bit unit and the weight storage point Q carry out exclusive OR operation through an exclusive OR gate.
Every time a row of bit units is calculated, 1bit output of the 256 bit units is accumulated to output a 9bit multiply-accumulate result.
The bit cell is a 6T SRAM memory cell.
And the 1bit output of the 256 bit units is accumulated through an 8-level adder tree (R) and then a 9bit multiply-accumulate result is output.
The column control module for bit line control and calculation of the write weight is also used for controlling each column of bit cells to provide a bit line BL and a bit line bar BLB.
The row decoding and input driving module is also used for controlling word lines of the bit cells in each row.
The transistor T7 is an NMOS transistor, and the transistor T8 is a PMOS transistor.
The digital memory computing array device of the present invention is described in detail below, wherein 256 rows by 64 columns of memory computing modules (i.e., bit cells) are used for weight storage. The module controls the bit lines BL (i) and bit line inverses BLB (i) to realize weight writing, and the module also acts on the column selection control signals RE (i) and the control signals REN (i) to select the ith column for calculation. The row decoding and input driving module comprises a row decoding function and an input driving function, acts on a word line WL (i) of the storage array during row decoding, and acts on an input signal IN (i) during driving input; the input IN and the weight Q are subjected to the same or operation to generate a 1-bit calculation result, and 256 numbers of 1bit are connected to a module (8-level adder tree) to output a 9-bit result.
The array device of the present invention operates in two modes: 1. writing the weights to a stored value pattern of the memory cells; 2. a calculation mode for a binary multiply-accumulate operation is implemented.
In the save mode, the read/write operation of the inventive bitcell is the same as the write operation of a conventional 6T SRAM cell for normal data write operations. A row decoding module of the storage unit decodes row address signals of data to be stored, and selects a certain row WL (i) of the array; the column decoding module decodes the column address signal of the data to be stored, selects a certain column BL (i) and BLB (i) of the array and realizes the writing operation of the data stored in the storage array.
IN the calculation mode, the weights are stored IN the memory cells, and 256 rows of input data IN (0) -IN (255) are simultaneously activated and input to the array. In (i) is high when the input data is 1, in (i) is low when the input data is 0, and the storage node (Q) stores logic "1" when the weight value is 1 and logic "0" when the weight value is 0. The result OUT (output of the XNOR gate) of the multiplication operation (XNOR) between the input IN (i) and the weight Q is 0 or 1, the OUT with 256 1 bits obtains 128 results with 2 bits through the first-stage adder, obtains 64 results with 3 bits through the second-stage adder, and so on, and obtains 1 result with 9 bits through the eighth-stage adder for output.
FIG. 2 shows a bit cell used in the present invention and its connection to a computational structure. Bit cells in an array device, namely 6-pipe standard SRAM memory cells: the transistor comprises two pull-up PMOS transistors T1 and T2, two pull-down NMOS transistors T3 and T4, two pass transistors T5 and T6(NMOS transistors), a word line WL, a bit line BL and a bit line bar BLB. The computing structure includes two transfer tubes T7, T8 and an XNOR gate.
Connection relation: the source electrode of the tube T1 is connected with a power supply VDD, the grid electrode of the tube T1 is connected with a QB point (weight storage point), and the drain electrode of the tube T1 is connected with a Q point (weight storage point); the source electrode of the tube T2 is connected with a power supply VDD, the grid electrode of the tube T2 is connected with a point Q, and the drain electrode of the tube T2 is connected with a point QB; the source electrode of the tube T3 is grounded, the grid electrode of the tube T3 is connected with the QB point, and the drain electrode of the tube T3 is connected with the Q point; the source electrode of the T4 tube is grounded, the grid electrode of the T4 tube is connected with a Q point, and the drain electrode of the T4 tube is connected with a QB point; the source electrode of the T5 transistor is connected with a bit line BL, the gate electrode of the T5 transistor is connected with a word line WL, and the drain electrode of the T5 transistor is connected with a Q point; the source electrode of the T6 transistor is connected with the bit line bar BLB, the gate electrode of the T6 transistor is connected with the word line WL, and the drain electrode of the T6 transistor is connected with the QB point; the source electrode of the tube T7 is connected with the first input end of the XNOR gate, the grid electrode of the tube T7 is connected with the control signal RE, and the drain electrode of the tube T7 is connected with the point Q; the source electrode of the tube T8 is connected with a point Q, the grid electrode of the tube T8 is connected with a control signal REN, and the drain electrode of the tube T8 is connected with the first input end of the XNOR gate; IN is connected to the second input terminal of the XNOR gate, and the output terminal of the XNOR gate is connected to OUT.
The control signal RE and the control signal REN are in an inverse relationship, when RE is 1, REN is 0, and at the time, the T7 tube and the T8 tube are conducted, so that the conduction from the Q point to the same or gate is controlled.
As shown IN fig. 2, the calculation of the weight stored IN a single bit cell and the input signal IN comprises the following steps: the first step input driving module transmits an input signal to IN, meanwhile, a control signal RE and a control signal REN control the transmission gate to be conducted, and the second step input and the weight are multiplied through an exclusive-nor gate to obtain 1-bit output.
The storage array calculates one column at a time, each column has 256 rows, so 256 OUT are obtained, and the adder accumulates the 256 numbers of 1bit and outputs a 9-bit multiply-accumulate result.
In the invention, the storage module in the memory computing device adopts a stable 6-tube unit, and is easy to realize. The multiplication and accumulation by a digital method can not cause the loss of calculation precision, and can be applied to some high-precision calculation models. Sharing one adder tree for 64 columns saves a lot of area.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (6)
1. A digital memory computing array device is characterized by comprising a row decoding and input driving module, a column control module for controlling and computing a bit line of a write weight, and a 256-row multiplied by 64-column memory computing module, wherein each memory computing module comprises a bit cell, a tube T7, a tube T8 and an exclusive OR gate, the tube T7 and the tube T8 form a transmission gate, and the bit cell is an SRAM memory cell;
the column control module for bit line control and calculation of the write weight is used for providing a control signal RE and a control signal REN for each column; the row decoding and input driving module is used for providing input signals for each row;
the weight storage point Q of the bit cell is connected with the input end of a transmission gate, the output end of the transmission gate is connected with the first input end of the exclusive-OR gate, the second input end of the exclusive-OR gate is connected with the input signal, the output of the exclusive-OR gate is used as the output of the bit cell, the grid of a tube T7 is connected with a control signal RE, and the grid of a tube T8 is connected with a control signal REN;
the input signal input by each bit unit and the weight storage point Q carry out exclusive OR operation through an exclusive OR gate;
every time a row of bit units is calculated, 1bit output of the 256 bit units is accumulated to output a 9bit multiply-accumulate result.
2. The array apparatus of claim 1, wherein the bit cell is a 6T SRAM memory cell.
3. The array apparatus of claim 1, wherein the 1-bit output of the 256-bit cells is accumulated by an 8-stage adder tree to output a 9-bit multiply-accumulate result.
4. The array apparatus of claim 1, wherein the bit line control and calculation column control module for writing weight is further configured to control each column of bit cells to provide bit lines and bit line bar.
5. The array of claim 1, wherein the row decode and input driver module is further configured to control word lines of each row of bit cells.
6. The array of claim 1, wherein the transistor T7 is an NMOS transistor and the transistor T8 is a PMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110555001.2A CN113035251B (en) | 2021-05-21 | 2021-05-21 | Digital memory computing array device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110555001.2A CN113035251B (en) | 2021-05-21 | 2021-05-21 | Digital memory computing array device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113035251A true CN113035251A (en) | 2021-06-25 |
| CN113035251B CN113035251B (en) | 2021-08-17 |
Family
ID=76455723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110555001.2A Active CN113035251B (en) | 2021-05-21 | 2021-05-21 | Digital memory computing array device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113035251B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113743046A (en) * | 2021-09-16 | 2021-12-03 | 上海后摩智能科技有限公司 | Storage and calculation integrated layout structure and data splitting storage and calculation integrated layout structure |
| CN114063975A (en) * | 2022-01-18 | 2022-02-18 | 中科南京智能技术研究院 | Computing system and method based on sram memory computing array |
| CN114647398A (en) * | 2022-05-23 | 2022-06-21 | 中科南京智能技术研究院 | Carry bypass adder-based in-memory computing device |
| CN114913895A (en) * | 2022-07-19 | 2022-08-16 | 中科南京智能技术研究院 | Memory computing macro unit for realizing two-bit input single-bit weight |
| CN114937470A (en) * | 2022-05-20 | 2022-08-23 | 电子科技大学 | Fixed point full-precision memory computing circuit based on multi-bit SRAM unit |
| CN114995783A (en) * | 2022-07-26 | 2022-09-02 | 中科南京智能技术研究院 | Memory computing unit |
| CN115083462A (en) * | 2022-07-14 | 2022-09-20 | 中科南京智能技术研究院 | Novel digital in-memory computing device based on Sram |
| WO2024082377A1 (en) * | 2022-10-20 | 2024-04-25 | 上海科技大学 | D6t in-memory computing accelerator capable of always linearly discharging and reducing numeric steps |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110414677A (en) * | 2019-07-11 | 2019-11-05 | 东南大学 | It is a kind of to deposit interior counting circuit suitable for connect binaryzation neural network entirely |
| US10964362B2 (en) * | 2019-04-25 | 2021-03-30 | Marvell Asia Pte, Ltd. | Three-port memory cell and array for in-memory computing |
-
2021
- 2021-05-21 CN CN202110555001.2A patent/CN113035251B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10964362B2 (en) * | 2019-04-25 | 2021-03-30 | Marvell Asia Pte, Ltd. | Three-port memory cell and array for in-memory computing |
| CN110414677A (en) * | 2019-07-11 | 2019-11-05 | 东南大学 | It is a kind of to deposit interior counting circuit suitable for connect binaryzation neural network entirely |
Non-Patent Citations (1)
| Title |
|---|
| 黎力: "基于SRAM的存内乘法和点乘电路结构设计", 《中国优秀硕士学位论文全文数据库（电子期刊）》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113743046A (en) * | 2021-09-16 | 2021-12-03 | 上海后摩智能科技有限公司 | Storage and calculation integrated layout structure and data splitting storage and calculation integrated layout structure |
| CN113743046B (en) * | 2021-09-16 | 2024-05-07 | 上海后摩智能科技有限公司 | Integrated layout structure for memory and calculation and integrated layout structure for data splitting and memory and calculation |
| CN114063975A (en) * | 2022-01-18 | 2022-02-18 | 中科南京智能技术研究院 | Computing system and method based on sram memory computing array |
| CN114937470A (en) * | 2022-05-20 | 2022-08-23 | 电子科技大学 | Fixed point full-precision memory computing circuit based on multi-bit SRAM unit |
| CN114647398A (en) * | 2022-05-23 | 2022-06-21 | 中科南京智能技术研究院 | Carry bypass adder-based in-memory computing device |
| CN114647398B (en) * | 2022-05-23 | 2022-08-05 | 中科南京智能技术研究院 | Carry bypass adder-based in-memory computing device |
| CN115083462A (en) * | 2022-07-14 | 2022-09-20 | 中科南京智能技术研究院 | Novel digital in-memory computing device based on Sram |
| CN115083462B (en) * | 2022-07-14 | 2022-11-11 | 中科南京智能技术研究院 | Digital in-memory computing device based on Sram |
| CN114913895A (en) * | 2022-07-19 | 2022-08-16 | 中科南京智能技术研究院 | Memory computing macro unit for realizing two-bit input single-bit weight |
| CN114995783A (en) * | 2022-07-26 | 2022-09-02 | 中科南京智能技术研究院 | Memory computing unit |
| WO2024082377A1 (en) * | 2022-10-20 | 2024-04-25 | 上海科技大学 | D6t in-memory computing accelerator capable of always linearly discharging and reducing numeric steps |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113035251B (en) | 2021-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113035251B (en) | Digital memory computing array device | |
| CN112151091B (en) | 8T SRAM unit and memory computing device | |
| CN111816231B (en) | Memory computing device with double-6T SRAM structure | |
| CN112992223B (en) | Memory computing unit, memory computing array and memory computing device | |
| CN112151092B (en) | Storage unit, storage array and in-memory computing device based on 4-pipe storage | |
| CN112558919B (en) | Memory computing bit unit and memory computing device | |
| CN109979503B (en) | Static random access memory circuit structure for realizing Hamming distance calculation in memory | |
| CN112884140B (en) | Multi-bit memory internal computing unit, array and device | |
| CN112599165B (en) | Memory computing unit for multi-bit input and multi-bit weight multiplication accumulation | |
| CN112992232B (en) | Multi-bit positive and negative single-bit memory computing unit, array and device | |
| CN111816234A (en) | Voltage accumulation memory computing circuit based on SRAM bit line union | |
| CN114300012B (en) | Decoupling SRAM memory computing device | |
| CN113838504B (en) | Single-bit memory computing circuit based on ReRAM | |
| CN113077050B (en) | Digital domain computing circuit device for neural network processing | |
| CN113296734B (en) | Multi-position storage device | |
| CN113782072B (en) | Multi-bit memory computing circuit | |
| CN114512161B (en) | Memory computing device with symbols | |
| CN112233712B (en) | 6T SRAM (static random Access memory) storage device, storage system and storage method | |
| CN112558922A (en) | Four-transistor memory computing device based on separated word lines | |
| CN114895869B (en) | Multi-bit memory computing device with symbols | |
| CN114944180B (en) | Weight-configurable pulse generating device based on copy column | |
| CN114882921B (en) | Multi-bit computing device | |
| CN115312093A (en) | Memory computing unit and array based on 9TSRAM | |
| CN113258910B (en) | Computing device based on pulse width modulation | |
| CN114464239B (en) | Memory computing unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 5 / F, building 1, Qilin artificial intelligence Industrial Park, 266 Chuangyan Road, Jiangning District, Nanjing City, Jiangsu Province Patentee after: Zhongke Nanjing Intelligent Technology Research Institute Address before: 5 / F, building 1, Qilin artificial intelligence Industrial Park, 266 Chuangyan Road, Jiangning District, Nanjing City, Jiangsu Province Patentee before: Nanjing Institute of intelligent technology, Institute of microelectronics, Chinese Academy of Sciences |
|
| CP01 | Change in the name or title of a patent holder |