CN115064448A - 用于薄膜型热界面的共面控制 - Google Patents

用于薄膜型热界面的共面控制 Download PDF

Info

Publication number
CN115064448A
CN115064448A CN202210245677.6A CN202210245677A CN115064448A CN 115064448 A CN115064448 A CN 115064448A CN 202210245677 A CN202210245677 A CN 202210245677A CN 115064448 A CN115064448 A CN 115064448A
Authority
CN
China
Prior art keywords
package
tim
feature
adhesive
heat spreader
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210245677.6A
Other languages
English (en)
Inventor
王裕勋
谢秉颖
王卜
郑礼辉
卢思维
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN115064448A publication Critical patent/CN115064448A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/16153—Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Auxiliary Devices For And Details Of Packaging Control (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)

Abstract

本申请涉及用于薄膜型热界面的共面控制。一种方法包括：在封装组件之上接合第一封装和第二封装；分别在第一封装和第二封装之上粘附第一热界面材料(TIM)和第二TIM；在封装组件上配置粘合特征；以及将散热器布置在粘合特征之上并使散热器与粘合特征接触。散热器包括位于第一TIM和第二TIM之上的一部分。然后，粘合特征被固化。

Description

用于薄膜型热界面的共面控制
技术领域
公开一般涉及半导体领域，并且更具体地涉及用于薄膜型热界面地共面控制。
背景技术
集成电路封装可以具有多个封装组件，例如器件管芯和封装基板，这些封装组件接合在一起以增加功能性和集成水平。由于多个封装组件的不同材料之间的差异，可能发生翘曲。随着封装尺寸的增大，翘曲变得更加严重。这带来了一些新问题。例如，热界面材料可用于将热量从集成电路封装中的器件传导到散热器。由于翘曲，热界面材料和对应的器件管芯或封装之间可能发生分层。分层通常出现在不同材料/组件相互连接的区域(例如器件管芯或封装的拐角)以及弱粘合表面(例如模塑料(molding compound)的表面)。
发明内容
根据本申请的一方面，提供一种方法，包括：在封装组件之上接合第一封装和第二封装；分别在第一封装和第二封装之上粘附第一热界面材料TIM和第二TIM；在第一TIM和所述第二TIM被粘附之后，在封装组件上配置第一粘合特征；将散热器布置在第一粘合特征之上并使散热器与第一粘合特征接触，其中，散热器包括位于第一TIM和第二TIM之上的一部分；以及固化第一粘合特征。
根据本申请的一方面，提供一种封装，包括：封装组件；第一封装和第二封装，接合在封装组件之上；第一热界面材料TIM和第二TIM，分别位于第一封装和第二封装之上；第一粘合特征，位于封装组件上；以及散热器，位于第一粘合特征之上并接触第一粘合特征，其中，散热器进一步位于第一TIM和第二TIM之上。
根据本申请的又一方面，提供一种封装，包括：封装基板；封装组件，位于封装基板之上并接合到封装基板，封装组件包括：插入件；以及器件管芯，位于插入件之上并接合到插入件；盖，包括上部，该上部位于封装组件之上；以及粘合特征，位于盖和封装基板之间并与盖和封装基板物理接触，其中，粘合特征的第一顶表面高于封装组件的第二顶表面。
附图说明
当结合附图进行阅读时，通过以下详细描述可最佳地理解本公开的各个方面。要注意的是，根据行业的标准惯例，各种特征没有按比例绘制。事实上，为了讨论的清楚，可以任意地增大或缩小各种特征的尺寸。
图1-5和图6A示出了根据一些实施例的形成包括粘合特征(adhesive feature)的封装的中间阶段的截面图。
图6B示出了根据一些实施例的包括粘合特征的封装的截面图。
图7示出了根据一些实施例的包括粘合特征的封装的截面图。
图8、图9、图10A和图10B示出了根据替代实施例的形成包括条形盖(bar-lid)的封装的中间阶段的截面图。
图11示出了根据一些实施例的包括条形盖和具有鳍的散热器(heat sink)的封装的截面图。
图12-14示出了根据一些实施例的封装的俯视图。
图15示出了根据一些实施例的用于形成封装的工艺流程。
具体实施方式
下面的公开内容提供了用于实现本发明的不同特征的许多不同的实施例或示例。以下描述了组件和布置的特定示例以简化本公开。当然，这些只是示例，并不旨在进行限制。例如，在下面的描述中在第二特征之上或在第二特征上形成第一特征可以包括其中第一特征和第二特征以直接接触方式形成的实施例，还可以包括可以在第一特征和第二特征之间形成附加特征，使得第一特征和第二特征可以不直接接触的实施例。此外，本公开可以在各个示例中重复附图标记和/或字母。这种重复是为了简单和清楚的目的，并且其本身并不指示所讨论的各个实施例和/或配置之间的关系。
此外，本文中可以使用空间相关术语(例如，“之下”、“下方”、“下”、“之上”、“上”等)，以易于描述图中所示的一个要素或特征相对于另外(一个或多个)要素或(一个或多个)特征的关系。这些空间相关术语旨在涵盖器件在使用或工作中除了图中所示朝向之外的不同朝向。装置可能以其他方式定向(旋转90度或处于其他朝向)，并且本文中所用的空间相关描述符同样可能被相应地解释。
提供了一种封装及其形成方法。根据本公开的一些实施例，第一封装组件(例如封装)被接合在第二封装组件(例如封装基板)上。热界面材料(TIM)设置在第一封装组件上。粘合剂也设置在第二封装组件之上以形成粘合特征。散热器(也可以是盖)可以布置在粘合特征之上并连接到粘合特征。粘合特征可有助于减少所得封装的翘曲，并减少TIM和下层的第一封装组件之间的分层。本文讨论的实施例旨在提供示例，以使得能够制作或使用本公开的主题，并且本领域的普通技术人员将容易理解在保持在不同实施例的预期范围内的同时可以进行的修改。在整个各种视图和说明性实施例中，使用相似的附图标记来指定相似的元件。尽管可以将方法实施例讨论为以特定顺序执行，但是其他方法实施例可以以任何逻辑顺序执行。
图1-5和图6A示出了根据一些实施例的形成包括粘合特征的封装的中间阶段的截面图。相对应的过程也示意性地反应在图15所示的流程图中。
图1示出了封装组件20的截面图，该封装组件20在其中包括多个相同的封装组件22。根据一些实施例，封装组件20是封装基板条带，该封装基板条带在其中包括多个封装基板22。封装基板22可以是包括芯的有芯封装基板，或者可以是其中没有芯的无芯封装基板。根据替代实施例，封装组件20可以是另一种类型，例如插入件(interposer)晶圆、印刷电路板、重构晶圆等。根据一些实施例，封装组件20可以在其中不含(或可以包括)有源器件，例如晶体管和二极管。封装组件20也可以在其中不含(或可以包括)无源器件，例如电容器、电感器、电阻器等。
根据本公开的一些实施例，封装组件20包括多个电介质层，这些电介质层可以包括电介质层24、电介质层24之上的电介质层26和电介质层24之下的电介质层28。根据一些实施例，电介质层26和28可以由干膜形成，例如Ajinomoto堆积膜(Ajinomoto Build-upFilm，ABF)。替代地，电介质层26和28可以由聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等形成或包含这些材料，这些材料可以流动形式涂覆并随后固化。当电介质层24位于芯中时，电介质层24可以由环氧树脂、树脂、玻璃纤维、预浸料(包括环氧树脂、树脂和/或玻璃纤维)、玻璃、模塑料、塑料、其组合和/或其多层形成。根据替代实施例，电介质层24可以由诸如PBO、聚酰亚胺、BCB等聚合物形成。再配置线30(包括金属线/焊盘和过孔)形成在电介质层24中。再配置线30被互连以形成封装组件20中的直通连接。
根据一些实施例，当封装组件20不够刚性以致于不能支撑其自身和上覆结构时，提供载体10以支撑封装组件20。根据替代实施例，封装组件20是厚且刚性的，并且能够支撑在其上形成的结构。因此，可以不使用载体10和释放膜(release film)12。在使用了载体10时，载体10可以是玻璃载体、有机载体等。释放膜12形成在载体10上，以用于将封装组件附接到载体10。释放膜12可以由基于聚合物的材料(例如光热转换(Light-To-Heat-Conversion，LTHC)材料)形成，该材料可以包括基于环氧树脂的热释放材料。
根据替代实施例，如图1所示，封装组件20是预成型的，并且被布置放在释放膜12之上。根据替代实施例，封装组件20被逐层构建在释放膜12的顶部上。例如，可以在释放膜12上形成均厚电介质层28，然后逐层形成电介质层24和26以及再分布线(RDL)30。相对应的电介质层24、26和/或28可以由有机材料(例如聚合物)形成，例如聚酰亚胺、PBO等。根据本公开的替代实施例，电介质层24、26和/或28可以由可沉积的无机电介质材料形成，例如氮化硅、氧化硅、氮氧化硅等。沉积工艺可以包括化学气相沉积(CVD)、原子层沉积(ALD)、等离子体增强化学气相沉积(PECVD)或其他适用的沉积工艺。RDL/焊盘30可以通过电镀或替代地通过镶嵌工艺来形成。
进一步参考图1，封装32(也称为封装组件)被布置在封装组件20上。如图15所示，相应的过程在工艺流程200中被图示为过程202。尽管图示了一组(例如两个)封装32，但在此过程中布置了多组封装32，每一组被布置在封装组件22中的对应一个封装组件之上。封装32在其中包括器件管芯，并且可以包括其他封装组件，例如插入件、封装、管芯堆叠等。根据一些实施例，封装32包括封装组件34、46A和46B(图6B)。根据一些实施例，封装组件34是插入件，该插入件包括基板36和相对应的电介质层38。因此，封装组件34也可称为插入件34，而封装组件34也可以为其他类型。示意性地示出了插入件34的结构，并且未示出诸如基板36的顶侧和底侧上的多个电介质层、金属线和过孔、金属焊盘等细节。穿基板过孔40(当基板36为硅基板时，有时称为穿硅过孔40)穿透基板36。穿基板过孔40用于将基板36顶侧和底侧上的导电特征相互互连。焊料区域42可位于插入件之下并连接至插入件，并且用于将插入件34接合至封装组件20。其他接合方案(例如金属对金属直接接合、混合接合等)也可用于将封装组件34接合至封装组件20。
根据一些实施例，封装组件46A(和46B，如图6B所示)被接合到相应的下层封装组件34。图1示出了其中一个封装组件46A可见的截面。在图6B中显示了封装32的另一个截面图，该截面图显示出封装组件46B也与(一个或多个)封装组件46A一样接合到相同的封装组件34(例如插入件)。封装组件46A和46B是不同类型的封装组件，它们统称为封装组件46。
封装组件46中的每一个可以是器件管芯、封装有器件管芯的封装、被集成为系统的包括多个集成电路(或器件管芯)的片上系统(System-on-Chip，SoC)管芯等。封装组件46中的器件管芯可以是或可以包括逻辑管芯、存储器管芯、输入输出管芯、集成无源器件(IPD)等，或其组合。例如，封装组件46中的逻辑器件管芯可以是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯、微控制单元(MCU)管芯、基带(BB)管芯、应用处理器(AP)管芯等。封装组件46中的存储器管芯可以包括静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等。封装组件46中的器件管芯可以包括半导体基板和互连结构。
在根据一些示例实施例的后续讨论中，封装组件46A被称为器件管芯，其可以是根据一些实施例的SoC管芯。封装组件46B可以是诸如高性能存储器(High-PerformanceMemory，HBM)堆叠之类的存储器堆叠。封装组件46B可以包括形成管芯堆叠的存储器管芯60和将存储器管芯60密封在其中的密封料62(例如模塑料)。当从顶部观察时，密封料62可以形成环绕存储器管芯60的环。
返回参考图1，封装组件46(例如46A)可以例如通过焊料区域50接合到下层封装组件34。底部填料54被配置在封装组件46和下层封装组件34之间。根据一些实施例，封装32通过晶圆上芯片(Chip-on-Wafer，CoW)接合工艺形成，其中作为分立芯片/封装的封装组件46被接合到未切割晶圆中的封装组件34以形成重构晶圆。根据一些实施例，未在封装组件46上模制模塑料。重构晶圆由此形成。将重构晶圆切割开以形成分立封装32，分立封装32被接合到封装组件20。
在将封装32布置到封装组件20上之后，焊料区域42被回流，并且底部填料44可被配置在封装32和20之间的间隙中。所得结构如图2所示。如图15所示，相应的过程在工艺流程200中被图示为过程204。参考图6B所示的另一截面，可以存在诸如独立无源器件(Independent Passive Device，IPD)46C之类的其他封装组件，其接合到封装组件20。根据一些实施例，IPD 46C是分立电容器、分立电感器、分立电阻器等，并且在IPD 46C中不形成诸如晶体管之类的有源器件。在随后的讨论中，封装组件20、22、34、46A、46B和46C还分别被称为封装基板条带20、封装基板22、插入件34、器件管芯46A、存储器堆叠46B和IPD 46C，然而应当意识到，这些封装组件也可以是其他类型的封装组件，例如前面段落中已经讨论过的封装组件。
图12示出了图2(和图6A)和图6B所示的一些特征的示例俯视图。图12中的参考截面A-A对应于图2和图6A中所示的截面图，并且图12中的参考截面B-B对应于图6B中所示的截面图。如图12所示，可以有两个或更多个封装32接合到同一封装基板22。每个封装32可以包括一个或多个器件管芯46A和多个堆叠的存储器堆叠46B。存储器堆叠46B中的每一个可以包括存储器管芯60和模制(和包围)存储器管芯60的模塑料62。封装32彼此分隔开一定空间。IPD 46c可被接合到封装组件22的外围区域。
参考图3，TIM 64被附接到封装32。如图15所示，相应的过程在工艺流程200中被图示为过程206。TIM 64为薄膜型TIM，与以可流动形式配置然后固化为固体的液体型TIM相比，薄膜型TIM是在附接时预先成型的固体TIM。根据一些实施例，TIM 64包括基体材料，该基体材料可以是聚合物。基体材料可以由树脂、丙烯酸、基于PBO的聚合物、基于硅的聚合物等形成或包含这些材料。TIM 64可以在其中包括刚性填料，该刚性填料可以包括石墨、石墨烯、金属颗粒等。TIM 64可以被拾取并布置在封装32之上，或者可以通过辊子(roller)施加。根据一些实施例，如图12所示，TIM 64的俯视图尺寸可以大于、等于或小于下层封装32。因此，TIM 64与器件管芯46A和存储器堆叠46B的顶表面接触。TIM 64可以具有高于约1W/k*m、高于约5W/k*m、高于约10W/k*m或更高的热导率值。
参考图4，粘合特征66被配置在封装基板22的顶部上，并且可以与封装基板22物理接触。如图15所示，相应的过程在工艺流程200中被图示为过程208。根据一些实施例，粘合特征66是可流动的，并通过配置器进行配置。粘合特征66的粘度很高，因此在配置之后，粘合特征66可以自身立住并保持其形状，直到被固化为固体。根据一些实施例，粘合特征66包括作为粘合剂的基体可流动材料。根据一些实施例，基体可流动粘合剂由基于Si的聚合物形成或包含基于Si的聚合物，其可以是聚二甲基硅氧烷(PDMS)或类似材料。粘合特征66的性质将在后续段落中讨论。粘合特征66中的基体可流动材料可以是同质材料，其中整个粘合特征66中的基体可流动材料为相同材料。
根据一些实施例，整个粘合特征66由同质材料形成，例如，不添加填料的可流动基体材料。根据其他实施例，粘合特征66可以包括基体材料和基体材料中的填料(以填料颗粒的形式)。填料颗粒具有改善粘合特征66的总体粘度值的功能。根据一些实施例，填料颗粒由氧化铝(铝氧化物)、二氧化硅(氧化硅)、氮化硼、橡胶等形成。填料颗粒可以是预先制备的固体颗粒，这些固体颗粒与填料颗粒的可流动基体材料混合。
根据粘合特征66可流动的一些实施例，粘合特征66被配置。可以使用模板(stencil)和刮板(squeegee)来执行此配置，以限定粘合特征66的形状。替代地，在不使用任何模板的情况下配置粘合特征66。当在不使用模板的情况下配置粘合特征66时，粘合特征66可以具有不规则形状。例如，粘合特征66的侧壁可以是非竖直的，例如倾斜和弯曲的。粘合特征66的顶表面也可以是非平坦的。例如，粘合特征66可以具有弯曲的顶表面，并且可以具有或可以不具有尖端。此外，当在不使用模板的情况下配置粘合特征66时，粘合特征66的形状是随机且不规则的，并且粘合特征66的形状可能彼此不同。
根据一些实施例，粘合特征66位于封装32的外侧，如粘合特征66A作为示例所示的。粘合特征66被配置为靠近封装32，并且尽可能地靠近封装32，只要可由工艺实现。根据一些实施例，如图4所示，粘合特征66与封装32之间间隔开小间隙。粘合特征66也可以与最近的底部填料44间隔开，或者与底部填料44接触。例如，粘合特征66的内部部分可以与底部填料44的外部部分交叠并与之接触。粘合剂66A的顶表面在配置时高于TIM 64的顶表面。
根据一些实施例，在封装32之间配置有一部分粘合剂66(表示为粘合特征66B)作为间隙填充材料。粘合特征66B接触封装32的侧壁。粘合特征66B的顶表面低于TIM 64的顶表面，使得粘合特征将不会被挤压到TIM 64的顶面上。粘合特征66B的底表面可以与封装基板22的顶表面物理接触，或替代地，通过气隙67与封装基板22的顶表面间隔开。此外，粘合特征66B的顶表面可以高于封装32的顶表面、与封装32的顶表面齐平或低于封装32的顶表面。根据替代实施例，不形成粘合特征66B，并且相邻封装32之间的间隙在后续过程中保持未填充。根据又一替代实施例，例如，填充材料(其伸长值低于粘合特征66A的伸长值且其硬度值大于粘合特征66A的硬度值)可以被配置到封装32之间的间隙中作为填充区域。因此，粘合特征66B被示为虚线，以指示其可以形成也可以不形成，或者可以使用与粘合特征66A的材料不同的材料形成。
图4进一步示出了粘合剂68的配置，粘合剂68被配置到封装基板22的顶表面上。如图15所示，相应的过程在工艺流程200中被图示为过程210。粘合剂68可以被配置为包围封装32的环，或者可以被配置为分立部分。根据一些实施例，粘合剂68以及粘合特征66A和66B由相同材料形成。根据替代实施例，粘合剂68以及粘合特征66A和66B由不同材料形成。当随后附接的散热器70(图5)没有使得裙部(skirt)附接到封装基板20时，可以跳过对粘合剂68的配置。粘合剂68的热导率值可低于TIM 64的热导率。例如，粘合剂68的热导率值可低于约1W/k*m，也可采用较高的热导率值。
接下来，参考图5，散热器(或盖)70被附接到TIM 64。根据一些实施例，当散热器70包括下部(即裙部)时，散热器70也是盖，并且在下文中称为散热器。如图15所示，相应的过程在工艺流程200中被图示为过程212。根据一些实施例，封装组件20处于晶圆级，并且包括多个封装组件22。因此，存在多个散热器70，每个散热器被附接到封装组件22中的一个。根据一些实施例，如图5所示，散热器70包括上部70A，其底表面为平面且与TIM 64接触。散热器70还可包括下部70B，其向下延伸以连接粘合剂68。下部70B可以形成完整的环，该环包围封装32和粘合特征66A和66B。上部70A可以具有如图5所示的平面顶表面。根据替代实施例，上部70A包括鳍(其可以是散热器70的集成部分，或者可以是通过另一个TIM粘附到上部70A的独立部分)，如图7所示。根据替代实施例，散热器70不包括下部70B。因此，可以跳过如图4所示的配置粘合剂68的过程。在散热器70附接期间，将散热器70被向下推靠粘合特征66A、粘合特征68和TIM 64，以确保与这些特征的物理接触。结果，无论粘合特征66A具有直侧壁还是非直侧壁，粘合特征66A的侧壁在散热器70被推靠到其上之后都变得非直且不规则。使用虚线66SW作为示例，示出了非直且不规则的侧壁。非直且不规则的侧壁66SW可以从粘合特征66A的顶表面延伸至底表面。
然后执行固化工艺以固化粘合特征66和粘合剂68。如图15所示，相应的过程在工艺流程200中被图示为过程214。根据一些实施例，固化工艺包括热固化工艺，该工艺在约120℃至约170℃的温度范围内执行。固化持续时间可以在约150分钟到约180分钟之间。在固化工艺之后，粘合特征66具有低模量(modulus)，并且比底部填料44和54以及模塑料62更软(如图6B所示)。粘合特征66也可以是弹性的。此外，粘合特征66的热膨胀系数(Coefficient of Thermal Expansion，CTE)可以大于底部填料44和54以及模塑料62的CTE。粘合特征66A可在固化工艺期间收缩。粘合特征66A在固化工艺之后变软且有弹性，可以将散热器70和封装基板22相互拉向彼此。这可以补偿所得封装的翘曲，从而使所得封装具有较低的翘曲。粘合特征66A还将散热器70拉靠到封装32上，使得TIM 64被压靠在封装32上。因此，TIM 64和封装32之间的分层被减少。此外，模塑料62对TIM 64的粘合性相比对硅而言更差，并且粘合特征66A的形成可减少TIM 64和封装组件46B之间的分层。
接下来，根据一些实施例，将封装组件20与载体10解除接合。根据一些实施例，将诸如激光束之类的光束投射到释放膜12上，并且在光束的热作用下使释放膜12分解。因此，封装组件20和上覆结构从载体10中被释放。所得结构如图6A所示。焊料区域72可以被布置在封装组件22上，并且然后进行再回流，如图6A所示。
在随后的过程中，可以执行分离工艺，以切割封装组件20，使得封装组件22被分隔成分立的封装组件。每个封装组件22与相应的上覆封装组件46和散热器70形成封装74。
在上述实施例中，首先将散热器70附接到封装组件上，然后将封装组件20从载体10上脱离，接着切割封装组件20。根据替代实施例，首先将封装组件20从载体10上脱离，接着切割封装组件20，然后将散热器70附接到分立封装组件22。
图6A和图6B示出了封装74的不同截面。封装74的俯视图可以在图12中找到，其中图12所示的截面A-A如图6A所示，并且图12所示的截面B-B如图6B所示。在图12中未显示散热器70。如图12中所示，粘合特征66可以布置在TIM 64最有可能从下层特征分层的位置。最有可能发生分层的位置包括模塑料密度高的区域，例如，由于在存储器堆叠46B中使用模塑化合物62，两个存储器堆叠46B彼此相邻的区域76。因此，在靠近存储器堆叠46B之间的空间处形成粘合特征66A。粘合特征66可以沿着封装32的长边缘布置。
图7示出了根据替代实施例的封装74。根据这些实施例的结构、材料和形成过程基本上与图1-5、图6A和图6B所示的相同，不同之处在于散热器70还包括鳍70C。
图8、图9、图10A和图10B示出了根据本公开的替代实施例的形成封装的中间阶段的截面图。除非另有规定，否则这些实施例中的组件的材料和形成过程基本上与类似组件相同，这些组件在图1-5、图6A和图6B所示的先前实施例中由类似的附图标记表示。因此，关于图8、图9、图10A和图10B中所示的组件的形成过程和材料的细节可以在前面实施例的讨论中找到。
这些实施例的初始过程基本上与图1至图4所示的相同。所得结构也如图8所示。根据这些实施例，配置粘合特征66B被配置。粘合特征66B的体积与散热器条70D(图9)的尺寸有关，将在后续段落中讨论的。另一方面，可以配置或不配置粘合特征66A。因此，粘合特征66A被示为虚线，以指示这些特征可以形成，也可以不形成。根据一些实施例，粘合剂68也被配置，并且可以被形成为环。
接下来，参考图9，散热器70被布置并将其向下推。尽管示出了一个散热器70，但可能存在多个散热器70，每个散热器70被布置在封装组件22中的一个上。散热器70与封装组件22中的一个封装组件22上的TIM 64物理接触并附接到TIM 64。根据一些实施例，散热器70包括上部70A，其底表面为平面且与TIM 64接触。散热器70可以(也可以不)包括向下延伸以连接粘合剂68的下部70B。此外，散热器70还包括散热器条70D，散热器条70D从上部70A的底表面延伸到相邻封装32之间的间隙中。部分70A、70B和70D可以是同一集成区域的部分，其间没有分界面。在散热器70附接期间，将散热器70向下推靠粘合特征66B(以及66A，如果存在)、粘合剂68和TIM 64，以确保与这些特征的物理接触。
散热器条70D被插入粘合特征66B中。散热器条70的宽度小于封装32之间的距离，使得粘合特征66B可以被挤压并上爬到散热器条70D的侧壁。所得粘合特征66B的顶表面可以高于封装32的顶表面、与封装32的顶表面齐平或低于封装32的顶表面。因此，粘合特征66B和散热器条70D之间的接触面积增加，以确保良好的粘合。另一方面，粘合特征66B和散热器70的上部70A之间可能留有气隙71。因此，所配置的粘合特征66B的体积需要考虑散热器条70D的体积。留有一定的气隙可以提供一定的工艺裕度，使得粘合特征66B不会被挤压到TIM 64的顶表面。
然后执行固化工艺以固化粘合特征66和粘合剂68。可以使用如前述实施例中所述的类似温度和类似固化持续时间执行固化工艺。在固化工艺之后，封装组件22可以从载体10上解除接合，随后形成焊料区域72。然后，可以切割封装组件20以将封装组件22彼此分隔开，并形成封装74，如图10A和图10B所示，图10A和10B分别示出了截面A-A和B-B，如图12所示。
粘合特征66B不是直接拉动上部70A，而是在散热器条70D上施加力，从而将上部70A拉向封装基板22。因此，可以减少TIM 64和封装32之间的分层。根据一些实施例，还形成了粘合特征66A以减少分层。
图11示出了根据一些实施例的封装74。根据这些实施例的结构、材料和形成过程基本上与图8、图9、图10A和图10B所示的相同，不同之处在于散热器70还包括鳍70C。鳍70C可以通过另一TIM粘附到上部70A，或者可以是散热器70的集成部分。
图12至14示出了根据本公开的一些实施例的封装74中的一些组件的俯视图。图12示出了一个实施例，在该实施例中在围绕封装32的区域中形成粘合特征66A。例如，一些粘合特征66A可以被形成为靠近存储器堆叠46B彼此靠近的区域。粘合特征66B可以被配置在两个封装32之间。散热器条70D可以形成，也可以不形成，并且在形成时被形成为细长条，其可以在封装32之间的空间的整个长度上延伸，或在封装32之间的空间的基本上整个长度(例如，大于长度的约80％)上延伸。
图13示出了一个实施例，在该实施例中，粘合特征66A被形成为靠近封装32的拐角，该拐角也是更可能发生分层的区域。当存储器堆叠46B彼此靠近时(因此模塑料与TIM64接触)，粘合特征66A可以延伸至相邻存储器堆叠46B之间的空间附近。粘合特征66B可以被配置在两个封装32之间。散热器条70D可以形成，也可以不形成，并且在形成时被形成为细长条，其可以在封装32之间的空间的整个长度上延伸，或在封装32之间的空间的基本上整个长度(例如，大于长度的约80％)上延伸。
图14示出了一个实施例，在该实施例中，粘合特征66A被形成为完全环绕封装32的环。粘合特征66B可以被配置在两个封装32之间。粘合特征66B的一端或两端可以与粘合特征66A物理分隔开以作为分立特征。替代地，粘合特征66B的一端或两端可以与粘合特征66A物理连接。根据一些实施例，散热器条70D可以形成，也可以不形成，并且当形成时，可以被插入粘合特征66B中，但不能被插入粘合特征66A中。根据替代实施例，散热器条70D可以被插入粘合特征66B和粘合特征66A这两者中。根据这些实施例，散热器条延伸超出封装32之间的空间。
在图12、图13和图14中的每个实施例中，粘合特征66A和66B可以以各种组合形成。根据一些实施例，形成粘合特征66A，而不形成粘合特征66B。根据替代实施例，形成粘合特征66B，而不形成粘合特征66A。根据又一替代实施例，形成粘合特征66A和粘合特征66B两者。根据各种实施例，当形成粘合特征66B时，可以存在或不存在散热器条70D。
通过使用本公开的实施例，可以减少封装的翘曲，并且可以减少分层。这些实施例可应用于例如长度和宽度大于50mm或75mm的大型封装。已进行实验以形成不包括粘合特征66A的第一样品封装和包括粘合特征66A的第二样品封装。测量第一样品封装和第二个样品封装的共面度值(coplanarity value)。共面度值为0表示无翘曲，共面度值越大，翘曲越严重。第一样品封装的共面度为293μm，而第二个样品封装的共面度降低到264μm。因此，通过采用本公开的实施例，翘曲减少约9.8％。此外，第二个样本封装的TIM覆盖率也比第一个样本封装更好，其中TIM覆盖率表示应附着于下层特征的TIM区域实际上附着于下层特征而没有分层的百分比，100％表示没有分层。第一样本封装的TIM覆盖率在约94％到约95％之间，第二样本封装的TIM覆盖率提高到约98％到约99％之间。
此外，实验结果还表明，散热器条有助于减少翘曲。这可能归因于散热器(以及所得的封装)的加强，这种加强可能是由于散热器的某些部分增加了厚度，也可能是由于通过粘合特征66B施加的拉力而产生的。执行实验以形成不包括散热器条70D的第三样品封装和包括散热器条70D的第四样品封装。第三样品封装中散热器的共面度为140μm，而第四样品封装中散热器的共面度降低至125μm。此外，第三样本封装的TIM覆盖率在约94％到约95％之间，第四样本封装的TIM覆盖率提高到99％。
在上述示出的实施例中，根据本公开的一些实施例讨论了一些过程和特征，以形成三维(3D)封装。还可以包括其他特性和过程。例如，可以包括测试结构，以帮助3D封装或3D IC器件的验证测试。测试结构可包括例如在再配置层中或在基板上形成的测试焊盘，其允许测试3D封装或3D IC、使用探针和/或探针卡等。验证试验可以在中间结构和最终结构上执行。此外，本文公开的结构和方法可以与包含已知良好管芯的中间验证的测试方法结合使用，以增加良率和降低成本。
本公开的实施例具有一些有利特征。通过应用粘合特征，TIM从下层特征的分层减少。此外，封装的翘曲也被减少。散热器条的形成也有助于减少分层和翘曲。
根据本公开的一些实施例，一种方法包括：在封装组件之上接合第一封装和第二封装；分别在第一封装和第二封装之上粘附第一TIM和第二TIM；在封装组件上配置第一粘合特征；将散热器布置在第一粘合特征之上并使散热器与第一粘合特征接触，其中，散热器包括位于第一TIM和第二TIM之上的一部分；以及固化第一粘合特征。根据一个实施例，所述方法还包括：在第一封装和封装组件之间配置底部填料，其中，第一粘合特征还包括与底部填料交叠并接触的附加部分。根据一个实施例，第一粘合特征具有比底部填料更低的模量值。根据一个实施例，在配置第一粘合特征被配置之后并且在第一粘合特征被固化之前的第一时间，第一粘合特征具有第一顶表面，该第一顶表面高于第一TIM的第二顶表面。根据一个实施例，在布置散热器被布置之后的第二时间，第一粘合特征具有第三顶表面，该第三顶表面与第一TIM的第二顶表面共面。根据一个实施例，第一粘合特征被配置到第一封装的第一侧，并且第二封装位于第一封装的与第一侧相反的第二侧。在一个实施例中，所述方法还包括：在封装组件之上配置第二粘合特征，其中，第二粘合特征具有第一顶表面，该第一顶表面低于第一TIM的第二顶表面。根据一个实施例，散热器包括：上部，高于第一TIM和第二TIM；以及散热器条，从所述上部的底表面延伸到第一封装和第二封装之间的空间中，其中，散热器条被插入第二粘合特征中。在一个实施例中，所述方法还包括：配置粘合环，该粘合环围绕第一封装和第二封装，其中，散热器包括接触粘合环的下部。根据一个实施例，第一粘合特征包括基体材料和混合在基体材料中的基体材料填料颗粒。根据一个实施例，第一TIM和第二TIM在分别粘附在第一封装和第二封装之上时为预成型的固体TIM。
根据本公开的一些实施例，一种封装包括：封装组件；第一封装和第二封装，接合在封装组件之上；第一TIM和第二TIM，分别位于第一封装和第二封装之上；第一粘合特征，位于封装组件上；以及散热器，位于第一粘合特征之上并接触第一粘合特征，其中，散热器进一步位于第一TIM和第二TIM之上。根据一个实施例，散热器与第一TIM和第二TIM物理接触。根据一个实施例，第一粘合特征包括非直侧壁。根据一个实施例，封装还包括第一封装和封装组件之间的底部填料，其中，第一粘合特征的第一部分位于底部填料的第二部分之上并接触底部填料的第二部分。根据一个实施例，封装还包括封装组件上的第二粘合特征，其中，第二粘合特征位于第一封装和第二封装之间，并通过气隙与散热器间隔开。根据一个实施例，散热器包括：上部，高于第一TIM和第二TIM；以及散热器条，从所述上部的底表面延伸，其中，散热器条延伸到第二粘合特征中。
根据本公开的一些实施例，一种封装包括：封装基板；封装组件，位于封装基板之上并接合到封装基板，封装组件包括：插入件；以及器件管芯，位于插入件之上并接合到插入件；盖，包括位于封装组件之上的上部；以及粘合特征，位于盖和封装基板之间并与盖和封装基板物理接触，其中，粘合特征的第一顶表面高于封装组件的第二顶表面。根据一个实施例，封装还包括热界面材料，该热界面材料位于封装组件和盖之间并与封装组件和盖物理接触。根据一个实施例，封装还包括位于封装组件与封装基板之间的底部填料，其中，封装组件包括模制器件管芯的模塑料，并且其中，粘合特征比模塑料和底部填料两者都更软。
如下提供一些示例。
示例1.一种方法，包括：
在封装组件之上接合第一封装和第二封装；
分别在所述第一封装和所述第二封装之上粘附第一热界面材料TIM和第二TIM；
在所述第一TIM和所述第二TIM被粘附之后，在所述封装组件上配置第一粘合特征；
将散热器布置在所述第一粘合特征之上并使所述散热器与所述第一粘合特征接触，其中，所述散热器包括位于所述第一TIM和所述第二TIM之上的一部分；以及
固化所述第一粘合特征。
示例2.根据示例1所述的方法，其中，所述第一粘合特征与所述第一封装和所述第二封装间隔开。
示例3.根据示例1所述的方法，还包括：在所述第一封装和所述封装组件之间配置底部填料，其中，所述第一粘合特征具有比所述底部填料更低的模量值。
示例4.根据示例1所述的方法，其中，在所述第一粘合特征被配置之后并且在所述第一粘合特征被固化之前的第一时间，所述第一粘合特征具有第一顶表面，该第一顶表面高于所述第一TIM的第二顶表面。
示例5.根据示例4所述的方法，其中，在所述散热器被布置之后的第二时间，所述第一粘合特征具有第三顶表面，该第三顶表面与所述第一TIM的所述第二顶表面共面。
示例6.根据示例1所述的方法，其中，所述第一粘合特征被配置到所述第一封装的第一侧，并且所述第二封装位于所述第一封装的与所述第一侧相反的第二侧。
示例7.根据示例1所述的方法，还包括：在所述封装组件之上配置第二粘合特征，其中，所述第二粘合特征具有第一顶表面，该第一顶表面低于所述第一TIM的第二顶表面。
示例8.根据示例7所述的方法，其中，所述散热器包括：
上部，高于所述第一TIM和所述第二TIM；以及
散热器条，从所述上部的底表面延伸到所述第一封装和所述第二封装之间的空间中，其中，所述散热器条被插入所述第二粘合特征中。
示例9.根据示例1所述的方法，还包括：配置粘合环，该粘合环围绕所述第一封装和所述第二封装，其中，所述散热器包括接触所述粘合环的下部。
示例10.根据示例1所述的方法，其中，所述第一粘合特征包括基体材料和混合在所述基体材料中的填料颗粒。
示例11.根据示例1所述的方法，其中，所述第一TIM和所述第二TIM在分别被粘附在所述第一封装和所述第二封装之上时为预成型的固体TIM。
示例12.一种封装，包括：
封装组件；
第一封装和第二封装，接合在所述封装组件之上；
第一热界面材料TIM和第二TIM，分别位于所述第一封装和所述第二封装之上；
第一粘合特征，位于所述封装组件上；以及
散热器，位于所述第一粘合特征之上并接触所述第一粘合特征，其中，所述散热器进一步位于所述第一TIM和所述第二TIM之上。
示例13.根据示例12所述的封装，其中，所述散热器与所述第一TIM和所述第二TIM物理接触。
示例14.根据示例12所述的封装，其中，所述第一粘合特征包括非直侧壁。
示例15.根据示例12所述的封装，还包括所述第一封装和所述封装组件之间的底部填料，其中，所述第一粘合特征的第一部分位于所述底部填料的第二部分之上并接触所述底部填料的所述第二部分。
示例16.根据示例12所述的封装，还包括所述封装组件上的第二粘合特征，其中，所述第二粘合特征位于所述第一封装和所述第二封装之间，并通过气隙与所述散热器间隔开。
示例17.根据示例16所述的封装，其中，所述散热器包括：
上部，高于所述第一TIM和所述第二TIM；以及
散热器条，从所述上部的底表面延伸，其中，所述散热器条延伸到所述第二粘合特征中。
示例18.一种封装，包括：
封装基板；
封装组件，位于所述封装基板之上并接合到所述封装基板，所述封装组件包括：
插入件；以及
器件管芯，位于所述插入件之上并接合到所述插入件；
盖，包括上部，该上部位于所述封装组件之上；以及
粘合特征，位于所述盖和所述封装基板之间并与所述盖和所述封装基板物理接触，其中，所述粘合特征的第一顶表面高于所述封装组件的第二顶表面。
示例19.根据示例18所述的封装，还包括热界面材料，该热界面材料位于所述封装组件和所述盖之间并与所述封装组件和所述盖物理接触。
示例20.根据示例18所述的封装，还包括底部填料，该底部填料位于所述封装组件与所述封装基板之间，其中，所述封装组件包括模制所述器件管芯的模塑料，并且其中，所述粘合特征比所述模塑料和所述底部填料两者都更软。
前述内容概述了若干个实施例的特征，使得本领域技术人员可以更好地理解本公开的各方面。本领域的技术人员应该领会的是，他们可以容易地使用本公开作为基础，用于设计或者修改其他工艺和结构，以实现与这里引入的实施例相同的目的和/或达到与这里引入的实施例相同的优点。本领域技术人员还应当认识到，这些等同构造并不脱离本公开的精神和范围，并且他们可以在不脱离本公开的精神和范围的情况下进行各种改变、替代和变更。

Claims (10)

1.一种制备封装的方法，包括：
在封装组件之上接合第一封装和第二封装；
分别在所述第一封装和所述第二封装之上粘附第一热界面材料TIM和第二TIM；
在所述第一TIM和所述第二TIM被粘附之后，在所述封装组件上配置第一粘合特征；
将散热器布置在所述第一粘合特征之上并使所述散热器与所述第一粘合特征接触，其中，所述散热器包括位于所述第一TIM和所述第二TIM之上的一部分；以及
固化所述第一粘合特征。
2.根据权利要求1所述的方法，其中，所述第一粘合特征与所述第一封装和所述第二封装间隔开。
3.根据权利要求1所述的方法，还包括：在所述第一封装和所述封装组件之间配置底部填料，其中，所述第一粘合特征具有比所述底部填料更低的模量值。
4.根据权利要求1所述的方法，其中，在所述第一粘合特征被配置之后并且在所述第一粘合特征被固化之前的第一时间，所述第一粘合特征具有第一顶表面，该第一顶表面高于所述第一TIM的第二顶表面。
5.根据权利要求4所述的方法，其中，在所述散热器被布置之后的第二时间，所述第一粘合特征具有第三顶表面，该第三顶表面与所述第一TIM的所述第二顶表面共面。
6.根据权利要求1所述的方法，其中，所述第一粘合特征被配置到所述第一封装的第一侧，并且所述第二封装位于所述第一封装的与所述第一侧相反的第二侧。
7.根据权利要求1所述的方法，还包括：在所述封装组件之上配置第二粘合特征，其中，所述第二粘合特征具有第一顶表面，该第一顶表面低于所述第一TIM的第二顶表面。
8.根据权利要求7所述的方法，其中，所述散热器包括：
上部，高于所述第一TIM和所述第二TIM；以及
散热器条，从所述上部的底表面延伸到所述第一封装和所述第二封装之间的空间中，其中，所述散热器条被插入所述第二粘合特征中。
9.一种封装，包括：
封装组件；
第一封装和第二封装，接合在所述封装组件之上；
第一热界面材料TIM和第二TIM，分别位于所述第一封装和所述第二封装之上；
第一粘合特征，位于所述封装组件上；以及
散热器，位于所述第一粘合特征之上并接触所述第一粘合特征，其中，所述散热器进一步位于所述第一TIM和所述第二TIM之上。
10.一种封装，包括：
封装基板；
封装组件，位于所述封装基板之上并接合到所述封装基板，所述封装组件包括：
插入件；以及
器件管芯，位于所述插入件之上并接合到所述插入件；
盖，包括上部，该上部位于所述封装组件之上；以及
粘合特征，位于所述盖和所述封装基板之间并与所述盖和所述封装基板物理接触，其中，所述粘合特征的第一顶表面高于所述封装组件的第二顶表面。
CN202210245677.6A 2021-05-05 2022-03-14 用于薄膜型热界面的共面控制 Pending CN115064448A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202163184598P 2021-05-05 2021-05-05
US63/184,598 2021-05-05
US17/392,904 US11973005B2 (en) 2021-05-05 2021-08-03 Coplanar control for film-type thermal interface
US17/392,904 2021-08-03

Publications (1)

Publication Number Publication Date
CN115064448A true CN115064448A (zh) 2022-09-16

Family

ID=83197268

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210245677.6A Pending CN115064448A (zh) 2021-05-05 2022-03-14 用于薄膜型热界面的共面控制

Country Status (5)

Country Link
US (2) US11973005B2 (zh)
KR (1) KR20220151111A (zh)
CN (1) CN115064448A (zh)
DE (1) DE102021120585A1 (zh)
TW (1) TWI802004B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240194638A1 (en) * 2022-12-09 2024-06-13 Powerchip Semiconductor Manufacturing Corporation Stacked semiconductor device and method of fabricating the same

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9041192B2 (en) 2012-08-29 2015-05-26 Broadcom Corporation Hybrid thermal interface material for IC packages with integrated heat spreader
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9089051B2 (en) * 2013-06-27 2015-07-21 International Business Machines Corporation Multichip module with stiffening frame and associated covers
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
WO2016025451A1 (en) * 2014-08-11 2016-02-18 Massachusetts Institute Of Technology Interconnect structures for assembly of multi-layer semiconductor devices
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10580717B2 (en) 2016-01-11 2020-03-03 Intel Corporation Multiple-chip package with multiple thermal interface materials
GB2564188B (en) 2017-04-24 2022-02-09 Fuji Polymer Ind Silicone sheet and mounting method using the same
US10529645B2 (en) 2017-06-08 2020-01-07 Xilinx, Inc. Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management
WO2019066993A1 (en) 2017-09-30 2019-04-04 Intel Corporation LOWERING MITIGATION STRUCTURES CREATED ON A SUBSTRATE USING HIGH-PERFORMANCE ADDITIVE MANUFACTURE
US10770369B2 (en) 2018-08-24 2020-09-08 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US11600607B2 (en) 2019-01-17 2023-03-07 Samsung Electronics Co., Ltd. Semiconductor module including multiple power management semiconductor packages
US10804181B2 (en) 2019-03-12 2020-10-13 International Business Machines Corporation Heterogeneous thermal interface material for corner and or edge degradation mitigation
US11735552B2 (en) 2019-06-25 2023-08-22 Intel Corporation Microelectronic package with solder array thermal interface material (SA-TIM)
US11521905B2 (en) * 2020-10-21 2022-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US20220359339A1 (en) * 2021-05-05 2022-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-TIM Packages and Method Forming Same
US11869822B2 (en) * 2021-07-23 2024-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof

Also Published As

Publication number Publication date
TW202245079A (zh) 2022-11-16
US20220359345A1 (en) 2022-11-10
KR20220151111A (ko) 2022-11-14
US20240014100A1 (en) 2024-01-11
DE102021120585A1 (de) 2022-11-10
TWI802004B (zh) 2023-05-11
US11973005B2 (en) 2024-04-30

Similar Documents

Publication Publication Date Title
US11824040B2 (en) Package component, electronic device and manufacturing method thereof
US10157849B2 (en) Packages with molding structures and methods of forming the same
CN110660725A (zh) 具有可控间隙的扇出封装件
US9818722B1 (en) Package structure and method for manufacturing thereof
US20180061674A1 (en) Method of manufacturing an electronic device and electronic device manufactured thereby
TW201838108A (zh) 封裝結構
US20230369149A1 (en) Package structure with protective lid
US20220238407A1 (en) Three-dimensional integrated circuit structures and methods of forming the same
US20240014100A1 (en) Coplanar control for film-type thermal interface
CN109817587B (zh) 形成半导体结构的方法及封装件
US20230378020A1 (en) Multi-tim packages and method forming same
US11978715B2 (en) Structure and formation method of chip package with protective lid
US20230065884A1 (en) Package structure and manufacturing method thereof
KR102573008B1 (ko) 반도체 디바이스 및 제조 방법
CN219832631U (zh) 芯片封装结构
US20230326819A1 (en) Dam structure for integrated passive device integration and methods of forming the same
US20230386945A1 (en) Integrated chip package including a crack-resistant lid structure and methods of forming the same
US20220367413A1 (en) Packages With Multiple Types of Underfill and Method Forming The Same
US12033912B2 (en) Package structure and manufacturing method thereof
US20220352046A1 (en) Semiconductor packages and method of manufacturing the same
US20230048302A1 (en) Package structure and manufacturing method thereof
US20230024043A1 (en) Semiconductor Packages with Thermal Lid and Methods of Forming the Same
US20240071857A1 (en) Semiconductor device
US20230395479A1 (en) Dual-underfill encapsulation for packaging and methods of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination