CN115050322A - Display control method, display control unit and display device - Google Patents

Display control method, display control unit and display device Download PDF

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Publication number
CN115050322A
CN115050322A CN202210713097.5A CN202210713097A CN115050322A CN 115050322 A CN115050322 A CN 115050322A CN 202210713097 A CN202210713097 A CN 202210713097A CN 115050322 A CN115050322 A CN 115050322A
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China
Prior art keywords
control
circuit
light
display
control signal
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CN202210713097.5A
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Chinese (zh)
Inventor
郭永林
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to CN202210713097.5A priority Critical patent/CN115050322A/en
Publication of CN115050322A publication Critical patent/CN115050322A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention provides a display control method, a display control unit and a display device. The display control method is applied to a display panel, the display panel comprises a plurality of pixel circuits, and each pixel circuit comprises a light-emitting element, a drive circuit and a data write circuit; after the display refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, one frame time comprises a refresh stage and a hold stage which are arranged in sequence, and the hold stage in the first N frame times comprises M mutually independent setting time periods; n and M are positive integers; the display control method comprises the following steps: in a setting time period, the data writing circuit supplies a setting voltage supplied by the data line to the first end of the driving circuit under the control of the writing control signal; m is greater than or equal to a first number threshold. The invention can improve the magnetic hysteresis of the driving transistor and the switching flash phenomenon during low-frequency display.

Description

Display control method, display control unit and display device
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display control method, a display control unit, and a display device.
Background
In the related art, most display products supporting high and low refresh rates operate, the refresh time of each row of pixel circuits is the same in the high frequency refresh display and the low frequency refresh display, which results in data voltage writing in the high frequency refresh, but in the low frequency refresh, one frame time may be divided into a refresh sub-frame and a hold sub-frame, data voltage writing is performed in the refresh sub-frame, and data voltage writing is not performed in the hold sub-frame.
When a related display product works, after the high-frequency refreshing display is switched to the low-frequency refreshing display, the problem that the cut-frequency flicker is caused due to serious brightness reduction can be caused. For example, after the refresh frequency of the display panel is decreased from 120Hz to 10Hz, there is a severe luminance Drop (decrease) in the previous frame time, especially the first frame time.
Disclosure of Invention
The invention mainly aims to provide a display control method, a display control unit and a display device, which solve the problem that when a related display product works, after high-frequency refreshing display is switched to low-frequency refreshing display, the brightness is seriously reduced, so that the frequency-cut flicker is caused.
In one aspect, an embodiment of the present invention provides a display control method applied to a display panel including a plurality of pixel circuits including a light emitting element, a driving circuit, and a data writing circuit; the data writing circuit is used for controlling the connection or disconnection between the data line and the first end of the driving circuit under the control of a writing control signal, and the driving circuit is used for driving the light-emitting element;
after the display refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, one frame time comprises a refresh stage and a hold stage which are arranged in sequence, and the hold stage in the initial N frame times comprises M mutually independent setting time periods; n and M are positive integers;
the display control method comprises the following steps:
in the set time period, the data writing circuit supplies the set voltage supplied by the data line to the first end of the driving circuit under the control of the writing control signal;
m is greater than or equal to a first number threshold.
Optionally, N is smaller than a second number threshold, where the second number threshold is an integer greater than 1.
Optionally, N is greater than 1; n is a positive integer, N is less than N; the display control method comprises the following steps: after the display refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency,
the number of the setting time periods included in the holding stage in the first N frame times is larger than the number of the setting time periods included in the holding stages from the (N + 1) th frame time to the nth frame time.
Optionally, the pixel circuit further includes a first reset circuit; the display control method further includes:
in the set period, the first reset circuit writes a first reset voltage to a first pole of the light emitting element under the control of a first reset control signal.
Optionally, the pixel circuit further includes a first light emission control circuit; the display control method further includes:
in the setting time period, the first light-emitting control circuit controls the power supply voltage end and the first end of the drive circuit to be disconnected under the control of a light-emitting control signal.
Optionally, the pixel circuit further includes a compensation control circuit; the display control method further includes:
in the holding stage, the compensation control circuit controls the control end of the driving circuit to be disconnected from the second end of the driving circuit under the control of the compensation control signal.
The embodiment of the invention also provides a display control unit which is applied to a display panel, wherein the display panel comprises a plurality of pixel circuits, and each pixel circuit comprises a light-emitting element, a driving circuit and a data writing circuit; the data writing circuit is used for controlling the connection or disconnection between the data line and the first end of the driving circuit under the control of a writing control signal, and the driving circuit is used for driving the light-emitting element; after the display refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, one frame time comprises a refresh stage and a hold stage which are arranged in sequence, and the hold stage in the initial N frame times comprises M mutually independent setting time periods; n and M are positive integers; the display control unit comprises a write-in control signal control circuit;
the write control signal control circuit is used for controlling the write control signal so that the data write circuit provides a set voltage provided by the data line to the first end of the drive circuit under the control of the write control signal in the set time period;
m is greater than or equal to a first number threshold.
Optionally, N is greater than 1; n is a positive integer, N is less than N;
the write control signal control circuit is further configured to control the write control signal so that the number of set time periods included in the holding phase in the first N frame times is greater than the number of set time periods included in the holding phase in the (N + 1) th frame time to the N th frame time after the display refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency.
Optionally, the pixel circuit further includes a first reset circuit; the display control unit further includes a reset control circuit:
the reset control circuit is configured to control a first reset control signal so that the first reset circuit writes a first reset voltage to a first pole of the light emitting element under control of the first reset control signal in the set period.
Optionally, the pixel circuit further includes a first light emission control circuit; the display control unit also comprises a light-emitting control signal control circuit;
the light-emitting control signal control circuit is used for controlling a light-emitting control signal to enable the first light-emitting control circuit to control the power supply voltage end and the first end of the driving circuit to be disconnected under the control of the light-emitting control signal in the setting time period.
Optionally, the pixel circuit further includes a compensation control circuit; the display control unit also comprises a compensation control signal control circuit;
the compensation control signal control circuit is used for controlling the compensation control signal so that the compensation control circuit controls the control end of the driving circuit to be disconnected with the second end of the driving circuit under the control of the compensation control signal in the holding stage.
The embodiment of the invention also provides a display device which comprises the display control unit.
Optionally, the display device according to at least one embodiment of the present invention further includes a plurality of pixel circuits; the pixel circuit includes a light emitting element, a driving circuit, and a data writing circuit;
the data writing circuit is respectively electrically connected with a writing control end, a data line and the first end of the driving circuit and is used for controlling the connection or disconnection between the data line and the first end of the driving circuit under the control of a writing control signal provided by the writing control end;
the second end of the driving circuit is electrically connected with the light emitting element and is used for driving the light emitting element under the control of the potential of the control end of the driving circuit.
Optionally, the pixel circuit further includes a first light emitting control circuit, a compensation control circuit, and a first reset circuit;
the first light-emitting control circuit is respectively electrically connected with a light-emitting control end, a power supply voltage end and the first end of the driving circuit and is used for controlling the connection or disconnection between the power supply voltage end and the first end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control end;
the compensation control circuit is respectively electrically connected with the compensation control end, the control end of the driving circuit and the second end of the driving circuit and is used for controlling the connection or disconnection between the control end of the driving circuit and the second end of the driving circuit under the control of a compensation control signal provided by the compensation control end;
the first reset circuit is electrically connected to a first reset control terminal, a first reset voltage terminal and the first electrode of the light emitting device, respectively, and configured to write a first reset voltage provided by the first reset voltage terminal into the first electrode of the light emitting device under the control of a first reset control signal provided by the first reset control terminal.
Optionally, the pixel circuit further includes an energy storage circuit, a second light emission control circuit, and a second reset circuit;
the first end of the energy storage circuit is electrically connected with the control end of the driving circuit, the second end of the energy storage circuit is electrically connected with the power supply voltage end, and the energy storage circuit is used for storing electric energy;
the second light-emitting control circuit is respectively electrically connected with the light-emitting control end, the second end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the connection or disconnection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; the second pole of the light-emitting element is electrically connected with the first voltage end;
the second reset circuit is respectively electrically connected with the second reset control terminal, the second reset voltage terminal and the control terminal of the driving circuit, and is used for writing the second reset voltage provided by the second reset voltage terminal into the control terminal of the driving circuit under the control of a second reset control signal provided by the second reset control terminal.
The invention can improve the magnetic hysteresis of the driving transistor and the switching flicker phenomenon during low-frequency display.
Drawings
FIG. 1 is a block diagram of at least one embodiment of a pixel circuit included in a display device according to the present invention;
FIG. 2 is a circuit diagram of at least one embodiment of the pixel circuit;
fig. 3 is a waveform diagram of a light emission control signal, a compensation control signal, a write control signal, and a second reset control signal at a refresh frequency of 120 Hz;
fig. 4 is a waveform diagram of a light-emission control signal, a compensation control signal, a write control signal, and a second reset control signal at a first frame time after a refresh frequency becomes 60 Hz;
fig. 5 is a waveform diagram of the light emission control signal, the compensation control signal, the write control signal, and the second reset control signal at the second frame time to the fifth frame time after the refresh frequency becomes 60 Hz;
fig. 6 is another waveform diagram of the light-emission control signal, the compensation control signal, the write control signal, and the second reset control signal at the second frame time to the fifth frame time after the refresh frequency becomes 60 Hz;
fig. 7 is a waveform diagram of the light emission control signal, the compensation control signal, the write control signal, and the second reset control signal after the sixth frame time and after the sixth frame time after the refresh frequency becomes 60 Hz.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
The display control method is applied to a display panel, the display panel comprises a plurality of pixel circuits, and each pixel circuit comprises a light-emitting element, a driving circuit and a data writing circuit; the data writing circuit is used for controlling the connection or disconnection between the data line and the first end of the driving circuit under the control of a writing control signal, and the driving circuit is used for driving the light-emitting element;
after the display refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, one frame time comprises a refresh stage and a hold stage which are arranged in sequence, and the hold stage in the initial N frame times comprises M mutually independent setting time periods; n and M are positive integers;
the display control method comprises the following steps:
in the set time period, the data writing circuit supplies the set voltage supplied by the data line to the first end of the driving circuit under the control of the writing control signal;
m is greater than or equal to a first number threshold.
In the display control method according to the embodiment of the present invention, after the display refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency, in M set time periods in the hold stage in the initial N frame time, the data write circuit supplies the set voltage supplied by the data line to the first terminal of the driver circuit under the control of the write control signal, and refreshes the potential of the first terminal included in the driver circuit by the set voltage for multiple times to adjust the Stress state of the driver transistor included in the driver circuit, so that the hysteresis of the driver transistor can be improved during low-frequency display, and the flicker phenomenon can be improved.
In actual operation, in the holding stage, the number of times of setting the first end of the driving circuit is increased once, and the VRR (variable refresh rate) effect is obviously improved.
In at least one embodiment of the present invention, the first refresh frequency may be, for example, 120Hz, and the second refresh frequency may be, for example, 60Hz, 30Hz, 20Hz, or 10Hz, but not limited thereto.
In a specific implementation, the first refresh frequency may be greater than 60Hz, and the second refresh frequency may be equal to or less than 60Hz, but is not limited thereto.
For example, M may be equal to or greater than 2, i.e., the first number threshold may be 2;
in at least one embodiment of the present invention, the first number threshold may be greater than or equal to 2, and the first number threshold is an integer.
In at least one embodiment of the present invention, N is smaller than a second number threshold, and the second number threshold is an integer greater than 1.
For example, N may be equal to 5 and the second number threshold may be equal to 6. In practical applications, N may be equal to 1, 2, 3, 4, 6, 7 or 8, but not limited thereto.
Optionally; n is a positive integer, N is less than N; the display control method comprises the following steps: after the display refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency,
the number of the setting time periods included in the holding stage in the first N frame times is larger than the number of the setting time periods included in the holding stages from the (N + 1) th frame time to the nth frame time.
In specific implementation, after the display refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency, the potential at the first end of the driving circuit may be set a times in the holding stage in the first N frame times, and the potential at the first end of the driving circuit may be set B times in the holding stage from the (N + 1) th frame time to the nth frame time, where a is greater than B, so as to improve the blinking phenomenon on the premise of ensuring that the power consumption is not greatly increased.
In at least one embodiment of the present invention, the pixel circuit further includes a first reset circuit; the display control method further includes:
in the set period, the first reset circuit writes a first reset voltage to a first pole of the light emitting element under the control of a first reset control signal.
In a specific implementation, in the set period, the first reset circuit writes a first reset voltage into the first pole of the light-emitting element to control the light-emitting element not to emit light and to clear residual charges of the first pole of the light-emitting element.
In at least one embodiment of the present invention, the pixel circuit further includes a first light emission control circuit; the display control method further includes:
and in the setting time period, the first light-emitting control circuit controls the power supply voltage end and the first end of the drive circuit to be disconnected under the control of a light-emitting control signal.
In at least one embodiment of the present invention, the pixel circuit further includes a compensation control circuit; the display control method further includes:
in the holding stage, the compensation control circuit controls the control end of the driving circuit to be disconnected from the second end of the driving circuit under the control of the compensation control signal.
In a specific implementation, in the holding stage, the compensation control circuit controls the control end of the driving circuit to be disconnected from the second end of the driving circuit so as not to change the potential of the control end of the driving circuit.
As shown in fig. 1, at least one embodiment of a pixel circuit included in a display device according to the present invention includes a light-emitting element E0, a driver circuit 10, a data writing circuit 11, a first light-emission control circuit 12, a compensation control circuit 13, a first reset circuit 14, a tank circuit 15, a second light-emission control circuit 16, and a second reset circuit 17;
the data writing circuit 11 is electrically connected to a writing control terminal PG, a data line D1 and a first terminal of the driving circuit 10, respectively, and is configured to control connection or disconnection between the data line D1 and the first terminal of the driving circuit 10 under the control of a writing control signal provided by the writing control terminal PG;
the first light-emitting control circuit 12 is electrically connected to a light-emitting control terminal E1, a power voltage terminal VDD and the first terminal of the driving circuit 10, respectively, and is configured to control connection or disconnection between the power voltage terminal VDD and the first terminal of the driving circuit 10 under the control of a light-emitting control signal provided by the light-emitting control terminal E1;
the compensation control circuit 13 is electrically connected to a compensation control terminal NG, a control terminal of the driving circuit 10 and a second terminal of the driving circuit 10, respectively, and is configured to control the connection or disconnection between the control terminal of the driving circuit 10 and the second terminal of the driving circuit 10 under the control of a compensation control signal provided by the compensation control terminal NG;
the first reset circuit 14 is electrically connected to a first reset control terminal PR, a first reset voltage terminal I1 and a first pole of the light-emitting element E0, respectively, and is configured to write a first reset voltage Vi1 provided by the first reset voltage terminal I1 into a first pole of the light-emitting element E0 under the control of a first reset control signal provided by the first reset control terminal PR;
a first end of the energy storage circuit 15 is electrically connected with a control end of the driving circuit 10, a second end of the energy storage circuit 15 is electrically connected with the power supply voltage end VDD, and the energy storage circuit 15 is used for storing electric energy;
the second light-emitting control circuit 16 is electrically connected to the light-emitting control terminal E1, the second terminal of the driving circuit 10 and the first pole of the light-emitting element E0 respectively, and is used for controlling the connection or disconnection between the second terminal of the driving circuit 10 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal; the second pole of the light emitting element E0 is electrically connected with a first voltage terminal V1;
the second reset circuit 17 is electrically connected to the second reset control terminal NR, the second reset voltage terminal I2 and the control terminal of the driving circuit 10, and is configured to write the second reset voltage Vi2 provided by the second reset voltage terminal I2 into the control terminal of the driving circuit 10 under the control of a second reset control signal provided by the second reset control terminal NR.
In at least one embodiment of the present invention, the voltage value Vi2 may be greater than or equal to-6V and less than or equal to-2V, but not limited thereto.
In at least one embodiment of the present invention, the write control terminal PG and the first reset control terminal PR may be the same control terminal, and the write control signal provided by the write control terminal PG may be the same as the first reset control signal provided by the first reset control terminal PR.
In at least one embodiment of the present invention, the first voltage terminal may be a low voltage terminal, but is not limited thereto.
As shown in fig. 2, based on at least one embodiment of the pixel circuit shown in fig. 1, the light emitting element is an organic light emitting diode O1; the second reset circuit includes a first transistor T1, the compensation control circuit includes a second transistor T2, the driving circuit includes a driving transistor T3; the data writing circuit includes a fourth transistor T4, the first light emission control circuit includes a fifth transistor T5, the second light emission control circuit includes a sixth transistor T6, the first reset circuit includes a seventh transistor T7, the tank circuit includes a storage capacitor Cst;
the gate of the T1 is electrically connected to the second reset control terminal NR, the source of the T1 is electrically connected to the second reset voltage terminal I2, and the drain of the T1 is electrically connected to the gate of the driving transistor T3;
the gate of the T2 is electrically connected with the compensation control terminal NG, the source of the T2 is electrically connected with the gate of the T3, and the drain of the T2 is electrically connected with the drain of the T3;
the grid electrode of the T4 is electrically connected with the writing control end PG, the source electrode of the T4 is electrically connected with the data line D1, and the drain electrode of the T4 is electrically connected with the source electrode of the T3;
the grid electrode of the T5 is electrically connected with a light-emitting control end E1, the source electrode of the T5 is electrically connected with a power supply voltage end VDD, and the drain electrode of the T5 is electrically connected with the source electrode of the T3;
the grid of the T6 is electrically connected with a light-emitting control end E1, the source of the T6 is electrically connected with the drain of the T3, the drain of the T6 is electrically connected with the anode of the O1, and the cathode of the O1 is electrically connected with a low-voltage end VSS;
the gate of T7 is electrically connected to the write control terminal PG, the source of T7 is electrically connected to the first reset voltage terminal I1, and the drain of T7 is electrically connected to the anode of O1.
In at least one embodiment shown in fig. 2, the first reset control terminal is the write control terminal PG, but not limited thereto.
In at least one embodiment of the pixel circuit shown in fig. 2, T1 and T2 are n-type transistors, T3, T4, T5, T6 and T7 are p-type transistors, T1 and T2 are oxide thin film transistors, and T3, T4, T5, T6 and T7 are low temperature polysilicon thin film transistors, but not limited thereto.
When the refresh frequency of the display panel is reduced from 120Hz to 60Hz, FIG. 3 is a waveform diagram of the light-emitting control signal, the compensation control signal, the write control signal and the second reset control signal when the refresh frequency is 120 Hz;
fig. 4 is a waveform diagram of a light-emission control signal, a compensation control signal, a write control signal, and a second reset control signal at a first frame time after a refresh frequency becomes 60 Hz;
fig. 5 is a waveform diagram of the light emission control signal, the compensation control signal, the write control signal, and the second reset control signal at the second frame time to the fifth frame time after the refresh frequency becomes 60 Hz;
fig. 6 is another waveform diagram of the light-emission control signal, the compensation control signal, the write control signal, and the second reset control signal at the second frame time to the fifth frame time after the refresh frequency becomes 60 Hz;
fig. 7 is a waveform diagram of the light emission control signal, the compensation control signal, the write control signal, and the second reset control signal after the sixth frame time and after the sixth frame time after the refresh frequency becomes 60 Hz.
As shown in fig. 3, when the refresh frequency of the display panel is 120Hz, two upward pulses exist in the light emission control signal, the second reset control signal and the compensation control signal have one upward pulse, and the write control signal has one downward pulse within one frame time;
in fig. 3, reference numeral F0 denotes a frame time.
As shown in FIG. 3, when PG provides a low voltage signal, T4 is turned on to write the data voltage to the source of T3, E1 provides a high voltage signal at this time, and T5 is turned off to enable the data voltage to be smoothly written to the source of T3.
As shown in fig. 4, reference numeral F1 is a first frame time after the refresh frequency becomes 60 Hz;
the first frame time F1 includes a first refresh phase S1 and a first hold phase B1;
in the first refresh period S1, the light emission control signal has an upward pulse, the second reset control signal and the compensation control signal have an upward pulse, and the write control signal has a downward pulse;
in the first refresh phase S1, when NR provides a high voltage signal, T1 is turned on to write the second reset voltage Vi2 provided by I2 to the gate of T3;
when E1 provides a high voltage signal, PG provides a low voltage signal, NG provides a high voltage signal, T4, T2 and T7 are turned on, D1 provides data voltage Vdata to the source of T3, the gate of T3 is connected to the drain of T3, and I1 provides first reset voltage Vi1 to the anode of O1, so that O1 does not emit light and the anode of O1 is cleared of residual charges;
when the E1 provides a low voltage signal, T5 and T6 turn on, and T3 drives O1 to emit light.
In fig. 4, reference numeral SW1 is a first data writing period, the first data writing period SW1 is included in the first refresh phase S1, in the first data writing period SW1, PG provides a low voltage signal, E1 provides a high voltage signal, NG provides a high voltage signal, T4, T2, and T7 are turned on, D1 provides a data voltage Vdata to the source of T3, the gate of T3 communicates with the drain of T3, and I1 provides a first reset voltage Vi1 to write the anode of O1.
As shown in fig. 4, the first holding phase B1 includes a first set time period Sz1, a second set time period Sz2, a third set time period Sz3, a fourth set time period Sz4, a fifth set time period Sz5, a sixth set time period Sz6, and a seventh set time period Sz7 that are sequentially set;
in a first set period Sz1, a second set period Sz2, a third set period Sz3, a fourth set period Sz4, a fifth set period Sz5, a sixth set period Sz6, and a seventh set period Sz7, PG provides a low voltage signal, E1 provides a high voltage signal, T5 is turned off, T4 is turned on, and a data line D1 provides sources of set voltages Vz to T3; t7 is turned on, and I1 provides a first reset voltage Vi1 to the anode of O1 to control O1 not to emit light and clear residual charges of the anode of O1;
in the first hold phase B1, NG provides a low voltage signal, and T2 is turned off to control the gate of T3 to be disconnected from the drain of T3, so as to maintain the potential of the gate of T3.
In at least one embodiment of the present invention, the voltage value of Vz may be greater than or equal to 4V and less than or equal to 7V, and the voltage value of Vi1 may be greater than or equal to-6V and less than or equal to-2V, but not limited thereto.
As shown in fig. 4, at the first frame time after switching to the low frequency, the frequency of the write control signal may become 480Hz to adjust Stress state of the driving transistor T3 a plurality of times. In practical implementation, since the frequency of the write control signal is 480Hz, the frequency of the write control signal can be adjusted to 240Hz from the second frame time to the fifth frame time.
As shown in fig. 5, reference numeral FP is the pth frame time after the refresh frequency becomes 60 Hz; p may be an integer of 2 or more and 5 or less;
the pth frame time FP includes a pth refresh phase SP and a pth hold phase BP;
in the pth refresh period SP, there are two upward pulses in the light emission control signal, the second reset control signal and the compensation control signal have one upward pulse, and the write control signal has one downward pulse;
as shown in fig. 5, the pth refresh phase SP includes a pth data write period SWP;
in the pth data writing period SWP, PG provides a low voltage signal, E1 provides a high voltage signal, NG provides a high voltage signal, T4, T2 and T7 are turned on, D1 provides a data voltage Vdata to the source of T3, the gate of T3 is connected to the drain of T3, and I1 provides a first reset voltage Vi1 to be written to the anode of O1.
As shown in fig. 5, the light emission control signal has 8 upward pulses at the P-th frame time FP.
As shown in fig. 5, the pth hold phase BP includes an eighth set period Sz8, a ninth set period Sz9, and a tenth set period Sz 10;
in the eighth set period Sz8, the ninth set period Sz9, and the tenth set period Sz10, PG supplies a low voltage signal, E1 supplies a high voltage signal, T5 is turned off, T4 is turned on, and the data line D1 supplies set voltages Vz to the sources of T3; t7 is turned on, and I1 provides a first reset voltage Vi1 to the anode of O1 to control O1 not to emit light and clear residual charges of the anode of O1;
in the pth hold phase BP, NG provides a low voltage signal, and T2 is turned off to control the gate of T3 to be disconnected from the drain of T3, so as to maintain the potential of the gate of T3.
As shown in fig. 5, the frequency of the write control signal may be changed to 240Hz during the second frame time to the fifth frame time after the switching to the low frequency, so as to adjust the Stress state of the driving transistor T3 multiple times.
As shown in fig. 6, reference numeral FP is the pth frame time after the refresh frequency becomes 60 Hz; p may be an integer of 2 or more and 5 or less;
the pth frame time FP includes a pth refresh phase SP and a pth hold phase BP;
in the pth refresh period SP, there are two upward pulses in the light emission control signal, the second reset control signal and the compensation control signal have one upward pulse, and the write control signal has one downward pulse;
as shown in fig. 6, the pth refresh phase SP includes a pth data write period SWP;
in the pth data writing period SWP, PG provides a low voltage signal, E1 provides a high voltage signal, NG provides a high voltage signal, T4, T2 and T7 are turned on, D1 provides a data voltage Vdata to the source of T3, the gate of T3 is connected to the drain of T3, and I1 provides a first reset voltage Vi1 to be written to the anode of O1.
As shown in fig. 6, the light emission control signal has 4 upward pulses at the P-th frame time FP.
As shown in fig. 6, the pth hold phase BP includes an eighth set period Sz8, a ninth set period Sz9, and a tenth set period Sz 10;
in the eighth set period Sz8, the ninth set period Sz9, and the tenth set period Sz10, PG supplies a low voltage signal, E1 supplies a high voltage signal, T5 is turned off, T4 is turned on, and the data line D1 supplies set voltages Vz to the sources of T3; t7 is turned on, and I1 provides a first reset voltage Vi1 to the anode of O1 to control O1 not to emit light and clear residual charges of the anode of O1;
in the pth hold phase BP, NG provides a low voltage signal, and T2 is turned off to control the gate of T3 to be disconnected from the drain of T3, so as to maintain the potential of the gate of T3.
As shown in fig. 6, the frequency of the write control signal may be changed to 240Hz during the second frame time to the fifth frame time after switching to the low frequency, so as to adjust the Stress state of the driving transistor T3 multiple times.
As shown in fig. 4-6, after the display refresh frequency of the display panel is reduced from 120Hz to 60Hz, the potential at the first end of the driving circuit may be set 7 times in the holding stage of the first frame time, and the potential at the first end of the driving circuit may be set 3 times in the holding stage of the second frame time to the fifth frame time, where 7 is greater than 3, so as to improve the blinking phenomenon while ensuring that the power consumption is not greatly increased.
In actual operation, after the display refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency and N frames of time pass, the brightness waveform is basically stable, and the display panel can be switched to a common mode again for driving in order to reduce power consumption; in at least one embodiment of the present invention, when the first refresh rate is 120Hz and the second refresh rate is 60Hz, N may be equal to 5, but is not limited thereto.
As shown in fig. 7, denoted by FQ is the Q-th frame time after the refresh frequency becomes 60 Hz; q may be an integer of 6 or more;
the Q-th frame time FQ includes a Q-th refresh phase SQ and a Q-th hold phase BQ;
in the Q-th refresh period SQ, there are two upward pulses of the light emission control signal, the second reset control signal and the compensation control signal have one upward pulse, and the write control signal has one downward pulse;
as shown in fig. 7, the qth refresh phase SQ includes a qth data write period SWQ;
in the Q-th data writing period SWQ, PG provides a low voltage signal, E1 provides a high voltage signal, NG provides a high voltage signal, T4, T2 and T7 are turned on, D1 provides a data voltage Vdata to the source of T3, the gate of T3 is connected to the drain of T3, and I1 provides a first reset voltage Vi1 to be written to the anode of O1.
As shown in fig. 7, the light emission control signal has 4 upward pulses at the Q-th frame time FQ.
As shown in fig. 7, the Q-th holding phase BQ includes an eleventh set period Sz 11;
in an eleventh set period Sz11, PG supplies a low voltage signal, E1 supplies a high voltage signal, T5 is turned off, T4 is turned on, and the data line D1 supplies set voltages Vz to the source of T3; t7 is turned on, and I1 provides a first reset voltage Vi1 to the anode of O1 to control O1 not to emit light and clear residual charges of the anode of O1;
in the Q-th holding phase BQ, NG provides a low voltage signal, and T2 is turned off to control the gate of T3 to be disconnected from the drain of T3 to maintain the potential of the gate of T3.
The display control unit is applied to a display panel, the display panel comprises a plurality of pixel circuits, and each pixel circuit comprises a light-emitting element, a driving circuit and a data writing circuit; the data writing circuit is used for controlling connection or disconnection between a data line and a first end of the driving circuit under the control of a writing control signal, and the driving circuit is used for driving the light-emitting element; after the display refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, one frame time comprises a refresh stage and a hold stage which are arranged in sequence, and the hold stage in the initial N frame times comprises M mutually independent setting time periods; n and M are positive integers; the display control unit comprises a write-in control signal control circuit;
the write control signal control circuit is used for controlling the write control signal so that the data write circuit provides a set voltage provided by the data line to the first end of the drive circuit under the control of the write control signal in the set time period;
m is greater than or equal to a first number threshold.
When the display control unit according to the embodiment of the present invention is in operation, after the display refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency, the write control signal control circuit is configured to control the write control signal, so that the data write circuit provides the set voltage provided by the data line to the first terminal of the driving circuit under the control of the write control signal in M set time periods in the holding stage in the initial N frame time, and refreshes the potential of the first terminal included in the driving circuit for multiple times by the set voltage to adjust the Stress state of the driving transistor included in the driving circuit, thereby improving hysteresis of the driving transistor during low-frequency display and improving a stroboscopic phenomenon.
Optionally, N is greater than 1; n is a positive integer, N is less than N;
the write control signal control circuit is further configured to control the write control signal so that the number of set time periods included in the holding phase in the first N frame times is greater than the number of set time periods included in the holding phase in the (N + 1) th frame time to the N th frame time after the display refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency.
In at least one embodiment of the present invention, the pixel circuit further includes a first reset circuit; the display control unit further includes a reset control circuit:
the reset control circuit is configured to control a first reset control signal so that the first reset circuit writes a first reset voltage to a first pole of the light emitting element under control of the first reset control signal in the set period.
In at least one embodiment of the present invention, the pixel circuit further includes a first light emission control circuit; the display control unit also comprises a light-emitting control signal control circuit;
the light-emitting control signal control circuit is used for controlling a light-emitting control signal to enable the first light-emitting control circuit to control the power supply voltage end and the first end of the driving circuit to be disconnected under the control of the light-emitting control signal in the setting time period.
In at least one embodiment of the present invention, the pixel circuit further includes a compensation control circuit; the display control unit also comprises a compensation control signal control circuit;
the compensation control signal control circuit is used for controlling the compensation control signal so that the compensation control circuit controls the control end of the driving circuit to be disconnected with the second end of the driving circuit under the control of the compensation control signal in the holding stage.
The display device provided by the embodiment of the invention comprises the display control unit.
The display device according to at least one embodiment of the present invention further includes a plurality of pixel circuits; the pixel circuit includes a light emitting element, a driving circuit, and a data writing circuit;
the data writing circuit is respectively electrically connected with a writing control end, a data line and the first end of the driving circuit and is used for controlling the connection or disconnection between the data line and the first end of the driving circuit under the control of a writing control signal provided by the writing control end;
the second end of the driving circuit is electrically connected with the light emitting element and is used for driving the light emitting element under the control of the potential of the control end of the driving circuit.
In at least one embodiment of the present invention, the pixel circuit further includes a first light emission control circuit, a compensation control circuit, and a first reset circuit;
the first light-emitting control circuit is respectively electrically connected with a light-emitting control end, a power supply voltage end and the first end of the driving circuit and is used for controlling the connection or disconnection between the power supply voltage end and the first end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control end;
the compensation control circuit is respectively electrically connected with the compensation control end, the control end of the driving circuit and the second end of the driving circuit and is used for controlling the connection or disconnection between the control end of the driving circuit and the second end of the driving circuit under the control of a compensation control signal provided by the compensation control end;
the first reset circuit is electrically connected to a first reset control terminal, a first reset voltage terminal and the first electrode of the light emitting device, respectively, and configured to write a first reset voltage provided by the first reset voltage terminal into the first electrode of the light emitting device under the control of a first reset control signal provided by the first reset control terminal.
Optionally, the pixel circuit further includes an energy storage circuit, a second light emission control circuit, and a second reset circuit;
the first end of the energy storage circuit is electrically connected with the control end of the driving circuit, the second end of the energy storage circuit is electrically connected with the power supply voltage end, and the energy storage circuit is used for storing electric energy;
the second light-emitting control circuit is respectively electrically connected with the light-emitting control end, the second end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the connection or disconnection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; the second pole of the light-emitting element is electrically connected with the first voltage end;
the second reset circuit is respectively electrically connected with the second reset control terminal, the second reset voltage terminal and the control terminal of the driving circuit, and is used for writing the second reset voltage provided by the second reset voltage terminal into the control terminal of the driving circuit under the control of a second reset control signal provided by the second reset control terminal.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A display control method is applied to a display panel, the display panel comprises a plurality of pixel circuits, and the pixel circuits comprise light-emitting elements, driving circuits and data writing circuits; the data writing circuit is used for controlling the connection or disconnection between the data line and the first end of the driving circuit under the control of a writing control signal, and the driving circuit is used for driving the light-emitting element; it is characterized in that the preparation method is characterized in that,
after the display refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, one frame time comprises a refresh stage and a hold stage which are arranged in sequence, and the hold stage in the initial N frame times comprises M mutually independent setting time periods; n and M are positive integers;
the display control method comprises the following steps:
in the set time period, the data writing circuit supplies the set voltage supplied by the data line to the first end of the driving circuit under the control of the writing control signal;
m is greater than or equal to a first number threshold.
2. The display control method of claim 1, wherein N is less than a second number threshold, the second number threshold being an integer greater than 1.
3. The display control method according to claim 1, wherein N is greater than 1; n is a positive integer, N is less than N; the display control method comprises the following steps: after the display refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency,
the number of the setting time periods included in the holding stage in the first N frame times is larger than the number of the setting time periods included in the holding stages from the (N + 1) th frame time to the nth frame time.
4. The display control method according to any one of claims 1 to 3, wherein the pixel circuit further includes a first reset circuit; the display control method further includes:
in the set period, the first reset circuit writes a first reset voltage to a first pole of the light emitting element under the control of a first reset control signal.
5. The display control method according to any one of claims 1 to 3, wherein the pixel circuit further includes a first light emission control circuit; the display control method further includes:
and in the setting time period, the first light-emitting control circuit controls the power supply voltage end and the first end of the drive circuit to be disconnected under the control of a light-emitting control signal.
6. The display control method according to any one of claims 1 to 3, wherein the pixel circuit further includes a compensation control circuit; the display control method further includes:
in the holding stage, the compensation control circuit controls the control end of the driving circuit to be disconnected from the second end of the driving circuit under the control of the compensation control signal.
7. A display control unit is applied to a display panel, the display panel comprises a plurality of pixel circuits, and the pixel circuits comprise light-emitting elements, driving circuits and data writing circuits; the data writing circuit is used for controlling the connection or disconnection between the data line and the first end of the driving circuit under the control of a writing control signal, and the driving circuit is used for driving the light-emitting element; the method is characterized in that after the display refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, one frame time comprises a refresh stage and a hold stage which are arranged in sequence, and the hold stage in the first N frame times comprises M mutually independent setting time periods; n and M are positive integers; the display control unit comprises a write-in control signal control circuit;
the write control signal control circuit is used for controlling the write control signal so that the data write circuit provides a set voltage provided by the data line to the first end of the drive circuit under the control of the write control signal in the set time period;
m is greater than or equal to a first number threshold.
8. The display control unit of claim 7, wherein N is greater than 1; n is a positive integer, N is less than N;
the write control signal control circuit is further configured to control the write control signal so that the number of set time periods included in the holding phase in the first N frame times is greater than the number of set time periods included in the holding phase in the (N + 1) th frame time to the N th frame time after the display refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency.
9. The display control unit of claim 7, wherein the pixel circuit further comprises a first reset circuit; the display control unit further includes a reset control circuit:
the reset control circuit is configured to control a first reset control signal so that the first reset circuit writes a first reset voltage to a first pole of the light emitting element under control of the first reset control signal in the set period.
10. The display control unit according to any one of claims 7 to 9, wherein the pixel circuit further includes a first light emission control circuit; the display control unit also comprises a light-emitting control signal control circuit;
the light-emitting control signal control circuit is used for controlling a light-emitting control signal to enable the first light-emitting control circuit to control the power supply voltage end and the first end of the driving circuit to be disconnected under the control of the light-emitting control signal in the setting time period.
11. The display control unit according to any one of claims 7 to 9, wherein the pixel circuit further includes a compensation control circuit; the display control unit also comprises a compensation control signal control circuit;
the compensation control signal control circuit is used for controlling the compensation control signal so that the compensation control circuit controls the control end of the driving circuit to be disconnected with the second end of the driving circuit under the control of the compensation control signal in the holding stage.
12. A display device characterized by comprising the display control unit according to any one of claims 7 to 11.
13. The display device according to claim 12, further comprising a plurality of pixel circuits; the pixel circuit includes a light emitting element, a driving circuit, and a data writing circuit;
the data writing circuit is respectively electrically connected with a writing control end, a data line and the first end of the driving circuit and is used for controlling the connection or disconnection between the data line and the first end of the driving circuit under the control of a writing control signal provided by the writing control end;
the second end of the driving circuit is electrically connected with the light emitting element and is used for driving the light emitting element under the control of the potential of the control end of the driving circuit.
14. The display device according to claim 13, wherein the pixel circuit further comprises a first light emission control circuit, a compensation control circuit, and a first reset circuit;
the first light-emitting control circuit is respectively electrically connected with a light-emitting control end, a power supply voltage end and the first end of the driving circuit and is used for controlling the connection or disconnection between the power supply voltage end and the first end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control end;
the compensation control circuit is respectively electrically connected with the compensation control end, the control end of the driving circuit and the second end of the driving circuit and is used for controlling the connection or disconnection between the control end of the driving circuit and the second end of the driving circuit under the control of a compensation control signal provided by the compensation control end;
the first reset circuit is electrically connected to a first reset control terminal, a first reset voltage terminal and the first electrode of the light emitting device, respectively, and configured to write a first reset voltage provided by the first reset voltage terminal into the first electrode of the light emitting device under the control of a first reset control signal provided by the first reset control terminal.
15. The display device according to claim 14, wherein the pixel circuit further comprises a tank circuit, a second emission control circuit, and a second reset circuit;
the first end of the energy storage circuit is electrically connected with the control end of the driving circuit, the second end of the energy storage circuit is electrically connected with the power supply voltage end, and the energy storage circuit is used for storing electric energy;
the second light-emitting control circuit is respectively electrically connected with the light-emitting control end, the second end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the connection or disconnection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; the second pole of the light-emitting element is electrically connected with the first voltage end;
the second reset circuit is respectively electrically connected with the second reset control terminal, the second reset voltage terminal and the control terminal of the driving circuit, and is used for writing the second reset voltage provided by the second reset voltage terminal into the control terminal of the driving circuit under the control of a second reset control signal provided by the second reset control terminal.
CN202210713097.5A 2022-06-22 2022-06-22 Display control method, display control unit and display device Pending CN115050322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210713097.5A CN115050322A (en) 2022-06-22 2022-06-22 Display control method, display control unit and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210713097.5A CN115050322A (en) 2022-06-22 2022-06-22 Display control method, display control unit and display device

Publications (1)

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CN115050322A true CN115050322A (en) 2022-09-13

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Family Applications (1)

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