CN113870786B

CN113870786B - Pixel circuit, driving light emitting device and display device

Info

Publication number: CN113870786B
Application number: CN202111140808.6A
Authority: CN
Inventors: 沙一鸣; 李锡平; 承天一; 李孟; 黄耀
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-09-28
Filing date: 2021-09-28
Publication date: 2023-01-10
Anticipated expiration: 2041-09-28
Also published as: CN113870786A

Abstract

The invention provides a pixel circuit, a driving light emitting device and a display device. The pixel circuit comprises a driving circuit, a data writing circuit, a first energy storage circuit and a writing control circuit; the data writing circuit controls the communication between the writing node and the first end of the driving circuit under the control of the first control signal; the write-in control circuit controls the data line to be communicated with the write-in node under the control of a second control signal; the driving circuit is used for controlling the communication between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of the control end of the driving circuit. The invention can improve the flicker phenomenon on the premise of not increasing the power consumption.

Description

Pixel circuit, driving light emitting device and display device

Technical Field

The invention relates to the technical field of display, in particular to a pixel circuit, a driving light-emitting device and a display device.

Background

When the LTPO (low temperature poly oxide) pixel circuit is operated at a low frequency, a display period (the display period may be a frame time) includes a refresh period and a hold period, and in the hold period, since a gate potential of the driving transistor is lowered, a Flicker phenomenon is likely to occur.

Disclosure of Invention

The invention mainly aims to provide a pixel circuit, a driving light-emitting device and a display device, which solve the problem that the existing LTPO pixel circuit is easy to generate flicker phenomenon in the holding stage of the display period when working under low frequency.

In one aspect, embodiments of the present invention provide a pixel circuit including a driving circuit, a data writing circuit, a first tank circuit, and a write control circuit, wherein,

the data writing circuit is respectively electrically connected with a first control line, a writing node and a first end of the driving circuit and is used for controlling the communication between the writing node and the first end of the driving circuit under the control of a first control signal provided by the first control line;

the writing control circuit is respectively electrically connected with a second control line, a data line and the writing node and is used for controlling the data line to be communicated with the writing node under the control of a second control signal provided by the second control line;

the first end of the first energy storage circuit is electrically connected with the writing node, the second end of the first energy storage circuit is electrically connected with the first control node, and the first energy storage circuit is used for storing electric energy;

the drive circuit is used for controlling the communication between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of the control end of the drive circuit.

Optionally, the first control node is a dc voltage terminal.

Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a voltage control circuit;

the voltage control circuit is respectively electrically connected with a third control line, the data line and the first control node and is used for controlling the data line to be communicated with the first control node under the control of a third control signal provided by the third control line.

Optionally, the write control circuit includes at least one write control transistor, a control electrode of the write control transistor is electrically connected to the second control line, a first electrode of the write control transistor is electrically connected to the data line, and a second electrode of the write control transistor is electrically connected to the write node.

Optionally, the write control circuit includes N write control transistors connected in series with each other;

the control electrode of the writing control transistor is electrically connected with the second control line;

a first pole of the Nth writing control transistor is electrically connected with the data line, and a second pole of the first writing control transistor is electrically connected with the writing node;

a first pole of the nth write control transistor is electrically connected with a second pole of the (n + 1) th write control transistor;

n is an integer greater than 1, and N is a positive integer less than N.

Optionally, the voltage control circuit comprises at least one voltage control transistor;

and the control electrode of the voltage control transistor is electrically connected with the third control line, the first electrode of the voltage control transistor is electrically connected with the data line, and the second electrode of the voltage control transistor is electrically connected with the first control node.

Optionally, the voltage control circuit includes M voltage control transistors connected in series;

a control electrode of the voltage control transistor is electrically connected with the third control line;

a first pole of the Mth voltage control transistor is electrically connected with the data line, and a second pole of the first voltage control transistor is electrically connected with the first control node;

a first pole of the mth voltage control transistor is electrically connected with a second pole of the m +1 th voltage control transistor;

m is an integer greater than 1, and M is a positive integer less than M.

Optionally, the first tank circuit includes a first capacitor; the data write circuit includes a data write transistor;

a first end of the first capacitor is electrically connected with the write-in node, and a second end of the first capacitor is electrically connected with a first control node;

a control electrode of the data writing transistor is electrically connected to the first control line, a first electrode of the data writing transistor is electrically connected to the writing node, and a second electrode of the data writing transistor is electrically connected to the first end of the driving circuit.

Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a first light-emitting control circuit, a second tank circuit, a compensation control circuit, a first initialization circuit, a second initialization circuit, and a light-emitting element, wherein,

the first light-emitting control circuit is respectively electrically connected with a light-emitting control line, a power supply voltage end and the first end of the driving circuit and is used for controlling the communication between the power supply voltage end and the first end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control line;

the second light-emitting control circuit is respectively electrically connected with the light-emitting control line, the second end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the communication between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal;

the second energy storage circuit is electrically connected with the control end of the driving circuit and is used for storing electric energy;

the compensation control circuit is respectively electrically connected with the second control line, the control end of the driving circuit and the second end of the driving circuit and is used for controlling the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the second control signal;

the first initialization circuit is respectively electrically connected with a reset control line, a first initial voltage end and the control end of the driving circuit, and is used for controlling the writing of a first initial voltage provided by the first initial voltage end into the control end of the driving circuit under the control of a reset control signal provided by the reset control line;

the second initialization circuit is electrically connected to the first control line, a second initial voltage terminal and the first pole of the light emitting element, respectively, and is configured to write a second initial voltage provided by the second initial voltage terminal into the first pole of the light emitting element under the control of the first control signal;

and the second pole of the light-emitting element is electrically connected with the low-voltage end.

Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a first light-emitting control circuit, a second energy storage circuit, a compensation control circuit, an on-off control circuit, a first initialization circuit, a second initialization circuit, and a light-emitting element;

the compensation control circuit is respectively electrically connected with the first control line, the second end of the driving circuit and the second control node and is used for controlling the communication between the second end of the driving circuit and the second control node under the control of the first control signal;

the on-off control circuit is respectively electrically connected with the second control line, the control end of the driving circuit and the second control node and is used for controlling the communication between the control end of the driving circuit and the second control node under the control of the second control signal;

the first initialization circuit is respectively electrically connected with a reset control line, a first initial voltage end and the second control node, and is used for writing a first initial voltage provided by the first initial voltage end into the second control node under the control of a reset control signal provided by the reset control line;

the second initialization circuit is electrically connected to the first control line, the second initial voltage terminal and the first pole of the light emitting element, respectively, and is configured to write a second initial voltage provided by the second initial voltage terminal into the first pole of the light emitting element under the control of the first control signal;

In a second aspect, embodiments of the present invention provide a driving method applied to the above-described pixel circuit, the display period including a refresh phase and a hold phase; the driving method includes:

in a data writing time period included in a refreshing stage, a data line provides data voltage, a writing control circuit provides the data voltage to a writing node under the control of a second control signal, and a data writing circuit controls the communication between the writing node and the first end of a driving circuit under the control of a first control signal so as to write the data voltage into the first end of the driving circuit;

in the holding stage, the write-in control circuit controls the data line and the write-in node to be disconnected under the control of a second control signal, and the first energy storage circuit maintains the potential of the write-in node;

the data writing circuit controls communication between the writing node and the first terminal of the driving circuit under control of the first control signal during a data writing period included in the holding phase.

Optionally, the pixel circuit further includes a voltage control circuit; the refresh phase further comprises a set time period set after the data write time period; the driving method further includes:

in the setting time period, the signal provided by the data line is changed from a data voltage to a black-state voltage, and the voltage control circuit writes the signal provided by the data line into a first control node under the control of a third control signal;

the voltage value of the black state voltage is greater than the voltage value of the data voltage.

In a third aspect, embodiments of the present invention provide a display device including the pixel circuit described above.

The pixel circuit, the driving light-emitting device and the display device can improve the flicker phenomenon on the premise of not increasing power consumption.

Drawings

Fig. 1 is a block diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 3A is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 3B is a graph showing the relationship between VGMP (VGMP is the potential of the second node during the data writing phase in the holding phase in the display period) and the flicker improvement degree S0;

FIG. 4 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 5 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 6 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 7 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 6 according to the present invention;

fig. 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

fig. 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 10 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 9 according to the present invention;

FIG. 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 12 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 11 according to the present invention;

fig. 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

fig. 15 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.

As shown in fig. 1, the pixel circuit according to the embodiment of the present invention includes a driving circuit 11, a data writing circuit 12, a first tank circuit 13, and a writing control circuit 14, wherein,

the data writing circuit 12 is electrically connected to a first control line P-GATE, a writing node N5 and a first end of the driving circuit 11, respectively, and is configured to control communication between the writing node N5 and the first end of the driving circuit 11 under the control of a first control signal provided by the first control line P-GATE;

the writing control circuit 14 is electrically connected to a second control line S2, a Data line Data and the writing node N5, and is configured to control communication between the Data line Data and the writing node N5 under the control of a second control signal provided by the second control line S2;

a first end of the first tank circuit 13 is electrically connected to the write-in node N5, a second end of the first tank circuit 13 is electrically connected to a first control node N6, and the first tank circuit 13 is configured to store electric energy;

the driving circuit 11 is used for controlling the communication between the first end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the potential of the control end of the driving circuit 11.

In fig. 1, a node denoted by N1 is a first node, a node denoted by N2 is a second node, and a node denoted by N3 is a third node, N1 is electrically connected to the control end of the driving circuit 11, N2 is electrically connected to the first end of the driving circuit 11, and N3 is electrically connected to the second end of the driving circuit 11.

When the embodiment of the pixel circuit of the present invention shown in fig. 1 is in operation, the display cycle includes a refresh phase and a hold phase;

in a Data writing time period included in a refreshing stage, a Data line Data provides a Data voltage Vdata, a writing control circuit 14 provides the Data voltage Vdata to a writing node N5 under the control of a second control signal, and a Data writing circuit 12 controls the communication between the writing node N5 and the first end of the driving circuit 11 under the control of a first control signal so as to write the Data voltage Vdata into the first end of the driving circuit 11;

in the holding phase, the write control circuit 14 controls the Data line Data to be disconnected from the write node N5 under the control of a second control signal, and the first tank circuit 13 maintains the potential of the write node N5;

in a data writing time period included in the holding stage, the data writing circuit 12 controls the communication between the writing node N5 and the first end of the driving circuit 11 under the control of the first control signal, so that the difference between the potential of the first end of the driving circuit 11 and Vdata is not large, and the flicker phenomenon can be improved on the premise of not increasing power consumption.

In at least one embodiment of the present invention, the fact that the potential of the first terminal of the driving circuit 11 is not much different from Vdata means that: the difference between the potential of the first end of the driving circuit 11 and the voltage value of Vdata is smaller than a predetermined voltage difference; the predetermined voltage difference may be selected according to practical situations, for example, the predetermined voltage difference may be 0.1V, 0.15V or 0.2V, but not limited thereto.

When the pixel circuit works, the holding stage can comprise a data writing time period and a light emitting time period which are set in sequence;

in the data writing time period included in the holding phase, the driving circuit 11 controls the communication between the first end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the potential of the control end of the driving circuit 11, the potential of the first end of the driving circuit 11 is not greatly different from the Vdata, and the potential of the second end of the driving circuit 11 is not greatly different from the Vdata;

the drive circuit 11 drives the light emitting element to emit light in the light emission period included in the holding period.

In the related art, when the potential of the first terminal of the driving circuit 11 and the potential of the second terminal of the driving circuit 11 are greatly different from Vdata in the data writing period included in the holding period, the characteristics of the driving transistor in the driving circuit 11 are affected, thereby being disadvantageous to the light emitting period included in the holding period and improving the flicker phenomenon.

When the pixel circuit works, in a data writing time period included in a holding stage, the difference between the potential of the first end of the driving circuit 11 and the Vdata is controlled to be not large, so that the parasitic capacitance between the grid of the driving transistor T0 and the source electrode between the grid and the T0 is charged, and the difference between the potential of the grid of the T0 and the Vdata + Vth is controlled to be not large, so that the flicker phenomenon is improved in the light emitting time period in the holding stage.

Optionally, the first control node may be a dc voltage terminal.

As shown in fig. 2, on the basis of the embodiment of the pixel circuit shown in fig. 1, the first control node is a power supply voltage terminal, the power supply voltage terminal is a direct current voltage terminal, and the power supply voltage terminal is used for providing a power supply voltage VDD;

the second end of the first tank circuit 13 is electrically connected to the supply voltage end.

In the data writing period included in the holding period, the data writing circuit 12 controls the writing node N5 to communicate with the first end of the driving circuit 11 under the control of the first control signal, and the potential of the first end of the driving circuit 11 (i.e., the potential of N2) is Vdata, so that the flicker phenomenon can be improved without increasing power consumption.

Optionally, the pixel circuit according to at least one embodiment of the present invention may further include a voltage control circuit;

As shown in fig. 3A, on the basis of the embodiment of the pixel circuit shown in fig. 1, the pixel circuit according to at least one embodiment of the present invention may further include a voltage control circuit 30;

the voltage control circuit 30 is electrically connected to a third control line S3, the Data line Data, and the first control node N6, and is configured to control the Data line Data and the first control node N6 to be communicated with each other under the control of a third control signal provided by the third control line S3.

When at least one embodiment of the pixel circuit shown in fig. 3A of the present invention is in operation, the refresh phase further includes a set time period set after the data write time period;

in the setting time period, the Data line Data provides a black-state voltage, the voltage control circuit 30 writes the black-state voltage into the first control node N6 under the control of the third control signal, and the potential of the write-in node N5 is raised under the action of the first energy storage circuit 13 to compensate the potential of N5;

the voltage value of the black state voltage is greater than the voltage value of the data voltage Vdata.

In at least one embodiment of the present invention, the voltage value of the black state voltage may be, for example, 7V, but is not limited thereto.

In an LTPO (low temperature poly oxide) pixel circuit, in the retention phase, there may be an on condition of a transistor included in the data writing circuit 12, there may be a voltage drop in the potential of N5, and the potential of N5 may be made not much different from Vdata by compensating for the potential of N5 in the set period in the refresh phase.

As shown in FIG. 3B, when VGMP is equal to Vdata, the flicker phenomenon is lightest; VGMP is a potential of the second node N2 in the data writing period in the holding period in the display period.

In fig. 3B, the vertical axis is S0, S0 is the flicker improvement degree, and the higher S0 is, the higher the flicker improvement degree is, and the lighter the flicker phenomenon is.

According to a specific embodiment, the write control circuit includes at least one write control transistor, a control electrode of the write control transistor is electrically connected to the second control line, a first electrode of the write control transistor is electrically connected to the data line, and a second electrode of the write control transistor is electrically connected to the write node.

In a specific implementation, the write control circuit may include at least one write control transistor, and when the number of the write control transistors is two or more, the two or more write control transistors are connected in parallel with each other.

According to another specific embodiment, the write control circuit includes N write control transistors connected in series with each other;

n is an integer greater than 1, and N is a positive integer less than N.

In a specific implementation, the write control circuit may include N write control transistors, and the N write control transistors are connected in series with each other.

According to a specific embodiment, the voltage control circuit comprises at least one voltage control transistor;

In a specific implementation, the voltage control circuit may include at least one voltage control transistor, and when the number of the voltage control transistors is two or more, the two or more voltage control transistors are connected in parallel with each other.

According to another specific embodiment, the voltage control circuit may include M voltage control transistors connected in series with each other;

m is an integer greater than 1, and M is a positive integer less than M.

In a specific implementation, the voltage control circuit may include M voltage control transistors, and the M voltage control transistors are connected in series with each other.

As shown in fig. 4, on the basis of the embodiment of the pixel circuit shown in fig. 1 of the present invention, the pixel circuit according to at least one embodiment of the present invention may further include a first light-emitting control circuit 411, a second light-emitting control circuit 412, a second tank circuit 42, a compensation control circuit 43, a first initialization circuit 44, a second initialization circuit 45, and a light-emitting element EL, wherein,

the first light-emitting control circuit 411 is electrically connected to a light-emitting control line EM, a power supply voltage end, and a first end of the driving circuit 11, and is configured to control the power supply voltage end to be communicated with the first end of the driving circuit 11 under the control of a light-emitting control signal provided by the light-emitting control line EM;

the second emission control circuit 412 is electrically connected to the emission control line EM, the second terminal of the driving circuit 11, and the first pole of the light-emitting element EL, respectively, and is configured to control communication between the second terminal of the driving circuit 11 and the first pole of the light-emitting element EL under the control of the emission control signal;

the second energy storage circuit 42 is electrically connected with the control end of the driving circuit 11 and is used for storing electric energy;

the compensation control circuit 43 is electrically connected to the second control line S2, the control end of the driving circuit 11, and the second end of the driving circuit 11, respectively, and is configured to control the communication between the control end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the second control signal;

the first initialization circuit 44 is respectively electrically connected to a RESET control line RESET, a first initial voltage end, and a control end of the driving circuit 11, and is configured to control writing of a first initial voltage Vinit1 provided by the first initial voltage end into the control end of the driving circuit 11 under the control of a RESET control signal provided by the RESET control line RESET;

the second initialization circuit 45 is electrically connected to the first control line P-GATE, a second initialization voltage terminal and the first pole of the light emitting element EL, respectively, and is configured to write a second initialization voltage Vinit2 provided by the second initialization voltage terminal into the first pole of the light emitting element EL under the control of the first control signal;

the second pole of the light-emitting element EL is electrically connected with the low-voltage end; the low voltage terminal is used for providing a low voltage VSS.

When the embodiment of the pixel circuit shown in fig. 4 of the present invention is in operation, the refresh phase includes a reset time period, a data write time period, and a light emitting time period that are set in sequence;

in a RESET period in the refresh phase, the first initialization circuit 44 controls writing of the first initial voltage Vinit1 provided by the first initial voltage terminal into the control terminal of the drive circuit 11 under the control of a RESET control signal provided by the RESET control line RESET, so that the drive circuit 11 can turn on the connection between the first terminal and the second terminal thereof at the start of the data write period;

in a Data writing time period in a refreshing stage, a Data voltage Vdata is provided by a Data line Data, a writing control circuit 14 provides the Data voltage Vdata to a writing node N5 under the control of a second control signal, and a Data writing circuit 12 controls the communication between the writing node N5 and a first end of a driving circuit 11 under the control of a first control signal so as to write the Data voltage Vdata into the first end of the driving circuit 11; the compensation control circuit 43 controls the communication between the control end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the second control signal; the second initialization circuit 45 writes a second initialization voltage Vinit2 provided by the second initialization voltage terminal into the first pole of the light emitting element EL under the control of the first control signal, so that the light emitting element EL does not emit light;

at the beginning of the data writing period in the refresh phase, the driving circuit 11 turns on the connection between the first terminal and the second terminal thereof, and changes the potential of the control terminal of the driving circuit 11 through charging until the potential of the control terminal of the driving circuit 11 becomes Vdata + Vth, the driving circuit 11 controls the disconnection between the first terminal thereof and the second terminal of the driving circuit 11, and Vth is the threshold voltage of the driving transistor included in the driving circuit 11;

in the light emission period in the refresh phase, the first light emission control circuit 411 controls the communication between the power supply voltage terminal and the first terminal of the driving circuit 11 under the control of the light emission control signal provided by the light emission control line EM, and the second light emission control circuit 412 controls the communication between the second terminal of the driving circuit 11 and the first pole of the light emitting element EL under the control of the light emission control signal; the drive circuit 11 drives the light emitting element EL to emit light.

In at least one embodiment of the present invention, the light emitting element EL may be an organic light emitting diode, a first electrode of the light emitting element EL is an anode, and a second electrode of the light emitting element EL is a cathode, but not limited thereto.

As shown in fig. 5, on the basis of the embodiment of the pixel circuit shown in fig. 1 of the present invention, the pixel circuit according to at least one embodiment of the present invention may further include a first light-emitting control circuit 411, a second light-emitting control circuit 412, a second tank circuit 42, a compensation control circuit 43, an on-off control circuit 40, a first initialization circuit 44, a second initialization circuit 45, and a light-emitting element EL;

the first light-emitting control circuit 411 is electrically connected to a light-emitting control line EM, a power voltage terminal, and a first terminal of the driving circuit 11, and is configured to control communication between the power voltage terminal and the first terminal of the driving circuit 11 under the control of a light-emitting control signal provided by the light-emitting control line EM;

the second emission control circuit 412 is electrically connected to the emission control line EM, the second terminal of the driving circuit 11, and the first electrode of the light emitting element EL, respectively, and is configured to control communication between the second terminal of the driving circuit 11 and the first electrode of the light emitting element EL under the control of the emission control signal;

the compensation control circuit 43 is electrically connected to the first control line PGATE, the second end of the driving circuit 11, and a second control node N0, respectively, and is configured to control the communication between the second end of the driving circuit 11 and the second control node N0 under the control of the first control signal;

the on-off control circuit 40 is electrically connected to the second control line S2, the control end of the driving circuit 11, and the second control node N0, and is configured to control the connection between the control end of the driving circuit 11 and the second control node N0 under the control of the second control signal;

the first initialization circuit 44 is electrically connected to a RESET control line RESET, a first initial voltage terminal, and the second control node N0, respectively, and is configured to write a first initial voltage Vinit1 provided by the first initial voltage terminal into the second control node N0 under the control of a RESET control signal provided by the RESET control line RESET;

the second initialization circuit 45 is electrically connected to the first control line P-GATE, the second initialization voltage terminal and the first pole of the light emitting element EL, respectively, and configured to write the second initialization voltage Vinit2 provided by the second initialization voltage terminal into the first pole of the light emitting element EL under the control of the first control signal;

the second electrode of the light emitting element EL is electrically connected to a low voltage terminal for providing a low voltage VSS.

When the embodiment of the pixel circuit shown in fig. 5 of the present invention is in operation, the refresh phase includes a reset time period, a data write time period, and a light emitting time period that are set in sequence;

in a RESET period in a refresh phase, the first initialization circuit 44 controls, under the control of a RESET control signal provided by the RESET control line RESET, to write a first initial voltage Vinit1 provided by the first initial voltage terminal into the second control node N0, and the on-off control circuit 40 controls, under the control of the second control signal, communication between the control terminal of the driving circuit 11 and the second control node N0, so that the driving circuit 11 can turn on the connection between the first terminal and the second terminal thereof at the beginning of the data writing period;

in a Data writing time period in a refreshing stage, a Data voltage Vdata is provided by a Data line Data, a writing control circuit 14 provides the Data voltage Vdata to a writing node N5 under the control of a second control signal, and a Data writing circuit 12 controls the communication between the writing node N5 and a first end of a driving circuit 11 under the control of a first control signal so as to write the Data voltage Vdata into the first end of the driving circuit 11; the compensation control circuit 43 controls the second end of the driving circuit 11 to be communicated with the second control node N0 under the control of the first control signal, and the on-off control circuit 40 controls the control end of the driving circuit 11 to be communicated with the second control node N0 under the control of the second control signal; the second initialization circuit 45 writes a second initialization voltage Vinit2 provided by the second initialization voltage terminal into the first pole of the light emitting element EL under the control of the first control signal, so that the light emitting element EL does not emit light;

at the beginning of the data writing period in the refresh phase, the driving circuit 11 turns on the connection between the first terminal and the second terminal thereof, and changes the potential of the control terminal of the driving circuit 11 through charging until the potential of the control terminal of the driving circuit 11 becomes Vdata + Vth, where the driving circuit 11 controls the disconnection between the first terminal thereof and the second terminal of the driving circuit 11, and Vth is the threshold voltage of the driving transistor included in the driving circuit 11;

in the light emission period in the refresh phase, the first light emission control circuit 411 controls the communication between the power supply voltage terminal and the first terminal of the driving circuit 11 under the control of the light emission control signal supplied from the light emission control line EM, and the second light emission control circuit 412 controls the communication between the second terminal of the driving circuit 11 and the first pole of the light emitting element EL under the control of the light emission control signal; the drive circuit 11 drives the light emitting element EL to emit light.

As shown in fig. 6, on the basis of at least one embodiment of the pixel circuit shown in fig. 4, the first control node is a power supply voltage terminal, and the power supply voltage terminal is used for providing a power supply voltage VDD; the write control circuit 14 includes a write control transistor Tc; the drive circuit 11 includes a drive transistor T0; the first tank circuit 13 comprises a first capacitor C1; the data write circuit 12 includes a data write transistor Tw;

the gate of the writing control transistor Tc is electrically connected to the second control line S2, the source of the writing control transistor Tc is electrically connected to the Data line Data, and the drain of the writing control transistor Tc is electrically connected to the writing node N5;

a first end of the first capacitor C1 is electrically connected to the write-in node N5, and a second end of the first capacitor C1 is electrically connected to the power supply voltage terminal;

a GATE of the data writing transistor Tw is electrically connected to the first control line P-GATE, a source of the data writing transistor Tw is electrically connected to the writing node, and a drain of the data writing transistor Tw is electrically connected to the source of the driving transistor T0;

the light emitting element is an organic light emitting diode O1, the first light emitting control circuit 411 includes a first transistor T1, the second light emitting control circuit 412 includes a second transistor T2, the second tank circuit 42 includes a second capacitor C2, the compensation control circuit 43 includes a third transistor T3, the first initialization circuit 44 includes a fourth transistor T4, and the second initialization circuit 45 includes a fifth transistor T5;

the grid electrode of the T1 is electrically connected with the light-emitting control line EM, the source electrode of the T1 is electrically connected with the power supply voltage end, and the drain electrode of the T1 is electrically connected with the source electrode of the T0;

the grid electrode of the T2 is electrically connected with the light-emitting control line EM, the source electrode of the T2 is electrically connected with the drain electrode of the T0, and the drain electrode of the T2 is electrically connected with the anode of the O1;

the first end of the C2 is electrically connected with the grid electrode of the T0, and the second end of the C2 is electrically connected with the power supply voltage end;

the grid electrode of the T3 is electrically connected with the second control line S2, the source electrode of the T3 is electrically connected with the grid electrode of the T0, and the drain electrode of the T3 is electrically connected with the drain electrode of the T0;

a grid electrode of the T4 is electrically connected with a RESET control line RESET, a source electrode of the T4 is electrically connected with a first initial voltage end, and a drain electrode of the T4 is electrically connected with a grid electrode of the T0; the first initial voltage end is used for providing a first initial voltage Vinit1;

the grid electrode of the T5 is electrically connected with the first control line P-GATE, the source electrode of the T5 is electrically connected with the second initial voltage end, and the drain electrode of the T5 is electrically connected with the anode of the O1;

the cathode of O1 is electrically connected to a low voltage terminal for providing a low voltage VSS.

In at least one embodiment of the pixel circuit shown in fig. 6, tc is an n-type transistor, tw is a p-type transistor, T1, T2 and T5 are p-type transistors, and T3 and T4 are n-type transistors, but not limited thereto;

tc, T3 and T4 may be oxide thin film transistors, tw, T1, T2 and T5 may be low temperature polysilicon thin film transistors, but not limited thereto.

In fig. 6, a first node is denoted by N1, a second node is denoted by N2, a third node is denoted by N3, N1 is electrically connected to the gate of T0, N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

In at least one embodiment of the pixel circuit shown in fig. 6, the second control signal provided by S2 and the RESET control signal provided by RESET may be, but are not limited to, scan signals provided by the same scan signal generating circuit.

As shown in fig. 7, when at least one embodiment of the pixel circuit shown in fig. 6 of the present invention is in operation, the refresh phase in the display period includes a reset period t1, a data write period t2, and a light emitting period t3;

during a RESET period T1 in the refresh phase, RESET provides a high voltage signal, S2 provides a low voltage signal, P-GATE provides a high voltage signal, EM provides a high voltage signal, T4 is turned on to write Vinit1 to N1, so that at the beginning of a data write period T2, T0 can be turned on;

in a Data writing time period T2 in the refreshing stage, RESET provides a low-voltage signal, S2 provides a high-voltage signal, P-Gate provides a low-voltage signal, data provides a Data voltage Vdata, T4 is turned off, tw and Tc are turned on, vdata is written into N5 and N2, and C1 maintains the potential of N5 to be Vdata;

in a Data writing time period T2 in the refreshing phase, RESET provides a low voltage signal, S2 provides a high voltage signal, P-Gate provides a low voltage signal, data provides a Data voltage Vdata, T3 is turned on, and T5 is turned on to write Vinit2 into the anode of O1 so that O1 does not emit light;

when a data writing time period T2 in the refreshing stage begins, T0 is turned on, vdata charges C2 through T0 and T3 to boost the potential of the gate of T0 until T0 is turned off, and the potential of N1 is Vdata + Vth at this time, where Vth is a threshold voltage of T0;

in the light-emitting time period T3 in the refreshing phase, EM provides a low-voltage signal, RESET provides a low-voltage signal, S2 provides a low-voltage signal, P-GATE provides a high-voltage signal, T1 and T2 are conducted, and T0 drives O1 to emit light.

In operation of at least one embodiment of the pixel circuit shown in fig. 6, the holding phase in the display period includes a data writing period and a light emitting period that are set in sequence;

in the data writing time period in the holding stage, the EM provides a high-voltage signal, the P-GATE provides a low-voltage signal, tw is turned on, N5 is communicated with N2, the potential of N2 is Vdata, T0 is turned on, and the potential of N3 is Vdata, so that the flicker phenomenon in the light emitting time period of the holding stage is improved on the premise of not increasing power consumption;

in the data writing period in the holding phase, T5 is turned on, and Vinit2 writes the anode of O1 so that O1 does not emit light;

in the light emitting time period in the holding phase, the EM provides a low voltage signal, the P-GATE provides a high voltage signal, T1 and T2 are turned on, and T0 drives O1 to emit light;

during the hold phase, S2 provides a low voltage signal and RESET provides a low voltage signal.

At least one embodiment of the pixel circuit shown in fig. 8 is different from at least one embodiment of the pixel circuit shown in fig. 6 in that the writing control circuit 14 includes a first writing control transistor Tc1, a second writing control transistor Tc2, and a third writing control transistor Tc3; tc1, tc2 and Tc3 are connected in parallel with each other;

a gate of Tc1 is electrically connected to the second control line S2, a source of Tc1 is electrically connected to the Data line Data, and a drain of Tc1 is electrically connected to the write node N5;

a gate of Tc2 is electrically connected to the second control line S2, a source of Tc2 is electrically connected to the Data line Data, and a drain of Tc2 is electrically connected to the write node N5;

a gate of Tc3 is electrically connected to the second control line S2, a source of Tc3 is electrically connected to the Data line Data, and a drain of Tc3 is electrically connected to the write node N5;

tc1, tc2 and Tc3 are all n-type transistors, tc1, tc2 and Tc3 are all oxide thin film transistors, but not limited thereto.

In at least one embodiment of the present invention, the number of the writing control transistors included in the writing control circuit 14 may be at least two, and at least two writing control transistors may be connected in parallel or in series.

As shown in fig. 9, on the basis of at least one embodiment of the pixel circuit shown in fig. 5, the first control node is a power supply voltage terminal, and the power supply voltage terminal is used for providing a power supply voltage VDD; the write control circuit 14 includes a write control transistor Tc; the drive circuit 11 includes a drive transistor T0; the first tank circuit 13 comprises a first capacitor C1; the data write circuit 12 includes a data write transistor Tw;

the light emitting element is an organic light emitting diode O1, the first light emitting control circuit 411 includes a first transistor T1, the second light emitting control circuit 412 includes a second transistor T2, the second tank circuit 42 includes a second capacitor C2, the compensation control circuit 43 includes a third transistor T3, the first initialization circuit 44 includes a fourth transistor T4, and the second initialization circuit 45 includes a fifth transistor T5; the on-off control circuit 40 includes a sixth transistor T6;

the grid electrode of the T3 is electrically connected with the first control line P-GATE, the source electrode of the T3 is electrically connected with the second control node N0, and the drain electrode of the T3 is electrically connected with the drain electrode of the T3;

the grid electrode of the T4 is electrically connected with a RESET control line RESET, the source electrode of the T4 is electrically connected with a first initial voltage end, and the drain electrode of the T4 is electrically connected with a second control node N0; the first initial voltage end is used for providing a first initial voltage Vinit1;

the grid electrode of the T6 is electrically connected with the second control line S2, the source electrode of the T6 is electrically connected with the grid electrode of the T0, and the drain electrode of the T6 is electrically connected with the second control node N0;

In at least one embodiment of the pixel circuit shown in fig. 9, tc is an n-type transistor, tw is a p-type transistor, T1, T2 and T5 are p-type transistors, T3 and T4 are p-type transistors, and T6 is an n-type transistor, but not limited thereto;

tc and T6 may be oxide TFTs, tw, T1, T2, T3, T4 and T5 may be LTPS TFTs, but not limited thereto.

In fig. 9, a first node is denoted by N1, a second node is denoted by N2, a third node is denoted by N3, N1 is electrically connected to the gate of T0, N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

In at least one embodiment of the pixel circuit shown in fig. 9, the first control signal provided by the P-GATE and the RESET control signal provided by the RESET may be the scan signal provided by the same scan signal generating circuit, but not limited thereto.

As shown in fig. 10, when at least one embodiment of the pixel circuit shown in fig. 9 of the present invention is in operation, the refresh phase in the display period includes a reset period t1, a data write period t2, and a light emitting period t3;

during a RESET period T1 in the refresh phase, RESET provides a low voltage signal, S2 provides a high voltage signal, P-GATE provides a high voltage signal, EM provides a high voltage signal, T4 and T6 are turned on to write Vinit1 to N1, so that at the beginning of a data write period T2, T0 can be turned on;

in a Data writing time period T2 in the refreshing stage, RESET provides a high-voltage signal, S2 provides a high-voltage signal, P-Gate provides a low-voltage signal, data provides a Data voltage Vdata, T4 is turned off, tw and Tc are turned on, vdata is written into N5 and N2, and C1 maintains the potential of N5 to be Vdata;

during a Data writing time period T2 in the refresh phase, RESET provides a high voltage signal, S2 provides a high voltage signal, P-Gate provides a low voltage signal, data provides a Data voltage Vdata, T3 is on, T6 is on, T5 is on, to write Vinit2 into the anode of O1 so that O1 does not emit light;

when a data writing time period T2 in the refreshing stage begins, T0 is turned on, vdata charges C2 through T0, T3 and T6 to boost the potential of the gate of T0 until T0 is turned off, and the potential of N1 is Vdata + Vth at this time, where Vth is a threshold voltage of T0;

in the light-emitting time period T3 in the refreshing phase, EM provides a low-voltage signal, RESET provides a high-voltage signal, S2 provides a low-voltage signal, P-GATE provides a high-voltage signal, T1 and T2 are conducted, and T0 drives O1 to emit light.

In operation of at least one embodiment of the pixel circuit shown in fig. 9, the holding phase in the display period includes a data writing period and a light emitting period that are set in sequence;

in the data writing time period in the holding stage, EM provides a high-voltage signal, P-GATE provides a low-voltage signal, tw is turned on, N5 is communicated with N2, the potential of N2 is Vdata, T0 is turned on, the potential of N3 is Vdata, T5 is turned on, and Vinit2 is written into the anode of O1, so that O1 does not emit light;

during the hold phase, S2 provides a low voltage signal and RESET provides a high voltage signal.

As shown in fig. 11, on the basis of at least one embodiment of the pixel circuit shown in fig. 4, the pixel circuit according to at least one embodiment of the present invention further includes a voltage control circuit 30;

the voltage control circuit 30 includes a voltage control transistor Tv;

a gate of the voltage control transistor Tv is electrically connected to a third control line S3, a source of the voltage control transistor Tv is electrically connected to the Data line Data, and a drain of the voltage control transistor Tv is electrically connected to a first control node N6;

the write control circuit 14 includes a write control transistor Tc; the driving circuit 11 includes a driving transistor T0; the first tank circuit 13 comprises a first capacitor C1; the data write circuit 12 includes a data write transistor Tw;

a first end of the first capacitor C1 is electrically connected to the write node N5, and a second end of the first capacitor C1 is electrically connected to the first control node N6;

In at least one embodiment of the pixel circuit shown in fig. 11, tc is an n-type transistor, tw is a p-type transistor, T1, T2 and T5 are p-type transistors, and T3 and T4 are n-type transistors, but not limited thereto;

tc, T3 and T4 may be oxide TFTs, tw, T1, T2 and T5 may be LTPS TFTs, but not limited thereto.

In fig. 11, a first node is denoted by N1, a second node is denoted by N2, a third node is denoted by N3, N1 is electrically connected to the gate of T0, N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

In at least one embodiment of the pixel circuit shown in fig. 11, the second control signal provided by S2, the RESET control signal provided by RESET, and the third control signal provided by S3 may be a scan signal provided by the same scan signal generating circuit, but not limited thereto.

As shown in fig. 12, when at least one embodiment of the pixel circuit shown in fig. 11 of the present invention is in operation, the refresh phase in the display cycle includes a reset time period t1, a data writing time period t2, a set time period t0, and a light emitting time period t3, which are sequentially set;

during a RESET time period T1 in the refresh phase, RESET provides a high voltage signal, P-GATE provides a high voltage signal, S2 provides a low voltage signal, S3 provides a low voltage signal, EM provides a high voltage signal, T4 is on, vinit1 writes N1, such that at the beginning of the data write time period T2, T0 can be turned on;

during a Data write period T2 in the refresh phase, RESET provides a low voltage signal, P-GATE provides a low voltage signal, S2 provides a high voltage signal, S3 provides a low voltage signal, EM provides a high voltage signal, data provides a Data voltage Vdata, T4 is off, T3 is on, tc is on, tw is on, tv is off, T5 is on, vinit2 writes the anode of O1 so that O1 does not emit light; t1 and T2 are switched off, and Vdata are written into N5 and N2;

when a data writing time period T2 in the refreshing stage begins, T0 is turned on, vdata charges C2 through T0 and T3 to boost the potential of the gate of T0 until T0 is turned off, the potential of N1 becomes Vdata + Vth, and Vth is a threshold voltage of T0;

in a set time period t0 in the refreshing phase, S2 provides a low-voltage signal, P-GATE provides a high-voltage signal, RESET provides a low-voltage signal, S3 provides a high-voltage signal, EM provides a high-voltage signal, data provides a signal which is changed from a Data voltage to a black-state voltage, the voltage value of the black-state voltage is larger than that of the Data voltage, tw is turned off, tc is turned on, and Tv is turned on so as to write the black-state voltage into N6, and the potential of N5 is boosted through the coupling effect of C1 so as to compensate the potential of N5; the voltage value of the black state voltage may be, for example, 7V, but is not limited thereto;

in the light emitting time period T3 in the refreshing phase, S2 provides a low voltage signal, P-GATE provides a high voltage signal, RESET provides a low voltage signal, S3 provides a low voltage signal, EM provides a low voltage signal, T1 and T2 are conducted, and T0 drives O1 to emit light.

In operation of at least one embodiment of the pixel circuit shown in fig. 11 of the present invention, during the hold phase of the display period, S2 provides a low voltage signal, and RESET provides a low voltage signal; the holding phase may include a data writing period and a light emitting period that are set in sequence;

in the data writing time period in the holding phase, the P-GATE provides a low voltage signal, the EM provides a high voltage signal, the Tw is opened to control the communication between the N5 and the N2, at the moment, the potential of the N5 has a voltage drop, and the potential of the N5 is compensated through the setting time period T0 in the refreshing phase, so that in the data writing time period in the holding phase, the potential of the N5 and the potential of the N2 do not greatly differ from the Vdata, and the T0 is opened, so that the potential of the N3 does not greatly differ from the Vdata, and the flicker phenomenon in the light emitting time period in the holding phase is improved on the premise of not increasing the power consumption;

in the data writing time period in the holding phase, T5 is turned on, vinit2 is written into the anode of O1, and O1 does not emit light;

in the light emitting period in the holding phase, the P-GATE provides a high voltage signal, the EM provides a low voltage signal, the T1 and the T2 are conducted, and the T0 drives the O1 to emit light.

The difference between the at least one embodiment of the pixel circuit shown in fig. 13 of the present invention and the at least one embodiment of the pixel circuit shown in fig. 11 of the present invention is as follows: the voltage control circuit 30 includes a first voltage control transistor Tv1 and a second voltage control transistor Tv2; tv1 and Tv2 are connected in parallel with each other;

the grid of Tv1 is electrically connected with a third control line S3, the source of Tv1 is electrically connected with the Data line Data, and the drain of Tv1 is electrically connected with a first control node N6;

the grid electrode of Tv2 is electrically connected with the third control line S3, the source electrode of Tv2 is electrically connected with the Data line Data, and the drain electrode of Tv2 is electrically connected with the first control node N6;

the write control circuit 14 includes a first write control transistor Tc1 and a second write control transistor Tc2; tc1 and Tc2 are connected in parallel with each other;

the gate of Tc2 is electrically connected to the second control line S2, the source of Tc2 is electrically connected to the Data line Data, and the drain of Tc2 is electrically connected to the write node N5.

In at least one embodiment shown in fig. 13, tv1, tv2, tc1 and Tc2 may all be n-type transistors, and Tv1, tv2, tc1 and Tc2 may all be oxide thin film transistors, but not limited thereto.

In at least one embodiment of the present invention, the voltage control circuit 30 may further include at least three voltage control transistors connected in parallel, and the write control circuit 14 may include at least three write control transistors connected in parallel.

The difference between the at least one embodiment of the pixel circuit shown in fig. 14 of the present invention and the at least one embodiment of the pixel circuit shown in fig. 11 of the present invention is as follows: the voltage control circuit 30 includes a first voltage control transistor Tv1 and a second voltage control transistor Tv2; tv1 and Tv2 are connected in series;

the grid of Tv1 and the grid of Tv2 are both electrically connected with a third control line S3;

the source electrode of the T2 is electrically connected with the Data line Data, the drain electrode of the T2 is electrically connected with the source electrode of the T1, and the drain electrode of the T1 is electrically connected with a first control node N6;

the write control circuit 14 includes a first write control transistor Tc1 and a second write control transistor Tc2; tc1 and Tc2 are connected in series;

the grid of Tc1 and the grid of Tc2 are both electrically connected with a second control line S2;

the source of Tc2 is electrically connected to the Data line Data, the drain of Tc2 is electrically connected to the source of Tc1, and the drain of T1 is electrically connected to the write node N5.

In at least one embodiment shown in fig. 14, tv1, tv2, tc1 and Tc2 may all be n-type transistors, and Tv1, tv2, tc1 and Tc2 may all be oxide thin film transistors, but not limited thereto.

In at least one embodiment of the present invention, the voltage control circuit 30 may further include at least three voltage control transistors connected in series, and the write control circuit 14 may include at least three write control transistors connected in series.

As shown in fig. 15, on the basis of at least one embodiment of the pixel circuit shown in fig. 5, the pixel circuit according to at least one embodiment of the present invention further includes a voltage control circuit 30;

the voltage control circuit 30 includes a voltage control transistor Tv;

the gate of the voltage control transistor Tv is electrically connected to a third control line S3, the source of the voltage control transistor Tv is electrically connected to the Data line Data, and the drain of the voltage control transistor Tv is electrically connected to a first control node N6;

the write control circuit 14 includes a write control transistor Tc; the drive circuit 11 includes a drive transistor T0; the first tank circuit 13 comprises a first capacitor C1; the data write circuit 12 includes a data write transistor Tw;

In at least one embodiment of the pixel circuit shown in fig. 15, tc is an n-type transistor, tw is a p-type transistor, T1, T2 and T5 are p-type transistors, T3 and T4 are p-type transistors, and T6 is an n-type transistor, but not limited thereto;

tc and T6 may be oxide thin film transistors, tw, T1, T2, T3, T4 and T5 may be low temperature polysilicon thin film transistors, but not limited thereto.

In fig. 15, a first node is denoted by N1, a second node is denoted by N2, a third node is denoted by N3, N1 is electrically connected to the gate of T0, N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

In at least one embodiment of the present invention, the voltage control circuit 30 may further include at least two voltage control transistors connected in parallel, and the write control circuit 14 may include at least two write control transistors connected in parallel; alternatively, the voltage control circuit 30 may further include at least two voltage control transistors connected in parallel and in series, and the write control circuit 14 may include at least two write control transistors connected in series.

The driving method of the embodiment of the invention is applied to the pixel circuit, and the display period comprises a refreshing stage and a maintaining stage; the driving method includes:

in a holding stage, a write control circuit controls the data line and the write node to be disconnected under the control of a second control signal, and the first energy storage circuit maintains the potential of the write node;

and in the data writing time period included in the holding stage, the data writing circuit controls the communication between the writing node and the first end of the driving circuit under the control of the first control signal.

In the driving method according to the embodiment of the present invention, in the data writing period included in the holding stage, the data writing circuit controls the connection between the writing node N5 and the first end of the driving circuit 11 under the control of the first control signal, so that the difference between the potential of the first end of the driving circuit and the data voltage is not large, and the flicker phenomenon can be improved without increasing power consumption.

In a specific implementation, the pixel circuit may further include a voltage control circuit; the refresh phase further comprises a set time period set after the data write time period; the driving method further includes:

in the setting time period, the signal provided by the data line is changed from a data voltage to a black state voltage, and the voltage control circuit writes the signal provided by the data line into a first control node under the control of a third control signal;

In an LTPO (low temperature poly oxide) pixel circuit, in a keeping stage, a transistor included in a data writing circuit is opened, the potential of a writing node is dropped, and the potential of the writing node is compensated in a setting time period in a refreshing stage, so that the potential of the writing node is not greatly different from the data voltage in the data writing time period in the keeping stage, and the flicker phenomenon is improved.

The display device provided by the embodiment of the invention comprises the pixel circuit.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiment of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made therein without departing from the principles of the invention as set forth in the appended claims.

Claims

1. A pixel circuit comprises a drive circuit, a data write circuit, a first tank circuit and a write control circuit,

the writing control circuit is respectively and electrically connected with a second control line, a data line and the writing node and is used for controlling the communication between the data line and the writing node under the control of a second control signal provided by the second control line;

the drive circuit is used for controlling the communication between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of the control end of the drive circuit;

the pixel circuit also comprises a voltage control circuit;

2. The pixel circuit of claim 1, wherein the first control node is a dc voltage terminal.

3. The pixel circuit according to claim 2, wherein the write control circuit comprises at least one write control transistor having a control electrode electrically connected to the second control line, a first electrode electrically connected to the data line, and a second electrode electrically connected to the write node.

4. The pixel circuit according to claim 2, wherein the write control circuit includes N write control transistors connected in series with each other;

a first pole of the nth write control transistor is electrically connected to a second pole of the (n + 1) th write control transistor;

n is an integer greater than 1, and N is a positive integer less than N.

5. The pixel circuit according to claim 1, wherein the voltage control circuit comprises at least one voltage control transistor;

6. The pixel circuit according to claim 1, wherein the voltage control circuit comprises M voltage control transistors connected in series with each other;

a first pole of the mth voltage control transistor is electrically connected to a second pole of the m +1 th voltage control transistor;

m is an integer greater than 1, and M is a positive integer less than M.

7. A pixel circuit as claimed in claim 1 or 2, wherein the first tank circuit comprises a first capacitor; the data write circuit includes a data write transistor;

8. The pixel circuit according to claim 1 or 2, further comprising a first light emission control circuit, a second tank circuit, a compensation control circuit, a first initialization circuit, a second initialization circuit, and a light emitting element, wherein,

the second light-emitting control circuit is respectively electrically connected with the light-emitting control line, the second end of the driving circuit and the first pole of the light-emitting element and is used for controlling the communication between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal;

the compensation control circuit is respectively and electrically connected with the second control line, the control end of the driving circuit and the second end of the driving circuit, and is used for controlling the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the second control signal;

the second initialization circuit is respectively electrically connected with the first control line, a second initial voltage end and the first pole of the light-emitting element and is used for writing a second initial voltage provided by the second initial voltage end into the first pole of the light-emitting element under the control of the first control signal;

the second pole of the light emitting element is electrically connected with the low voltage end.

9. The pixel circuit according to claim 1 or 2, further comprising a first light emission control circuit, a second tank circuit, a compensation control circuit, an on-off control circuit, a first initialization circuit, a second initialization circuit, and a light emitting element;

10. A driving method applied to the pixel circuit according to any one of claims 1 to 9, wherein the display period includes a refresh phase and a hold phase; the driving method includes:

11. The driving method according to claim 10, wherein the pixel circuit further includes a voltage control circuit; the refresh phase further comprises a set time period set after the data write time period; the driving method further includes:

12. A display device comprising the pixel circuit according to any one of claims 1 to 9.