CN115048226A - Virtual control system and method of multi-core heterogeneous processor - Google Patents
Virtual control system and method of multi-core heterogeneous processor Download PDFInfo
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- CN115048226A CN115048226A CN202210972805.7A CN202210972805A CN115048226A CN 115048226 A CN115048226 A CN 115048226A CN 202210972805 A CN202210972805 A CN 202210972805A CN 115048226 A CN115048226 A CN 115048226A
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
A virtual control system for a multi-core heterogeneous processor, comprising: a multi-core heterogeneous processor comprising at least two processor cores of different architectures; the virtual control terminal is configured on each processor core and used for managing virtual input and output hardware resources and physical input and output hardware resources connected with the processor core; the resource allocation module is connected with the virtual control terminal and used for allocating virtual input and output hardware resources for the processor core and establishing connection between the virtual input and output hardware resources and physical input and output hardware resources, wherein one physical input and output hardware resource is connected with one of a plurality of virtual input and output hardware resources corresponding to the physical input and output hardware resource; and the communication module is connected with the virtual control terminals on the processor cores and used for checking the physical input and output hardware resource information of different hardware domains among the virtual control terminals. The application also provides a virtual control method of the multi-core heterogeneous processor, which is convenient for checking input and output information among cores of each core processor.
Description
Technical Field
The present application relates to the field of processor technologies, and in particular, to a virtual control system and method for a multi-core heterogeneous processor.
Background
In the current large SOC (System on chip) design, multiple cores are different in structure for a trend, a plurality of processor cores with different architectures are often arranged in one chip, and a plurality of different peripherals, i.e. physical input and output hardware resources, such as input and output interfaces of DDR video, various high-speed data interfaces (such as USB, PCIE, etc.) and various slow peripherals (such as SPI, UART, I2C, I2S, etc.) are also arranged in the SOC, and due to the different architectures of the different processor cores, the hardware resources (such as a terminal controller, a clock controller, input and output hardware resources, etc.) connected with the processor cores form a closed hardware domain, so that the physical input and output hardware resources in one hardware domain can only be accessed by the processor cores in the hardware domain, but cannot be accessed by other processor cores. Therefore, in the prior art, when a chip is designed, each processor core is often configured with its dedicated physical input/output hardware resource. On one hand, the method causes waste of physical input and output hardware resources, and on the other hand, log check among different processor cores is difficult.
Disclosure of Invention
In order to solve the defects in the prior art, the present application aims to provide a virtual control system and method for a multi-core heterogeneous processor, which are easy to manage physical hardware resources and convenient for checking hardware resource information among processor cores.
To achieve the above object, the present application provides a virtual control system of a multi-core heterogeneous processor, including,
the multi-core heterogeneous processor comprises at least two processor cores with different architectures, wherein hardware resources connected with the processor cores respectively form a plurality of hardware domains which are isolated from each other on hardware, and the hardware resources comprise virtual input and output hardware resources;
the virtual control terminal is configured on each processor core and used for managing virtual input and output hardware resources and physical input and output hardware resources connected with the processor core;
the resource allocation module is connected with the virtual control terminal and used for allocating virtual input and output hardware resources for the processor core and establishing connection between the virtual input and output hardware resources and physical input and output hardware resources, wherein one physical input and output hardware resource is connected with one of a plurality of virtual input and output hardware resources corresponding to the physical input and output hardware resource;
and the communication module is connected with the virtual control terminals on the processor cores and used for checking the physical input and output hardware resource information of different hardware domains among the virtual control terminals.
Further, there are 1 physical input/output hardware resource of the same type, and the physical input/output hardware resource is connected to a virtual input/output hardware resource of any processor core by default.
Further, the types of operating systems configured on the processor cores are the same or different.
Further, the communication module includes a Mailbox module and a shared memory, where the Mailbox module is used to transmit an inter-core message, and the inter-core message is used to notify the virtual control terminal of a read-write instruction in the shared memory; the shared memory is at least provided with an instruction buffer and a log buffer for each processor core, wherein the instruction buffer is used for caching instructions received by the processor core to which the instruction buffer belongs, and the log buffer is used for caching input and output information written by the processor core to which the log buffer belongs.
In order to achieve the above object, the present application further provides a virtual control method for a multi-core heterogeneous processor, including:
a first virtual control terminal sends an input/output information acquisition instruction to a second virtual control terminal, wherein the first virtual control terminal is configured on a first processor core, the second virtual control terminal is configured on a second processor core, and the first processor core is configured with physical input/output hardware resources;
based on the input and output information acquisition instruction, the second virtual control terminal acquires the input and output information of the processor core of the second virtual control terminal from the virtual input and output hardware resource of the processor core of the second virtual control terminal, and sends the input and output information to the first virtual control terminal;
and the first virtual control terminal controls the physical input and output hardware resource to check and print the input and output information.
Furthermore, the virtual control terminals communicate with each other through inter-core messages and a shared memory.
Further, the specific step of mutual communication between the first virtual control terminal and the second virtual control terminal through the inter-core message and the shared memory includes:
the method comprises the steps that a first virtual control terminal sends an input/output information acquisition instruction to an instruction buffer of a second processor core in a shared memory, and the instruction buffer is used for caching the instruction;
the first virtual control terminal informs the second virtual control terminal of acquiring the instruction from the instruction buffer through the inter-core message;
based on the instruction, the second virtual control terminal acquires input and output information from a virtual input and output hardware resource connected with the second processor core, writes the input and output information into a log buffer of the second processor core, and informs the first virtual control terminal through an inter-core message, wherein the log buffer is used for caching the input and output information;
and the first virtual control terminal acquires the input and output information from the log buffer.
In order to achieve the above object, the present application further provides a system chip, which includes the virtual control system of the multi-core heterogeneous processor as described above.
To achieve the above object, the electronic device provided in the present application includes the system chip as described above.
To achieve the above object, the present application provides a computer readable storage medium having stored thereon computer instructions, which, when executed, perform the steps of the virtual control method for a multi-core heterogeneous processor as described above.
The virtual control system and method of the multi-core heterogeneous processor easily and dynamically configure the input and output hardware resources for the heterogeneous processor cores, reduce the waste of the input and output hardware resources, and facilitate the access of the input and output hardware resource information among the processor cores.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not limit the application. In the drawings:
FIG. 1 is a schematic structural diagram of a virtual control system of a multi-core heterogeneous processor according to the present application;
fig. 2 is a schematic structural diagram of a communication module of the present application;
FIG. 3 is a flowchart illustrating a virtual control method of a multi-core heterogeneous processor according to the present application;
FIG. 4 is a schematic block diagram of an electronic device of the present application;
fig. 5 is a schematic diagram of a storage medium of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustration purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It is noted that references to "a", "an", and "the" modifications in this application are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise. "plurality" is to be understood as two or more.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Example 1
Fig. 1 is a schematic structural diagram of a virtual control system of a multi-core heterogeneous processor according to the present application, and as shown in fig. 1, the virtual control system of the multi-core heterogeneous processor according to the present application includes two heterogeneous processor cores 10 and 30, a communication module 20, a resource configuration module 40, and a physical input/output hardware resource 50, where a virtual control terminal 11 is configured on the processor core 10, a virtual control terminal 31 is configured on the processor core 30, the virtual control terminal 11 and the virtual control terminal 31 are communicatively connected through the communication module 20, the virtual control terminal 11 and the virtual control terminal 31 are connected to the resource configuration module 40, and the resource configuration module 40 is connected to the physical input/output hardware resource 50.
It can be understood that, because the processor cores 10 and 30 are in a heterogeneous configuration, there is no cache coherence hardware between them, and the hardware domains formed by the interrupt controller, the clock controller and the memory of each processor core are hard isolated, each processor core cannot be directly and uniformly scheduled by the operating system, and the hardware resources in the hardware domain of each processor core can only be accessed by its processor core.
Illustratively, processor core 10 is a Cortex-R processor core, processor core 30 is a Cortex-A processor core, and the two processor cores run the same or different operating systems, including but not limited to Android, Linux, QNX, and FREERTOS.
The virtual control terminal is used for managing virtual input and output hardware resources and physical input and output hardware resources connected with the processor core; the resource allocation module 40 is configured to allocate virtual input/output hardware resources to the processor core, and establish connection between the virtual input/output hardware resources and physical input/output hardware resources; the communication module 20 is used for virtually controlling physical input and output hardware resource information of different hardware domains among the terminals.
It should be noted that the virtual I/o hardware resources correspond to physical I/o hardware resources, where the physical I/o hardware resources include, but are not limited to, DDR video input/output interfaces, various high-speed data interfaces (such as USB, PCIE, etc.), and various slow peripherals (such as SPI, UART, I2C, I2S, etc.).
For example, if the physical input/output hardware resource is a physical serial port, the virtual input/output hardware resource is a virtual serial port.
As shown in fig. 1, the resource configuration module 40 includes a first virtual serial port 41, a second virtual serial port 42, and a driver 43, where the first virtual serial port is configured for the processor core 10, the second virtual serial port is configured for the processor core 30, the first virtual serial port is connected with a physical input/output hardware resource 50 through the driver 43, and the physical input/output hardware resource 50 is a physical serial port.
In the present embodiment, the physical input/output hardware resource 50 is connected to the first virtual serial port 41 by default, that is, the physical input/output hardware resource 50 is configured to the processor core 10 for use, in other embodiments, the physical input/output hardware resource 50 is configured to a processor core with better performance and faster starting speed by default.
Fig. 2 is a schematic structural diagram of a communication module according to the present application, as shown in fig. 2, wherein the communication module 20 includes a shared memory 21 and a Mailbox module 22; the shared memory 21 is configured with an instruction buffer2110 and a log buffer2111 for the virtual control terminal 11, and is configured with an instruction buffer2310 and a log buffer2311 for the virtual control terminal 31; the instruction buffer is used for caching an instruction of the virtual control terminal of the instruction sending end so as to be acquired by the virtual control terminal responding to the instruction, and the log buffer is used for caching input and output information of the virtual control terminal responding to the instruction so as to be acquired by the virtual control terminal of the instruction sending end; the Mailbox module 22 is configured to transmit an inter-core message, where the inter-core message is used to notify a virtual control terminal at the other end of the Mailbox module 22 to read and write an instruction into the shared memory.
The embodiment of the application is used for using 1 physical serial port, and under the condition that the physical serial ports are reduced, the printing logs and the debugging system can still be conveniently checked by a plurality of heterogeneous processor cores.
Illustratively, the working process of the embodiment of the application is as follows: because the current physical serial port is configured to the processor core 10, the input/output information on the processor core 30 can be checked on the processor core 10, the virtual control terminal 11 of the processor core 10 sends an input/output information acquisition instruction to the instruction buffer2310 of the processor core 30 in the shared memory 21, meanwhile, the Mailbox module 22 sends an inter-core message to notify the processor core 30 to read the instruction in the instruction buffer2310, the processor core 30 responds after reading the instruction from the instruction buffer2310, the input/output information is written into the log buffer2311, and meanwhile, the Mailbox module 22 sends the inter-core message to notify the processor core 10 to read the input/output information from the log buffer2311 for subsequent storage and printing check.
Example 2
One embodiment of the present application provides a virtual control system of a multi-core heterogeneous processor, which is used for viewing input and output information in different hardware domains between processor cores.
The present embodiment differs from embodiment 1 in that: in this embodiment, dedicated physical serial ports are configured for both the processor core 10 and the processor core 30, and at this time, both the processor core 10 and the processor core 30 can mutually check and print the input and output information of the processor core of the other side through the dedicated physical serial ports.
Example 3
One embodiment of the present application provides a virtual control method for a multi-core heterogeneous processor, which is used for checking input and output information in different hardware domains between processor cores.
Fig. 3 is a flowchart illustrating a virtual control method of a multi-core heterogeneous processor according to the present application, and the virtual control method of the multi-core heterogeneous processor according to the present application will be described in detail with reference to fig. 3:
step S101: a first virtual control terminal sends an input/output information acquisition instruction to a second virtual control terminal, wherein the first virtual control terminal is configured on a first processor core, the second virtual control terminal is configured on a second processor core, and the first processor core is configured with physical input/output hardware resources;
step S102: based on the input and output information acquisition instruction, the second virtual control terminal acquires the input and output information of the processor core of the second virtual control terminal from the virtual input and output hardware resource of the processor core of the second virtual control terminal, and sends the input and output information to the first virtual control terminal;
step S103: and the first virtual control terminal controls the physical input and output hardware resource to check and print the input and output information.
It should be noted that, in this embodiment, 1 virtual input/output hardware resource is configured for each processor core, and a physical input/output hardware resource is configured to the first processor core with better performance and faster start speed by default.
It should be noted that the virtual input/output hardware resources correspond to physical input/output hardware resources, where the physical input/output hardware resources include, but are not limited to, DDR video input/output interfaces, various high-speed data interfaces (such as USB, PCIE, etc.), and various slow-speed peripherals (such as SPI, UART, I2C, I2S, etc.
Further, the virtual control terminals communicate with each other through inter-core messages and a shared memory;
it should be noted that, the shared memory is configured with an instruction buffer and a log buffer for both the first processor core and the second processor core, and in the method of the present embodiment, since the physical input/output hardware resource is default configured to the first processor core with better performance and faster starting speed, the method of the present application mainly looks up the input/output information on the second processor core on the first processor core, and in the process of mutual communication between the whole virtual control terminals, the instruction buffer and the log buffer of the second processor core play an important role, but the instruction buffer and the log buffer of the first processor core do not play a role; the instruction buffer is used for caching the instructions received by the processor core to which the instruction buffer belongs, and the log buffer is used for caching input and output information written by the processor core to which the instruction buffer belongs; the inter-core message is transmitted through the Mailbox module and used for informing the opposite virtual control terminal of reading and writing instructions into the shared memory.
As a preferred embodiment, the specific step of mutual communication between the first virtual control terminal and the second virtual control terminal through the inter-core message and the shared memory includes:
the method comprises the steps that a first virtual control terminal sends an input and output information acquisition instruction to an instruction buffer of a second processor core in a shared memory, and the instruction buffer is used for caching the instruction;
the first virtual control terminal informs the second virtual control terminal of acquiring the instruction from the instruction buffer through the inter-core message;
based on the instruction, the second virtual control terminal acquires input and output information from a virtual input and output hardware resource connected with the second processor core, writes the input and output information into a log buffer of the second processor core, and informs the first virtual control terminal through an inter-core message, wherein the log buffer is used for caching the input and output information;
and the first virtual control terminal acquires the input and output information from the log buffer.
The embodiment of the application is used for using 1 physical serial port, and under the condition that the physical serial ports are reduced, the printing logs and the debugging system can still be conveniently checked by a plurality of heterogeneous processor cores.
Example 4
One embodiment of the present application provides a virtual control method for a multi-core heterogeneous processor, which is used for checking input and output information in different hardware domains between processor cores.
The embodiment of the application is different from embodiment 2 in that in this embodiment, dedicated physical serial ports are configured for both the first processor core and the second processor core, and at this time, both the first processor core and the second processor core can mutually check and print input and output information of the processor core of the other processor through the dedicated physical serial ports.
Example 5
In this embodiment, a system chip is further provided, which includes the virtual control system of the multi-core heterogeneous processor in the foregoing embodiment.
Example 6
In this embodiment, an electronic device is further provided, and fig. 4 is a schematic block diagram of the electronic device provided in this application. As shown in fig. 4, the electronic device 130 includes a virtual control system 131 of a multi-core heterogeneous processor and a memory 132. The memory 132 is used to store non-transitory computer readable instructions (e.g., one or more computer program modules). The processor core in the virtual control system 131 of the multi-core heterogeneous processor is configured to execute non-transitory computer readable instructions, which when executed by the processor core in the virtual control system 131 of the multi-core heterogeneous processor may perform one or more steps of the virtual control method of the multi-core heterogeneous processor described above. The memory 132 and the virtual control system 131 of the multi-core heterogeneous processor may be interconnected by a bus system and/or other form of connection mechanism (not shown).
For example, the processor core of the virtual control system 131 of the multi-core heterogeneous processor may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), or other form of processing unit having data processing capability and/or program execution capability, such as a Field Programmable Gate Array (FPGA), or the like; for example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. Which may be a general-purpose processor core or a special-purpose processor core, may control other components in electronic device 130 to perform desired functions.
For example, memory 132 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (cache), and/or the like. The non-volatile memory may include, for example, Read Only Memory (ROM), hard disk, Erasable Programmable Read Only Memory (EPROM), portable compact disk read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by the virtual control system 131 of the multi-core heterogeneous processor to implement various functions of the electronic device 130. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium.
It should be noted that, in the embodiment of the present application, reference may be made to the above description on the virtual control method of the multi-core heterogeneous processor for specific functions and technical effects of the electronic device 130, and details are not described here again.
Example 7
In this embodiment, a computer-readable storage medium is further provided, and fig. 5 is a schematic diagram of a storage medium according to the present application. As shown in fig. 5, storage medium 150 is used to store non-transitory computer readable instructions 151. For example, the non-transitory computer readable instructions 151, when executed by a computer, may perform one or more steps in a virtual control method according to a multi-core heterogeneous processor described above.
For example, the storage medium 150 may be applied to the electronic device 130 described above. For example, the storage medium 150 may be the memory 132 in the electronic device 130 shown in fig. 4. For example, the related description about the storage medium 150 may refer to the corresponding description of the memory 132 in the electronic device 130 shown in fig. 4, and is not repeated here.
It should be noted that the storage medium (computer-readable medium) described above in the present application may be a computer-readable signal medium or a non-transitory computer-readable storage medium or any combination of the two. The non-transitory computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the above. More specific examples of the non-transitory computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
In the present application, a non-transitory computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In this application, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a non-transitory computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.
The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.
Computer program code for carrying out operations for aspects of the present application may be written in any combination of one or more programming languages, including but not limited to an object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units described in the embodiments of the present application may be implemented by software or hardware. Where the name of an element does not in some cases constitute a limitation on the element itself.
The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), systems on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), and the like.
The above description is only a few embodiments of the present application and is intended to be illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure herein is not limited to the particular combination of features described above, but also encompasses other arrangements formed by any combination of the above features or their equivalents without departing from the spirit of the disclosure. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the application. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (10)
1. A virtual control system of a multi-core heterogeneous processor is characterized by comprising,
the multi-core heterogeneous processor comprises at least two processor cores with different architectures, wherein hardware resources connected with the processor cores respectively form a plurality of hardware domains which are isolated from each other on hardware, and the hardware resources comprise virtual input and output hardware resources;
the virtual control terminal is configured on each processor core and used for managing virtual input and output hardware resources and physical input and output hardware resources connected with the processor core;
the resource allocation module is connected with the virtual control terminal and used for allocating virtual input and output hardware resources for the processor core and establishing connection between the virtual input and output hardware resources and physical input and output hardware resources, wherein one physical input and output hardware resource is connected with one of a plurality of virtual input and output hardware resources corresponding to the physical input and output hardware resource;
and the communication module is connected with the virtual control terminals on the processor cores and used for checking the physical input and output hardware resource information of different hardware domains among the virtual control terminals.
2. The virtual control system of the multi-core heterogeneous processor according to claim 1, wherein 1 physical input/output hardware resource of the same type is provided and is connected to a virtual input/output hardware resource of any processor core by default.
3. The virtual control system of a multi-core heterogeneous processor according to claim 1, wherein types of operating systems configured on the respective processor cores are the same or different.
4. The virtual control system of the multi-core heterogeneous processor according to claim 1, wherein the communication module includes a Mailbox module and a shared memory, the Mailbox module is used for transmitting an inter-core message, and the inter-core message is used for notifying a virtual control terminal to read and write an instruction into the shared memory; the shared memory is at least provided with an instruction buffer and a log buffer for each processor core, wherein the instruction buffer is used for caching instructions received by the processor core to which the instruction buffer belongs, and the log buffer is used for caching input and output information written by the processor core to which the log buffer belongs.
5. A virtual control method of a multi-core heterogeneous processor comprises the following steps:
a first virtual control terminal sends an input/output information acquisition instruction to a second virtual control terminal, wherein the first virtual control terminal is configured on a first processor core, the second virtual control terminal is configured on a second processor core, and the first processor core is configured with physical input/output hardware resources;
based on the input and output information acquisition instruction, the second virtual control terminal acquires the input and output information of the processor core of the second virtual control terminal from the virtual input and output hardware resource of the processor core of the second virtual control terminal, and sends the input and output information to the first virtual control terminal;
and the first virtual control terminal controls the physical input and output hardware resource to check and print the input and output information.
6. The virtual control method of the multi-core heterogeneous processor according to claim 5, wherein the virtual control terminals communicate with each other through inter-core messages and a shared memory.
7. The virtual control method of the multi-core heterogeneous processor according to claim 6, wherein the specific step of mutual communication between the first virtual control terminal and the second virtual control terminal through the inter-core message and the shared memory comprises:
the method comprises the steps that a first virtual control terminal sends an input/output information acquisition instruction to an instruction buffer of a second processor core in a shared memory, and the instruction buffer is used for caching the instruction;
the first virtual control terminal informs the second virtual control terminal of acquiring the instruction from the instruction buffer through the inter-core message;
based on the instruction, the second virtual control terminal acquires input and output information from a virtual input and output hardware resource connected with the second processor core, writes the input and output information into a log buffer of the second processor core, and informs the first virtual control terminal through an inter-core message, wherein the log buffer is used for caching the input and output information;
and the first virtual control terminal acquires the input and output information from the log buffer.
8. A system-on-chip comprising the virtual control system of the multi-core heterogeneous processor of any one of claims 1 to 4.
9. An electronic device, characterized in that the electronic device comprises the system-on-chip of claim 8.
10. A computer-readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the virtual control method of a multi-core heterogeneous processor of any one of claims 5 to 7.
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