CN115037984A - High-efficiency reversing control system and method based on video decoding chip - Google Patents
High-efficiency reversing control system and method based on video decoding chip Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440218—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60Q—ARRANGEMENT OF SIGNALLING OR LIGHTING DEVICES, THE MOUNTING OR SUPPORTING THEREOF OR CIRCUITS THEREFOR, FOR VEHICLES IN GENERAL
- B60Q9/00—Arrangement or adaptation of signal devices not provided for in one of main groups B60Q1/00 - B60Q7/00, e.g. haptic signalling
- B60Q9/008—Arrangement or adaptation of signal devices not provided for in one of main groups B60Q1/00 - B60Q7/00, e.g. haptic signalling for anti-collision purposes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
- B60R1/00—Optical viewing arrangements; Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles
- B60R1/20—Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles
- B60R1/22—Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles for viewing an area outside the vehicle, e.g. the exterior of the vehicle
- B60R1/23—Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles for viewing an area outside the vehicle, e.g. the exterior of the vehicle with a predetermined field of view
- B60R1/26—Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles for viewing an area outside the vehicle, e.g. the exterior of the vehicle with a predetermined field of view to the rear of the vehicle
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/414—Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
- H04N21/41422—Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance located in transportation means, e.g. personal vehicle
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/44016—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving splicing one content stream with another content stream, e.g. for substituting a video clip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/47—End-user applications
- H04N21/488—Data services, e.g. news ticker
- H04N21/4882—Data services, e.g. news ticker for displaying messages, e.g. warnings, reminders
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a high-efficiency reversing control system based on a video decoding chip, which comprises a reversing system, a decoding chip, a microcontroller MCU, a flash memory unit, a liquid crystal display screen and a system level chip SOC, wherein the decoding chip is connected with the microcontroller MCU; a high-efficiency reversing control method based on a video decoding chip is characterized in that a microcontroller MCU inputs a channel switching instruction to the decoding chip through an IIC integrated circuit bus, and performs switching control on a normal interface data flow channel corresponding to a low-voltage differential signal LVDS input by a system-on-chip SOC and a reversing interface data flow channel corresponding to a composite synchronous video broadcast signal input by a reversing system; the decoding chip can output the input image data stream to the liquid crystal display screen for display after carrying out corresponding image quality adjustment and synthesis processing on the input image data stream so as to achieve the realization of the reversing function. The invention releases the system resources occupied by the backing function of the original SOC terminal, solves the bad phenomena of unstable part of the system, blocked picture, delayed backing image output, slower quick backing response and the like, and improves the user experience.
Description
Technical Field
The invention relates to the field of vehicle-mounted electronics, in particular to a high-efficiency reversing control system and method based on a video decoding chip.
Background
In the current vehicle-mounted reversing scheme, most Kernel in SOC (system on chip) integrating Linux or Android and other operating systems controls a single camera to output a reversing image NTSC (abbreviation of National Television Standards Committee, which means (american) National Television Standards Committee), this document only generates a "composite synchronous video broadcast signal" which is the same as CVBS) picture, and the scheme occupies more OS (operating system) resources and generally has a low reversing response speed. Especially, in the process of the host starting stage, because the system needs more threads to be started, the adverse phenomena of system instability, image jamming, backing image output delay, slow fast backing response and the like can occur. Reducing the user experience.
The safety guarantee function of 'warning words' cannot be directly prompted in the NTSC picture of the common reversing image composite synchronous video broadcast signal. If the requirement of the warning language prompting function needs to be completed, an OS (operating system) is required to synthesize the warning language picture and the original camera composite synchronous video broadcast signal NTSC and then output the synthesized warning language picture and the original camera composite synchronous video broadcast signal NTSC to a screen for display after the NTSC picture is obtained. Such a scheme would again increase OS-related resources, causing more significant image sticking and delays, further reducing user experience.
In the vehicle-mounted reversing system in the early-stage mass-produced host project, the operating system OS occupies more system resources in the reversing process, so that the quick reversing starting time is slow (about 3.0 s), and the quick reversing starting time specification (less than 1.2 s) of the current newly developed project cannot be met. Meanwhile, the operating system OS occupies more system resources, which causes the adverse phenomena of unstable system, blocked picture, delayed display of a reverse picture, slow response of rapid reverse and the like, and the user experience is low.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides an efficient reverse control system and method based on a video decoding chip, which release system resources occupied by the reverse function of an original SOC terminal, solve the problems of unstable part of the system, blocked pictures, delayed reverse image output, slower reverse response and the like, and improve the user experience.
The object of the invention is achieved on the one hand by: a high-efficiency reverse control method based on a video decoding chip comprises the following steps:
1) the microcontroller MCU inputs a channel switching instruction to the decoding chip through the IIC integrated circuit bus, and performs switching control on a normal interface data flow channel corresponding to the low-voltage differential signal LVDS input by the system-on-chip SOC and a data flow channel of the backing interface corresponding to the composite synchronous video broadcast signal input by the backing system;
2) when the data flow channel of the normal interface is switched, the decoding chip processes the video signal output by the SOC and outputs the video signal to the liquid crystal display screen;
3) when the data flow channel of the reversing interface is switched, the warning words stored in the peripheral flash memory unit are synthesized into a reversing image composite synchronous video broadcast signal picture by the decoding chip, then the warning words are converted into a double-path low-voltage differential signal LVDS signal, and the double-path low-voltage differential signal LVDS signal is output to the liquid crystal display screen.
Further, the step 2) specifically includes:
2-1) the microcontroller MCU inputs a normal interface data flow channel switching instruction corresponding to the low voltage differential signal LVDS input by the system level chip SOC into the decoding chip through the IIC integrated circuit bus;
2-2) the system level chip SOC outputs a normal interface data stream corresponding to the low voltage differential signal LVDS to a decoding chip;
2-3) the decoding chip outputs the processed low-voltage differential signal LVDS to a liquid crystal display screen for displaying.
Further, the step 3) specifically includes:
3-1) the microcontroller MCU inputs a data stream channel switching instruction of a backing interface corresponding to a composite synchronous video broadcast signal input by the backing system into a decoding chip through an IIC integrated circuit bus;
3-2) the reversing system outputs the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal to a decoding chip;
3-3) the decoding chip carries out image synthesis on the warning language picture acquired from the flash memory unit through the SPI serial peripheral interface and the backing interface corresponding to the composite synchronous video broadcast signal input by the backing system; the synthesized reversing image is converted into a two-way low-voltage differential signal LVDS for output through the inside of a decoding chip;
and 3-4) outputting the synthesized two-way low-voltage differential signal LVDS to a liquid crystal display screen for displaying by the decoding chip.
The object of the invention is achieved in another aspect by: a high-efficiency reversing control system based on a video decoding chip comprises a reversing system, a decoding chip, a microcontroller MCU, a flash memory unit, a liquid crystal display screen and a system on chip SOC;
the decoding chip is used for decoding the composite synchronous video broadcast signal of the reversing system acquired through the CVBS input port and outputting the video signal to the liquid crystal display screen through the dual-path low-voltage differential signal LVDS output port;
the microcontroller MCU is connected with the decoding chip through an IIC integrated circuit bus, is used for receiving and transmitting normal data, and realizes the switching of a normal picture and a reversing picture channel of the host machine through the operation of a register of the decoding chip;
the flash memory unit is connected with the decoding chip through a serial peripheral interface and is used for storing an alarm language picture;
the system-on-chip SOC is used for outputting a video signal to a decoding chip through a low-voltage differential signal LVDS;
the reversing system is used for outputting the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal to the decoding chip;
and the liquid crystal display screen is used for displaying the normal picture and the reversing picture after the synthesis processing of the decoding chip.
Furthermore, a digital video input end, an analog signal input end, a display output end, an SPI serial peripheral interface and an IIC integrated circuit bus are arranged on the decoding chip.
Further, the digital video input end is connected with the system-on-chip SOC and is used for receiving a low-voltage differential signal LVDS signal output by the system-on-chip SOC;
the analog signal input end is connected with the reversing system and used for receiving a composite synchronous video broadcast signal video signal of the reversing system;
the display output end is connected to the liquid crystal display screen and used for displaying images;
the SPI serial peripheral interface is connected to the flash memory unit and used for acquiring warning language picture information accessed in the flash memory unit;
the IIC integrated circuit bus is connected to the microcontroller MCU and used for controlling the display chip.
By adopting the technical scheme, compared with the prior art, the invention has the beneficial effects that: the video decoding chip is used for controlling the reversing picture, system resources occupied by the reversing function of the SOC end originally are released, the problems of instability of partial systems, picture jamming, reversing image output delay, slow reversing response and the like are solved, and user experience is improved, wherein the quick reversing starting time can be reduced to be less than 1.2s from about 3.0 s; the video decoding chip can also utilize OSD (On-Screen-Display) technology to synthesize the warning language pictures stored in the FLASH of the peripheral FLASH memory unit into a reversing image composite synchronous video broadcast signal NTSC picture, and then the pictures are converted into a two-way signal low-voltage differential LVDS signal through the inside of the decoding chip and output to a Screen for displaying, so that the reversing function efficiency and the safety are improved; the control method of the video decoding chip utilizes the microcontroller MCU to switch and control the channels of the normal interface and the backing interface output by the display chip through the IIC integrated circuit bus instruction, thereby achieving the realization of the backing function.
Drawings
FIG. 1 is a schematic diagram of the system of the present invention.
FIG. 2 shows the internal structure and part of the external interface of the decoding chip of the present invention.
FIG. 3 is a normal mode block diagram of the present invention.
FIG. 4 is a schematic diagram of the data flow within the normal interface of the present invention.
FIG. 5 is a block diagram of a reverse mode of the present invention.
FIG. 6 is a schematic diagram of the internal data flow of the reverse interface of the present invention.
FIG. 7 is a circuit diagram of the decoding chip and the MCU.
FIG. 8 is a schematic diagram of the connection between the decoding chip and the SOC circuit of the system on chip.
FIG. 9 is a schematic diagram of the circuit connection between the decoding chip and the LCD panel according to the present invention.
FIG. 10 is a schematic diagram of the circuit connection between the decoding chip and the flash memory unit according to the present invention.
FIG. 11 is a schematic circuit diagram of a flash memory cell of the present invention.
Fig. 12 is a schematic circuit diagram of a microcontroller MCU according to the present invention.
FIG. 13 is a schematic circuit diagram of the system on chip SOC of the present invention.
Detailed Description
The high-efficiency reversing control system based on the video decoding chip shown in fig. 1 comprises a reversing system, a decoding chip, a microcontroller MCU, a flash memory unit, a liquid crystal display screen and a system on chip SOC;
the decoding chip is used for decoding the composite synchronous video broadcast signal of the reversing system acquired through the CVBS input port and outputting the video signal to the liquid crystal display screen through the dual-path low-voltage differential signal LVDS output port;
the microcontroller MCU is connected with the decoding chip through the IIC integrated circuit bus, is used for receiving and transmitting normal data, and realizes the switching of the normal picture and the reversing picture channel of the host machine through the operation of a register of the decoding chip;
the flash memory unit is connected with the decoding chip through a serial peripheral interface and is used for storing an alarm language picture;
the system level chip SOC is used for outputting the video signal to the decoding chip through the low-voltage differential signal LVDS;
the reversing system is used for outputting the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal to the decoding chip;
the liquid crystal display screen is used for displaying the normal picture and the reverse picture after the synthesis processing of the decoding chip.
As shown in fig. 2, the decoding chip is provided with a digital video input terminal, an analog signal input terminal, a display output terminal, an SPI serial peripheral interface, and an IIC integrated circuit bus.
The Digital Video input end (Digital Video input) is connected with the SOC and used for receiving a low-voltage differential LVDS signal output by the SOC;
an Analog video input (VIN 1) is connected to the reversing system for receiving a composite synchronous video broadcast signal NTSC video signal of the reversing system;
the Display output end (LVDS Dual or VLDS Single low voltage differential signal, double-path or Single-path) is connected to the liquid crystal Display screen and is used for displaying images;
the SPI serial peripheral interface is connected to the flash memory unit and used for acquiring warning language picture information accessed in the flash memory unit;
the IIC integrated circuit bus is connected to the microcontroller MCU and used for controlling the display chip.
The decoding chip internal image processing unit:
after entering a Digital Video input terminal (Digital Video input), a low-voltage differential LVDS signal output by the system-level chip SOC passes through: LVDS Rx (LVDS input), Digital I/F (Digital interface), RGB/YC conversion;
after a composite synchronous video broadcast signal NTSC video signal of the reversing system enters an Analog video input end (Analog video input), the composite synchronous video broadcast signal NTSC video signal respectively passes through: ADC (Analog-to-Digital Converter), Video Decoder, I/P conversion, reduction scaling, Expansion scaling;
then, the video input source channel is selected by a multiplexer mux (multiplexer), and the signals are respectively subjected to YC offset, gain, Y contrast, Hue adjustment, YC/RGB conversion, Area selection, RGB contrast, RGB offset, Gamma correction, ROM-OSD (ROM, OSD image synthesis), gather/FRC (error diffusion/Frame Rate Control), LCD I/F (LCD interface), and finally output to the liquid crystal display screen through LVDS Tx (LVDS output).
A high-efficiency reverse control method based on a video decoding chip comprises the following steps:
1) the microcontroller MCU inputs a channel switching instruction to the decoding chip through the IIC integrated circuit bus, and performs switching control on a normal interface data flow channel corresponding to the low-voltage differential signal LVDS input by the system-on-chip SOC and a data flow channel of the backing interface corresponding to the composite synchronous video broadcast signal input by the backing system;
2) when the data flow channel of the normal interface is switched, the decoding chip processes the video signal output by the SOC and outputs the video signal to the liquid crystal display screen;
as shown in fig. 3-4, step 2 specifically includes:
2-1) the microcontroller MCU inputs a normal interface data flow channel switching instruction corresponding to the low voltage differential signal LVDS input by the system level chip SOC to the decoding chip through the IIC integrated circuit bus;
2-2) the system on chip SOC outputs the normal interface data stream corresponding to the low voltage differential signal LVDS to the decoding chip;
2-3) the decoding chip outputs the processed low-voltage differential signal LVDS to a liquid crystal display TFT-LCD for displaying.
3) When the data flow channel of the reversing interface is switched, the warning words stored in the peripheral flash memory unit are synthesized into a reversing image composite synchronous video broadcast signal picture by the decoding chip, then the warning words are converted into a two-way low-voltage differential signal LVDS signal, and the two-way low-voltage differential signal LVDS signal is output to the liquid crystal display.
As shown in fig. 5-6, step 3 specifically includes:
3-1) the microcontroller MCU inputs a data stream channel switching instruction of a reverse interface corresponding to a composite synchronous video broadcast signal NTSC input by the reverse system to a decoding chip through an IIC integrated circuit bus;
3-2) the reversing system outputs the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal NTSC to a decoding chip;
3-3) the decoding chip carries out image synthesis on a warning language picture acquired from the FLASH memory unit FLASH through the SPI serial peripheral interface and a reversing interface corresponding to a composite synchronous video broadcast signal NTSC input by the reversing system; the synthesized reversing image is converted into a double-path low-voltage differential signal LVDS for output through the interior of a decoding chip;
and 3-4) outputting the synthesized two-way low-voltage differential signal LVDS to a liquid crystal display TFT-LCD by the decoding chip for displaying.
As shown in fig. 7, the decoding chip is connected to the microcontroller MCU (fig. 12) through the IIC integrated circuit bus interface, and acquires the composite synchronous video broadcast signal NTSC video signal of the car backing system (CAMERA SYSTEM) through the CVBS input port;
a composite synchronous video broadcast signal (NTSC is connected to a decoding chip VIN1 (72 pin) through a hard wire CAMERA _ CVBS) output by the external backing system (CAMERA SYSTEM);
the pin SCL (25pin) and the pin SDA (26 pin) of the decoding chip are connected to the hard MCU _ I2CL0_3V3_ SCL and the MCU _ I2CL0_3V3_ SDA in the microcontroller MCU (fig. 12) through hard wires 86304_ IIC _ SCL and 86304_ IIC _ SDA, and are connected to the pins RIIC0SDL (27 pin) and RIIC0SDA (26 pin) of the microcontroller MCU.
As shown in fig. 8, the decoding chip obtains the video signal of the system on chip SOC (fig. 13) through the low voltage differential signal LVDS input port; LVDS input pin RD0AN (102 pin) of the decoding chip,
RD0 (103 pin), RD1 (104 pin), RD1 (105 pin), RD2 (106 pin), RD2 (107 pin), RCKAN (108 pin), RCKAP (109 pin), RD3 (110 pin), RD3 (111 pin) are connected to MIPI _ DSI _ DATA _ N (AN 15), MIPI _ DSI _ DATA _ P (AR15pin), MIPI _ DSI _ DATA _ N (AN17pin), MIPI _ DSI _ DATA _ P (AR17pin), MIPI _ DATA _ N (AM16pin), MIPI _ AP _ DATA _ P (MIPI _ AP _ DATA _ pin), MIPI _ DATA _ N (AM14pin), MIPI _ DATA _ P (MIPI _ DATA _ P) (MIPI _ DATA _ P (MIPI _ DATA _ pin), MIPI _ DATA _ P (MIPI _ DATA _ P) (MIPI _ DATA _ pin), MIPI _ AP _ DATA _ AP _ pin (MIPI _ AP16 _ AP _ DATA _ pin), MIPI _ DATA _ AP _ DATA _ P (MIPI _ AP _ DATA _ pin).
As shown in fig. 9, the decoding chip outputs the video signal to a TFT-LCD (liquid crystal display) through a dual low voltage differential signaling LVDS output port;
LVDS output pins TD3AP (49pin), TD3AN (50pin), TCKAP (51pin), TCKAN (52pin), TD2AP (53pin), TD2AN (54pin), TD1AP (55pin), TD1AN (56pin), TD0AP (57pin), TD0AN (58pin), TD3BP (37pin), TD3BN (38pin), TCKBP (39pin), TCKBN (40pin), TD2BP (41pin), TD2BN (42pin), TD1BP (43pin), TD1BN (44pin), TD0BP (45pin), TD0BN (46pin) of the decoding chip are connected with hard wires ODD _ LVDS _ DATA3_ P, ODD _ LVDS _ DATA3_ P
ODD _ LVDS _ CLK _ P, ODD _ LVDS _ CLK _ P, ODD _ LVDS _ DATA2_ P, ODD _ LVDS _ DATA2_ P, ODD _ LVDS _ DATA1_ P, ODD _ LVDS _ DATA1_ P, ODD _ LVDS _ DATA0_ P, ODD _ LVDS _ DATA0_ P, EVEN _ LVDS _ DATA3_ P, EVEN _ LVDS _ DATA3_ P, EVEN _ LVDS _ CLK _ P, EVEN _ LVDS _ CLK _ P, EVEN _ LVDS _ DATA2_ P, EVEN _ LVDS _ DATA2_ P, EVEN _ LVDS _ DATA1_ P, EVEN _ LVDS _ DATA1_ P, EVEN _ LVDS _ DATA0_ LVDS _ P, EVEN _ LVDS _ DATA0_ P is connected to the liquid crystal display TFT-LCD.
As shown in fig. 10, the decoding chip obtains the "warning language" picture in the flash memory unit (fig. 11) through the SPI serial peripheral interface;
the SPI pins QSD3(14pin), QSD2(15pin), QSD1(16pin), QSD0(17pin), QSCK (18pin), QSCS (19pin) of the decoding chip are connected to pin HOLD #/IO3(7pin), WP #/IO2(3pin), SO/IO1(2pin), SI/IO0 (5 pin), SCLK (6 pin), CS # (1pin) of the FLASH unit FLASH (fig. 11) through hardwires 86304_ FLASH _ SPI _ D3, 86304_ FLASH _ SPI _ D2, 86304_ FLASH _ SPI _ D1, 86304_ FLASH _ SPI _ D0, 86304_ FLASH _ SPI _ CLK, 86304_ FLASH _ SPI _ CS.
When the invention works, the microcontroller MCU is connected with the decoding chip through the IIC integrated circuit bus interface, the baud rate of 400bps can meet the receiving and transmitting of normal data, the microcontroller MCU can realize the switching of the DA (host) normal picture and the reversing picture channel through the operation of the decoding chip register, and the time specification (less than 1.2 s) of the rapid reversing start is met.
The FLASH memory unit FLASH can store a warning language picture, the warning language picture is connected with the decoding chip through the SPI serial peripheral interface, the microcontroller MCU sends a corresponding warning language instruction to the decoding chip through the IIC integrated circuit bus, the decoding chip acquires the warning language picture in the FLASH memory unit FLASH through the SPI serial peripheral interface instruction, and the warning language picture is synthesized with a composite synchronous video broadcast signal NTSC video signal output by the reversing system, and finally a double-path LVDS (low voltage differential signaling) reversing image picture with warning language safety prompt information is output.
The invention controls the decoding chip through the IIC integrated circuit bus based on the microcontroller MCU, realizes short starting time (less than 1.2 s) for rapid backing, can output the safety prompt function requirement of 'warning language', and improves the user experience and the safety.
The present invention is not limited to the above-mentioned embodiments, and based on the technical solutions disclosed in the present invention, those skilled in the art can make some substitutions and modifications to some technical features without creative efforts according to the disclosed technical contents, and these substitutions and modifications are all within the protection scope of the present invention.
Claims (6)
1. A high-efficiency reverse control method based on a video decoding chip is characterized by comprising the following steps:
1) the microcontroller MCU inputs a channel switching instruction to the decoding chip through the IIC integrated circuit bus, and performs switching control on a normal interface data flow channel corresponding to the low-voltage differential signal LVDS input by the system-level chip SOC and a data flow channel of the backing interface corresponding to the composite synchronous video broadcast signal input by the backing system;
2) when the data flow channel of the normal interface is switched, the decoding chip processes the video signal output by the SOC and outputs the video signal to the liquid crystal display screen;
3) when the data flow channel of the reversing interface is switched, the warning words stored in the peripheral flash memory unit are synthesized into a reversing image composite synchronous video broadcast signal picture by the decoding chip, then the warning words are converted into a double-path low-voltage differential signal LVDS signal, and the double-path low-voltage differential signal LVDS signal is output to the liquid crystal display screen.
2. The efficient reversing method based on the video decoding chip according to claim 1, wherein the step 2) specifically comprises:
2-1) the microcontroller MCU inputs a normal interface data flow channel switching instruction corresponding to the low voltage differential signal LVDS input by the system level chip SOC to the decoding chip through the IIC integrated circuit bus;
2-2) the system on chip SOC outputs the normal interface data stream corresponding to the low voltage differential signal LVDS to the decoding chip;
2-3) the decoding chip outputs the processed low-voltage differential signal LVDS to a liquid crystal display screen for displaying.
3. The efficient reversing method based on the video decoding chip according to claim 1, wherein the step 3) specifically comprises:
3-1) the microcontroller MCU inputs a data stream channel switching instruction of a backing interface corresponding to the composite synchronous video broadcast signal input by the backing system to a decoding chip through an IIC integrated circuit bus;
3-2) the reversing system outputs the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal to a decoding chip;
3-3) the decoding chip carries out image synthesis on the warning language picture acquired from the flash memory unit through the SPI serial peripheral interface and the backing interface corresponding to the composite synchronous video broadcast signal input by the backing system; the synthesized reversing image is converted into a double-path low-voltage differential signal LVDS for output through the interior of a decoding chip;
and 3-4) the decoding chip outputs the synthesized two-way low voltage differential signal LVDS to a liquid crystal display screen for displaying.
4. A high-efficiency reversing control system based on a video decoding chip comprises a reversing system, and is characterized by further comprising a decoding chip, a microcontroller MCU, a flash memory unit, a liquid crystal display screen and a system on chip SOC;
the decoding chip is used for decoding the composite synchronous video broadcast signal of the reversing system acquired through the CVBS input port and outputting the video signal to the liquid crystal display screen through the dual-path low-voltage differential signal LVDS output port;
the microcontroller MCU is connected with the decoding chip through an IIC integrated circuit bus, is used for receiving and transmitting normal data, and realizes the switching of a normal picture and a reversing picture channel of the host machine through the operation of a register of the decoding chip;
the flash memory unit is connected with the decoding chip through a serial peripheral interface and is used for storing an alarm language picture;
the system-on-chip SOC is used for outputting a video signal to a decoding chip through a low-voltage differential signal LVDS;
the reversing system is used for outputting the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal to the decoding chip;
and the liquid crystal display screen is used for displaying the normal picture and the reversing picture after the synthesis processing of the decoding chip.
5. The efficient reversing control system based on the video decoding chip as claimed in claim 4, wherein the decoding chip is provided with a digital video input terminal, an analog signal input terminal, a display output terminal, an SPI serial peripheral interface and an IIC integrated circuit bus.
6. The efficient reversing control system based on the video decoding chip according to claim 5, wherein the digital video input terminal is connected to the system-on-chip SOC and is configured to receive a low-voltage differential signal LVDS output by the system-on-chip SOC;
the analog signal input end is connected with the reversing system and used for receiving a composite synchronous video broadcast signal video signal of the reversing system;
the display output end is connected to the liquid crystal display screen and used for displaying images;
the SPI serial peripheral interface is connected to the flash memory unit and used for acquiring warning language picture information accessed in the flash memory unit;
the IIC integrated circuit bus is connected to the microcontroller MCU and used for controlling the display chip.
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