TW201016002A - System and method for processing multi-interface image signals - Google Patents

Abstract

A method for processing multi-interface image signals includes the following steps. An analog image signal is received via a first interface in a data input processing unit and is converted to a first digital image signal, and a second digital image signal is received via a second interface and is decoded to a third digital image signal. The first digital image signal or the third digital image signal is outputted from the data input processing unit to a scaler according to a control signal by a switch device. The first digital image signal or the third digital image signal is scaled by the scaler according to a resolution, and a digital image output signal is outputted to a timing controller and at least one line buffer, wherein the capacity of the line buffer corresponds to the resolution. A data signal is outputted from the timing controller.

Description

201016002

TW4133PA Nine, invention description: [Technical field of the invention] A multi-interface image, and particularly related to one can reduce the cost. The present invention relates to a method of image signal processing. Hole number processing system and integrated interface of the same type [Prior Art]

Nowadays, the application of flat panel display is high in resolution, and in order to achieve high resolution requirements, the digital video interface (DVI) and the dual data transmission path (dual 1 ink) are usually used to receive the image signal to the latter stage. The action of the circuit for image processing. Please refer to FIG. 1 , which is a block diagram of a conventional flat panel display. The flat display 100 receives the digital video signals of the DVI format via the first DVI interface 112 and the second DVI interface 114, and then respectively receives the first Minimized Differential Signal (TMDS) receiver 122 and the second TMDS. The receiver 124 converts the received digital image signal to the clock controller 13A, and the clock controller 130 outputs the data signal Data to the source driving unit 14A, so that the source driving unit 14 drives the panel 150 to A high-resolution image screen is displayed, for example, an image plane with a resolution of 1440x960. The above-mentioned flat panel display 1 utilizes a dual data transmission path and MDS receivers 122 and 124 to save bandwidth, so that the panel 15 得以 can display a high-resolution image without being affected by the bandwidth problem 201016002

The cost of applying a larger number of TMDS receivers to comply with the TMDS receiver is higher. When the requirements of the image are met, it is bound to meet the bandwidth requirements, which will make the manufacturing cost higher. In addition, today, the planar display of the image resolution is generally low, usually The D-Sub interface is used to receive the image signal to the subsequent circuit for image processing and the DVI interface is less used. However, if the DVI interface is used, the circuit design complexity will increase and the signal quality will be poor. Integrating the DVI interface and the D-Sub interface to make the flat panel display more widely used is a subject of industry efforts. SUMMARY OF THE INVENTION The present invention relates to a multi-interface image signal processing system and method using a scaler The simple architecture integrates multiple interfaces into a single package of wafers, which makes the multi-interface image signal processing system have the advantages of small size and low cost. According to the first aspect of the present invention, a multi-interface image signal processing system is proposed, 'Applies to a flat panel display. The flat panel display includes a panel and source driver unit. The source driving unit drives the panel in a resolution image. The multi-interface image signal processing system includes a data input processing unit, a scaler, a line buffer and a clock controller. The data input processing unit A type of analog-to-digital conversion XJXf, a decoder and a switching device. The analog digital converter receives and converts an analog image signal into a first digital image via a first interface.

TW4133PA number. The decoder is a third digital image signal via a second interface technique. Switching device:::: digital video signal and decoder, according to _ control signal control, ratio, bit conversion first digital image signal or third digital image signal, early element output material input processing unit 'and receive by data wheel Entry list ': coupled to the first received digital video signal or the third digit received by the digital video signal or the third digit according to the resolution of the resolution, and output - digital image transmission two / shirt image The signal is used to temporarily store the digital image output signal, and the line buffers the resolution of the second line. The clock controller according to the number (four) image = corresponding to the ; number to the source drive unit, so that the source drive single; out - data moving panel. According to the data signal, according to the second aspect of the present invention, the method of the invention comprises the following steps. At the image signal: the first interface receives and converts - the analog image 2 = the Γ Γ via the image signal, and the second digital image is the second digital image through the second octave image - the third digital image two is a digital image image Signal to-shrink = output the first-digit image signal or the third-digit first-digit material is calculated according to the resolution of the received signal, and the digital image signal is scaled by the moving line to slow the heart's _ line, buffer The size of the device is at least - = according to the digital image round. Clock Enables the source driver unit to drive a panel based on the data signal. 8 201016002

After the TW4133PA, the panel displays one of the image screens corresponding to the resolution. In order to make the above-mentioned content of the present invention more comprehensible, a preferred embodiment will be described below with reference to the accompanying drawings, which are described in detail below: 牛 [Embodiment] The present invention provides a multi-interface image signal processing. The system and method, combined with the function of the scaler, integrate multiple interfaces into a single package of wafers in a simple architecture, resulting in reduced manufacturing cost of the multi-interface image signal processing system. Referring to Figure 2A, a block diagram of a flat panel display in accordance with a preferred embodiment of the present invention is shown. The flat panel display 2 includes a panel Μ. The source driving unit 220, the first interface 232, the second interface 234, and the multi-interface image signal processing system 240. The panel 210 is used to display an image book, which can correspond to various resolutions, for example, an ultra-high resolution of 2560 x 1600. The source driving unit 220 is used to drive the panel 210. The multi-interface image signal processing system 240 is substantially packaged in a single wafer 'which includes a data input processing unit 250, a scaler 270, an in-line buffer 280, and a timing controller 290. . The data input processing unit 250 includes an analog to digital converter (ADC) 252, a decoder 254, and a switching device 260. The analog-to-digital converter 252 receives an analog image signal AS via the first interface 232. The analog image signal AS is, for example, a D-Sub video signal.

TW4133PA number. The analog digital converter 252 converts the analog video signal AS into a first digital video signal DS1. The first digital video signal DS1 is a Transistor-Transistor Logic (TTL) video signal. It conforms to the signal format required by the clock controller 290. The decoder 254 receives a second digital video signal DS2 via the second interface 234. The second digital video signal DS2 is, for example, a digital video interface (DVI) video signal or a high-definition multimedia interface. , HMI) video signal. The decoder 254 is essentially a - minimized transition differential signal (Transition Minimized Plus, TM (6) numerator, decodes the second digital video signal hall into a third number = like signal DS3', the third digital image signal coffee For the transistor one frame: the body logic image signal to meet the signal required by the clock controller 26 ° to the text bit converter 252 and the decoder 254, with the signal CS control data input point " No. DS1 or:: 5〇 The first digital image is outputted to the data input processing unit, and the first digital image outputted by 〇250 is outputted. The input processing early element, wherein the scaler 27 is based on the second; The resolution of the first-digital image signal coffee or & =, the action of zooming, and outputting the image-digital image or the third number; ^ output signal. If the first bit is corresponding to sfl竣DS3 Shadow 201016002

The resolution of the TW4133PA image is lower than the resolution corresponding to the panel 210. When the S is turned up (up SGaIe), the scaler is converted to a higher resolution. Only the lower resolution is to be resolved if the image of the third digit of the digital image signal DS14 is higher than the panel 2)): == 270 is turned down (d_ action, also; The resolution is converted to a lower resolution. The image screen corresponding to the scaler 27q ❿ reference signal will match the at least one line buffer 280 corresponding to the panel 2ig for the digital image output signal. The size of the line buffer #280 is Corresponding to the resolution corresponding to the panel 21 。. In the embodiment, the size of the line buffer 28 较佳 is preferably, for example, 2560 bits, so that the resolution of the scaler 27 can be up to The ultra-high resolution is 2560x1600, and the panel 21〇 can display the ultra-high resolution image surface. However, the size of the 'line buffer 280 can be more than 2560 bits, so the panel 210 can display more than the super high. In addition, if the panel 210 is driven by the polarity conversion method of 2-line conversion (2_line inversi), two line buffers are preferably required in the present embodiment. Coupled to the scaler 270, according to the number The image output signal 'outputs a data signal Data to the source driving unit 220, so that the source driving unit 220 drives the panel 210 according to the data signal Data. Wherein 'corresponding to the signal format required by the source driving unit 220, the data signal Data is A low swing differential signal (Reduced Swing 11 201016002

TW4133PA

Differential Signal, RSDS) or a low voltage differential signal (L〇w

Voltage Differential Signa LVDS). ❿ In addition, the control signal CS can be rotated by a microprocessor. Referring to Figure 2, there is shown a block diagram of a flat panel display in accordance with a preferred embodiment of the present invention. Compared to the flat panel display 200, the flat panel display 2, the multi-interface image signal processing system 240 further includes a microprocessor 2 rib. The microprocessor 265 outputs the control signal cs to the switching device 260 in accordance with a priority setting. For example, if the multi-interface video signal processing system 24 receives the analog video signal AS after receiving the second digital video signal DS2, the priority setting is such that the video signal processing system 24 receives the analog video signal AS after receiving the second digital video signal DS2. The controller 265 controls the switching device 26 to transmit the first image signal DSU scaler 27〇 without transmitting the third number to 270 22 or the third digital image signal _ for zooming. The image screen corresponding to the scene/image round-off signal conforms to the above-mentioned unveiled photo 200, and the function of the interface image signal processing system 200 and the amplifier is different in different interface images (4). The number can be used to make the multi-interface interface integrated into a single package of wafers with a wider number of digital video signals. The manufacturing cost of the Daihu processing system is reduced, and in addition, if the source drive _ is one anti-1^, the signal format required for the slave premise 220 is the output that can be output by the clock controller 290. Used for 12 201016002

The start signal (not shown in the figure) of the TW4133PA trigger source drive unit 2 2 is changed from the dynamic mode to the current drive mode. In this way, the source drive unit 22 is triggered by the bilateral trigger mode. Therefore, the circuit components required for the voltage driving mode can be omitted, and the cost is further reduced. In this embodiment, a multi-interface image signal processing method is further disclosed, and the multi-interface of the present invention is better than the seventh embodiment; Like a machine. In step S300, a data ΓΠ is received and converted through the “first” interface, and an analog image two signal is received, and the second digital image signal is received by the second interface through the second interface. In step _ output first-digit data, according to a control signal control data is transferred to the processing unit in step si r or the third digital image signal to a scaler. - The digital image signal or the recorder is based on the resolution of the received output-digital image _ 1-bit image δίι into the lamp zooming action, and the punch. Therefore, the line controller and at least one line of the slow = medium 'clock controller root degree, the number to the source drive the Cuiyuan wheel to send out a data transmission panel. In the step: the drive unit drives the image screen according to the data signal. In the S34G, the 'panel display corresponds to one of the resolutions mentioned above.> The Λ Λ system has been described in detail in the plane illusion 'face image signal processing method, its operating principle Τ 显 显 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 The disclosure of the above embodiments of the present invention will not be repeated here. , , and method ' combined with the function of the scaler and the simple image processing system 4 simple structure, will be multiple 13 201016002

The TW4133PA different interface image signals are adjusted to multiple digital image signals of the same clock, so that multiple interfaces can be integrated into a single package of chips, and different interface image signals can be processed, so that the manufacturing cost of the multi-interface image signal processing system is reduced. And more widely used. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. [Simple Description of the Drawing] Fig. 1 is a block diagram showing a conventional flat panel display. Figure 2A is a block diagram of a flat panel display in accordance with a preferred embodiment of the present invention. 2B is a detailed block diagram of a flat panel display in accordance with a preferred embodiment of the present invention. FIG. 3 is a flow chart showing a method for processing a multi-interface image signal according to a preferred embodiment of the present invention. [Description of main component symbols] 100: Flat panel display 112: First DVI interface 114: Second DVI interface 14 201016002

TW4133PA 122: first TMDS receiver 124: second TMDS receiver 130: clock controller 140: source drive unit 150: panel 200, 200': flat panel display 210: panel 220: source drive unit® 232: One interface 234: second interface 240: multi-interface video signal processing system 250: data input processing unit 252: analog digital converter 254: decoder 260: switching device 265 265: microprocessor 270: scaler 280: line buffer 290: Clock controller 15

Claims (1)

201016002 TW4133PA X. Patent application scope: 1. · A multi-interface video signal processing system applied to a flat-panel display T? The front panel display includes a panel and a source driving unit, and the surface display corresponds to a resolution image, and the source driving unit drives the panel 'the multi-interface image signal processing' includes: a stock input processing Units, including: The n U double-bit converter receives and decodes a second shirt image signal via a second interface via a first type of analogy H number (four) image signal; a gold 4·A decoder And a switching device coupled to the analog-to-digital converter and the solution=the ton-control signal controls the data input processing unit to output the two-digit image signal or the third digital image signal; The device is coupled to the data input processing unit and receives the first digital image signal or the third=汛 number rotated by the St: processing unit, wherein the scaler receives the received according to the resolution: = the signal output or the third digital image signal is zoomed to output a digital image output signal; the read line slow ^ temporary number (four) image round out _ the size corresponds to the resolution; and ^ shout - C Used to send out messages according to the digital image wheel "The data signal 2: move early 70' to make _, move the unit root: 2. As claimed in the patent scope 帛1, the multi-interface video signal office 16 201016002 TW4I33PA management system, Which analogy The image signal belongs to a D-sub image signal, and the first digital image signal belongs to a Transistor-Transistor Logic (TTL) image signal. 3. The multi-interface image as described in claim 1 a signal processing system, wherein the decoder is a Transition Minimized Differential Signal (TMDS) decoder, and the second digital image signal belongs to a digital video interface (Digital • VlSUal interface, Dv!) video signal or High Definition Multimedia Interface (HDMI) video signal 'The third digital image signal belongs to the -transistor-transistor logic image signal. 4. Multi-interface image signal as described in claim 凊 patent scope Wherein: the system, the switching device is a multiplexer for outputting the first digital image signal according to the control, the number of the control device, the first digital image signal to the scaler ® The multi-interface scene signal signal described in item 1 of the patent scope further includes a microprocessor for Firstly, the output is set to be wide: to switch the device, and the zoomer is controlled to zoom in on the received wide image or the third digital image signal to make the image corresponding to the (four) digital image round signal The facet is in accordance with the resolution. ^ 6. The multi-interface image signal processing system of claim 1, wherein the data signal is a reduced SWlng Dlfferential Signal (RSDS) or a low voltage. Differential signal 17 201016002 TW4133PA (Low Voltage Differential Signal, LVDS) The multi-interface image signal processing system according to item 1 of the remedy system, wherein the degree of hygiesis is greater than or equal to 256Gxl600. 8. The system described in the scope of the patent application is packaged in a single wafer. Port image signal processing unit 9. A multi-interface image signal processing in a data input processing unit command, via a first image signal as a first digital image signal, and via --:: receiving and decoding - second digital image The signal is - the third digit shadow: a unit apostrophe (four) m (four) round-in processing - scaler; the image 5 field or the third digital image signal to the downsizing unit according to the resolution of the signal or the third digit of the image Level 4®—Digital image bit image output (4) to the ordering zoom action, and round-to-number green, the size corresponds to the solver, where the signal ^Wei (four) image output signal output 1 signal drive ~ a panel; causing the source driving unit to display an image plane corresponding to the resolution according to the data panel. The multi-interface image signal area described in item 9 of the patent area is - the image-to-image signal is - _ image signal, and the _th 旒 is a transistor-transistor logic image signal. The method of processing a multi-interface image signal according to claim 9 wherein the second digital image signal is decoded into the third digital image signal by using a minimized shift differential signal decoder. The second digital image=signal belongs to a digital video interface image signal or a high definition multimedia interface image signal. The third digital image signal belongs to a transistor-transistor logic image signal. 12. The multi-interface image signal processing method of claim 9, wherein the image corresponding to the digital image output signal conforms to the resolution. The multi-interface image signal processing method as described in claim 9 wherein the data signal is a low swing differential signal or a low voltage differential signal. The method of processing a multi-interface image signal as described in claim 9 wherein the resolution is greater than or equal to 2560 x 1600.