CN115036307A - RC-LIGBT device integrating four MOSFETs - Google Patents

RC-LIGBT device integrating four MOSFETs Download PDF

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CN115036307A
CN115036307A CN202210506312.4A CN202210506312A CN115036307A CN 115036307 A CN115036307 A CN 115036307A CN 202210506312 A CN202210506312 A CN 202210506312A CN 115036307 A CN115036307 A CN 115036307A
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region
mos
grid
oxide layer
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陈伟中
魏子凯
林徐葳
秦海峰
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Chongqing University of Post and Telecommunications
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention relates to an RC-LIGBT device integrating four MOSFETs, belonging to the technical field of semiconductors. The device comprises a cathode P + region, a cathode N + region, a cathode P-well region, a drift region, an oxygen burying layer, a substrate, an anode P + region, an anode P-well region, an anode N-buffer region, a common MOS metal grid, a common MOS grid oxide layer, an anode N + region, an anode floating N + region, a channel MOS metal grid, an anode auxiliary MOS metal grid, an anode floating MOS metal grid, a channel MOS grid oxide layer, an anode auxiliary MOS grid oxide layer and an anode floating MOS grid oxide layer. The invention improves the reverse recovery performance and reverse conduction performance of the device.

Description

RC-LIGBT device integrating four MOSFETs
Technical Field
The invention belongs to the technical field of semiconductors, and relates to an RC-LIGBT device integrating four MOSFETs.
Background
LIGBT (Lateral Insulated Gate Bipolar Transistor) is a Bipolar semiconductor power device combining MOSFET and BJT, has the advantages of reduced on-state voltage, low driving power consumption, high working frequency, and the like, is widely applied to the fields of communication technology, new energy devices and various consumer electronics, and is a core device of an electronic power system. LIGBT is easily integrated on Si-base, and is commonly applied in SOI-based power intelligence systems.
Since the LIGBT does not have reverse conduction capability, in practical use, it is usually necessary to connect a reverse freewheeling diode beside the LIGBT for protection. Meanwhile, in order to improve the integration degree of the device and reduce the manufacturing cost, people begin to try to integrate a freewheeling diode with a protective effect into the LIGBT to form an RC-LIGBT (Reverse-Conducting laterally Insulated Gate Bipolar Transistor). The RC-LIGBT obviously simplifies the topological structure of the intelligent power circuit, reduces parasitic parameters and reduces the chip area, but has some non-negligible defects.
In the conventional RC-LIGBT, for example, SA-LIGBT, an Anode N + region and a P + region of the SA-LIGBT (Short-Anode-LIGBT) are shorted together by an Anode electrode, a parasitic diode is introduced into a device body, and the device has a reverse conduction capability. The anode N + region can directly extract electrons in the drift region in the turn-off process of the device, so that the switching speed of the device is improved, and the turn-off loss of the device is reduced. However, due to the introduction of the anode N + region, the injection efficiency of holes in the on state is reduced, so that the on voltage drop is increased, and more seriously, the Snapback voltage is reversed. Under the condition of smaller conduction current, electrons injected by the NMOS directly flow out of the anode N + region, the P +/N-buffer junction is not conducted, the device is in a unipolar mode, and the conduction resistance is higher; along with the gradual increase of the conduction current, the voltage drop generated when electrons flow through the N-buffer area below the P + area is gradually increased, when the voltage drop is larger than the built-in potential of the P +/N-buffer junction, the P + area starts to inject holes into the drift area to generate a conductivity modulation effect, the device enters a bipolar mode, the resistance is greatly reduced, and the Snapback phenomenon is caused. This can introduce electromagnetic oscillations into the circuitry, affecting the stability of the system.
In order to alleviate the Snapback phenomenon, researchers have proposed SSA-LIGBT (isolated-short-Anode LIGBT, split Anode insulated gate bipolar transistor). The structure separates a P + region from an N + region to a sufficient distance, equivalently introduces a large resistor between the P + region and the N + region, and the device can work in a bipolar mode under a small conduction current. Although the Snapback phenomenon is alleviated, a large amount of chip area is wasted.
Disclosure of Invention
In view of the above, the present invention provides an RC-LIGBT device integrating four MOSFETs, which controls the device to turn on and off by using a common MOSFET in the structure of a conventional LIGBT device; the reverse recovery performance of the device is greatly improved by adjusting the proportion of multi-electron holes and minority electron holes injected into the device at the reverse conduction time of the device by using the channel MOSFET; the anode auxiliary MOSFET is used for eliminating the Snapback voltage folding phenomenon in the traditional RC-LIGBT, and the reverse conducting performance of the device is further improved.
In order to achieve the purpose, the invention provides the following technical scheme:
an RC-LIGBT device integrating four MOSFETs comprises a cathode P + region 1, a cathode N + region 2, a cathode P-well region 3, a drift region 4, an oxygen burying layer 5, a substrate 6, an anode P + region 7, an anode P-well region 8, an anode N-buffer region 9, a common MOS metal grid 12 and a common MOS grid oxide layer 16, and further comprises an anode N + region 10, an anode floating N + region 11, a channel MOS metal grid 13, an anode auxiliary MOS metal grid 14, an anode floating MOS metal grid 15, a channel MOS grid oxide layer 17, an anode auxiliary MOS grid oxide layer 18 and an anode floating MOS grid oxide layer 19.
The reverse conducting region consists of an anode N-buffer region 9, an anode P-well region 8, an anode N + region 10, an anode auxiliary MOS metal grid 14, an anode auxiliary MOS grid oxide layer 18, an anode floating N + region 11, an anode floating MOS metal grid 15 and an anode floating MOS grid oxide layer 19; the anode N + region 10 is positioned right behind the anode P + region 7, and the anode N + region 10 and the anode P + region 7 are jointly wrapped on the upper right side by the anode P-well region 8; the anode P-well area 8 is completely wrapped on the upper right side by the anode N-buffer area 9; the anode floating N + region 11 is positioned at the rear upper part of the anode N-buffer region 9 and is positioned in the same horizontal direction with the anode P + region 7 and the anode N + region 10; the anode P + region 7 and the anode N + region 10 are in direct contact with the anode electrode together; the anode auxiliary MOS metal grid 14 and the anode auxiliary MOS grid oxide layer 18 are positioned right above the anode P-well region 8 in the interlayer of the anode N-buffer region 9-the anode P-well region 8-the anode N + region 10; the lower side of the anode auxiliary MOS grid oxide layer 18 is directly contacted with the upper side of the anode P-well region 8, and the upper side of the anode auxiliary MOS grid oxide layer 18 is directly contacted with the lower side of the anode auxiliary MOS metal grid 14; the electrode of the anode auxiliary MOS metal grid 14 is connected with the anode electrode; the anode floating MOS metal grid 15 is positioned right above the anode P-well region 8, the anode N-buffer region 9 and the anode floating N + region 11 in an interlayer of the anode N + region 10, the anode P-well region 8, the anode N-buffer region 9 and the anode floating N + region 11; the lower side of the anode floating MOS metal gate oxide layer 19 is directly contacted with the upper sides of the anode P-well region 8 and the anode N-buffer region 9, and the upper side of the anode floating MOS metal gate oxide layer 19 is directly contacted with the left lower side part of the anode floating MOS metal gate 15; the anode floating MOS metal grid 15 is directly contacted with the anode floating MOS grid oxide layer 19 and the anode floating N + region 11;
the channel diode region consists of a cathode N + region 2, a cathode P-well region 3, a drift region 4, a channel MOS metal grid 13 and a channel MOS grid oxide layer 17; the cathode N + region 2 is positioned at the right side of the cathode P + region 1 and is completely wrapped by the cathode P-well region 3; the drift region 4 is positioned at the lower side and the right side of the cathode P-well region 3; the channel MOS metal grid 13 is positioned right above the cathode P-well region 3 in the interlayer of the cathode N + region 2-the cathode P-well region 3-the drift region 4; the lower side of the channel MOS gate oxide layer 17 is directly contacted with the upper side of the cathode P-well region 3 and the left part of the upper side of the drift region 4, and the upper side of the channel MOS gate oxide layer 17 is directly contacted with the lower side of the channel MOS metal gate 13; the electrode of the channel MOS metal grid 13 is connected with the cathode electrode;
the bottom of the device consists of a buried oxide layer 5 and a substrate 6; the buried oxide layer 5 is located on the lower side of the drift region 4 and on the upper side of the substrate 6.
Further, the source electrode of the common MOSFET is a cathode N + region 2, the drain electrode is an (N-drift) drift region 4, the grid electrode is a common MOS metal grid electrode 12, and the grid oxide layer is a common MOS grid oxide layer 16;
the source of the channel MOSFET is an (N-drift) drift region 4, the drain is a cathode N + region 2, the grid is a channel MOS metal grid 13, and the grid oxide layer is a channel MOS grid oxide layer 17;
the source electrode of the anode auxiliary MOSFET is an anode N-buffer area 9, the drain electrode is an anode N +10, the grid electrode is an anode auxiliary MOS metal grid electrode 14, and the grid oxide layer is an anode auxiliary MOS grid oxide layer 18;
the source electrode of the anode floating MOSFET is an anode N + region 10, the drain electrode is an anode floating N + region 11, the grid electrode is an anode floating MOS metal grid electrode 15, and the grid oxide layer is an anode floating MOS grid oxide layer 19.
The structure and function of the four MOSFETs are shown in table 1 below:
TABLE 1 Structure and function of four MOSFETs
Figure BDA0003636304960000031
Further, a common MOSFET is used to control the injection of cathode electrons; the channel MOSFET is used for being started before the internal parasitic diode when being conducted reversely; the anode-assist MOSFET is used to ensure that the device provides an extra channel for electrons in the bipolar mode.
Further, a common MOSFET is used to control the on and off of the device; the channel MOSFET is used for adjusting the proportion of multi-electron and minority electron holes injected into the device at the reverse conduction moment of the device; the anode auxiliary MOSFET is used for eliminating the Snapback voltage folding phenomenon in the traditional RC-LIGBT and further improving the reverse conducting performance of the device.
Further, the thickness of the trench MOS gate oxide layer 17, the anode auxiliary MOS gate oxide layer 18, or the anode floating MOS gate oxide layer 19 may be adjusted as desired.
Further, the material of the anode floating MOS metal gate 15 includes doped polysilicon or aluminum.
The invention has the beneficial effects that: on the basis of the traditional LIGBT device, a reverse conducting region is introduced into an anode, and a channel diode region is introduced into a cathode. Under the condition that the device works in the forward direction conduction and the anode voltage is low, electrons in the blocking drift region of the anode P-well layer cannot directly flow away from the anode N + region which is in short circuit with the anode P + region. Along with the gradual increase of the anode voltage, the auxiliary gate at the anode is opened, electrons can flow away through the anode N + region and can also flow away through the anode P + region, and at the moment, the device is in a bipolar working mode, so that the Snapback voltage folding phenomenon is eliminated. When the device is turned off, the anode auxiliary grid can also assist in extracting electrons in the drift region, and the turn-off loss of the device is reduced. Under the condition that the device works in reverse conduction, the trench diode positioned at the cathode can be started before a PN junction formed by the cathode P + and the drift region N-drift is conducted, so that the quantity of injected minority carrier holes during reverse conduction is reduced, and the reverse recovery performance of the device is greatly improved. Under the condition that the device works in reverse conduction, the floating gate positioned in the anode reverse conduction area is automatically started by utilizing the voltage applied to a reverse bias PN junction formed by the anode N-buffer and the anode P-well, so that the reverse conduction performance is improved.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic structural diagram of a new-structure RC-LIGBT device in example 1 of the present invention;
FIG. 2 is a cross-sectional view of three different cross-sections a, b, c of the device of FIG. 1;
FIG. 3 is an equivalent circuit diagram of FIG. 1;
fig. 4 (a) is a schematic structural diagram of a conventional LIGBT device, and (b) is a schematic structural diagram of a conventional PIN diode;
FIG. 5 is a diagram showing potential distributions of the LIGBT in avalanche breakdown state according to embodiment 1 of the present invention;
FIG. 6 shows the drift region length L of the LIGBT in the embodiment 1 of the present invention and the conventional LIGBT D Graph comparing blocking characteristics at 18 μm;
FIG. 7 is a graph comparing the latch-up of the conventional LIGBT in the forward turn-on condition in the embodiment 1 of the present invention;
FIG. 8 is a graph comparing forward conduction characteristics of example 1 of the present invention and a conventional LIGBT, and a graph comparing electron concentrations in the vicinity of each gate in example 1;
FIG. 9 is a reverse conducting characteristic diagram of example 1 of the present invention, and an electron concentration comparison diagram in the vicinity of each gate in example 1;
FIG. 10 is a graph of the turn-off characteristics of the inductive load test circuit of example 1 and the conventional LIGBT under the same turn-on voltage drop, and the electron concentration in the vicinity of each gate in example 1;
fig. 11 is a comparison graph of reverse recovery test circuits and reverse recovery performance characteristics of example 1 of the present invention and a conventional PIN diode, and an electron concentration in the vicinity of each gate in example 1;
FIG. 12 is a schematic diagram of the main process flow of the new RC-LIGBT device provided by the present invention;
reference numerals: the MOS transistor comprises a 1-cathode P + region, a 2-cathode N + region, a 3-cathode P-well region, a 4- (N-drift) drift region, a 5-buried oxide layer, a 6-substrate, a 7-anode P + region, an 8-anode P-well region, a 9-anode N-buffer region, a 10-anode N + region, an 11-anode floating N + region, a 12-common MOS metal grid, a 13-channel MOS metal grid, a 14-anode auxiliary MOS metal grid, a 15-anode floating MOS metal grid, a 16-common MOS grid oxide layer, a 17-channel MOS grid oxide layer, an 18-anode auxiliary MOS grid oxide layer and a 19-anode floating MOS grid oxide layer.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; for a better explanation of the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.
As shown in fig. 4, the conventional LIGBT device mainly comprises a cathode P + region 1, a cathode N + region 2, a cathode P-well region 3, a drift region 4, an anode P + region 7, an anode P-well region 8, an anode N-buffer region 9, a common MOS metal gate 12, and a common MOS gate oxide layer 16. From left to right, a cathode P + region 1, a cathode N + region 2, a common MOS metal grid 12, a common MOS grid oxide layer 16, a cathode P-well region 3, an (N-drift) drift region 4, an anode P + region 7, an anode P-well region 8 and an anode N-buffer region 9 are respectively arranged. The right side of the cathode P + region 1 is adjacent to the cathode N + region 2, and the cathode P + region 1 and the cathode N + region 2 are connected with a cathode electrode together. The cathode P-well region 3 is positioned at the lower sides of the cathode P + region 1 and the cathode N + region 2, and completely wraps the cathode P + region 1 and the cathode N + region 2. The (N-drift) drift region 4 is adjacent to the cathode P-well region 3 and the anode N-buffer region 9. The anode P +7, the anode P-well area 8 and the anode N-buffer area 9 form a sandwich-like structure. The anode P + region 7 is completely surrounded by the anode P-well region 8. The anode P-well region 8 is completely surrounded by the anode N-buffer region 9. The anode P + region 7 is in contact with the anode electrode. The common MOS metal grid 12 is positioned right above the cathode P-well region 3 in the interlayer of the cathode N + region 2-the cathode P-well region 3-the N-drift region 4, and the common MOS grid oxide layer 16 is directly contacted with the cathode P-well region 3.
Example 1:
as shown in fig. 1, the conventional LIGBT device is improved, and this embodiment provides a new RC-LIGBT device integrating four MOSFETs, which mainly includes a cathode P + region 1, a cathode N + region 2, a cathode P-well region 3, (N-drift) drift region 4, a buried oxide layer 5, a substrate 6, an anode P + region 7, an anode P-well region 8, an anode N-buffer region 9, an anode N + region 10, an anode floating N + region 11, a common MOS metal gate 12, a channel MOS metal gate 13, an anode auxiliary MOS metal gate 14, an anode floating MOS metal gate 15, a common MOS gate oxide layer 16, a channel MOS gate oxide layer 17, an anode auxiliary MOS gate oxide layer 18, and an anode floating MOS gate oxide layer 19.
The reverse conducting region consists of an anode N-buffer region 9, an anode P-well region 8, an anode N + region 10, an anode auxiliary MOS metal grid 14, an anode auxiliary MOS grid oxide layer 18, an anode floating N + region 11, an anode floating MOS metal grid 15 and an anode floating MOS grid oxide layer 19. From left to right are an anode N-buffer region 9, an anode P-well region 8, an anode N + region 10, an anode auxiliary MOS metal gate 14, an anode auxiliary MOS gate oxide layer 18, an anode floating N + region 11, an anode floating MOS metal gate 15, and an anode floating MOS gate oxide layer 19, respectively. The anode N + region 10 is positioned right behind the anode P + region 7, and the anode N + region 10 and the anode P + region 7 are jointly wrapped by the anode P-well region 8. The anode P-well region 8 is completely surrounded by the anode N-buffer region 9. The anode floating N + region 11 is positioned at the rear upper part in the anode N-buffer region 9 and is positioned in the same horizontal direction with the anode P + region 7 and the anode N + region 10. The anode P + region 7 and the anode N + region 10 are in direct contact with the anode electrode in common. The anode auxiliary MOS metal grid 14 is positioned right above the anode P-well region 8 in the interlayer of the anode N-buffer region 9-the anode P-well region 8-the anode N + region 10, and the anode auxiliary MOS grid oxide layer 18 is in direct contact with the anode P-well region 8. The electrode of the anode auxiliary MOS metal gate 14 is connected to the anode electrode. The anode floating MOS metal grid 15 is positioned right above the anode P-well region 8, the anode N-buffer region 9 and the anode floating N + region 11 in the interlayer of the anode N + region 10, the anode P-well region 8, the anode N-buffer region 9 and the anode floating N + region 11. The anode floating MOS metal gate oxide layer 19 is directly contacted with the anode P-well region 8 and the anode N-buffer region 9. The anode floating MOS metal gate 15 is in direct contact with the anode floating MOS gate oxide 19 and the anode floating N + region 11.
The channel diode region mainly comprises a cathode N + region 2, a cathode P-well region 3, an (N-drift) drift region 4, a channel MOS metal grid 13 and a channel MOS grid oxide layer 17. From left to right are a cathode N + region 2, a cathode P-well region 3, an (N-drift) drift region 4, a channel MOS metal gate 13, and a channel MOS gate oxide layer 17. Cathode N + region 2 is located to the right of cathode P + region 1 and is completely surrounded by cathode P-well region 3. The (N-drift) drift region 4 is located below and to the right of the cathode P-well region 3. The channel MOS metal grid 13 is positioned right above the cathode P-well region 3 in the interlayer of the cathode N + region 2-the cathode P-well region 3- (N-drift) drift region 4. The tunnel MOS gate oxide 17 is in direct contact with the cathode P-well region 3. An electrode of the trench MOS metal gate 13 is connected to the cathode electrode.
The bottom of the device consists of a buried oxide layer 5 and a substrate 6; the buried oxide layer 5 is located on the lower side of the (N-drift) drift region 4 and on the upper side of the substrate 6. The substrate 6 is located under the buried oxide layer 5.
The (N-drift) drift region 4 had a length (Y-axis direction) of 18 μm, a width (Z-axis direction) of 5 μm, and a thickness (X-axis direction) of 4 μm, and the doping concentration of the region was 2X 10 15 cm -3 . The cathode P + region 1 has a length of 1 μm, a width of 5 μm, a thickness of 1 μm, and a doping concentration of 1X 10 19 cm -3 . The cathode N + region 2 has a length of 1 μm, a width of 5 μm, a thickness of 1 μm, and a doping concentration of 1X 10 19 cm -3 . The cathode P-well region 3 has a length of 3 μm, a width of 5 μm, a thickness of 2 μm, and a doping concentration of 1X 10 17 cm -3 . The anode P + region 7 has a length of 1 μm, a width of 1 μm, a height of 1 μm, and a doping concentration of 1X 10 19 cm -3 . The anode P-well region 8 has a length of 2 μm, a width of 3 μm, a thickness of 2 μm and a doping concentration of 1X 10 17 cm -3 . The length of the anode N-buffer area 9 is3 μm, 5 μm in width, 3 μm in thickness, and 8X 10 in doping concentration 16 cm -3 . The anode N + region 10 has a length of 1 μm, a width of 1 μm, a thickness of 1 μm, and a doping concentration of 1X 10 19 cm -3 . The length of the anode floating N + region 11 is 1 μm, the width is 1 μm, the thickness is 1 μm, and the doping concentration is 1 × 10 19 cm -3 . The normal MOS metal gate 12 has a length of 1 μm, a width of 3 μm, and a thickness of 0.1 μm. The common MOS gate oxide layer 16 has a length of 1 μm, a width of 3 μm, and a thickness of 0.1 μm. The channel MOS metal gate 13 has a length of 1 μm, a width of 2 μm, and a thickness of 0.1 μm. The tunnel MOS gate oxide layer 17 has a length of 1 μm, a width of 2 μm, and a thickness of 0.01 μm. The anode auxiliary MOS metal gate 14 has a length of 1 μm, a width of 1 μm, and a thickness of 0.1 μm. The anode auxiliary MOS gate oxide layer 18 has a length of 1 μm, a width of 1 μm, and a thickness of 0.1 μm. The anode floating MOS metal gate 15 has a length of 1 μm, a width of 3 μm, and a thickness of 0.01 μm. The anode floating MOS gate oxide layer 19 has a length of 1 μm, a width of 3 μm, and a thickness of 0.01 μm. The buried oxide layer 5 has a length of 24 μm, a width of 5 μm and a thickness of 3 μm. The substrate 6 had a length of 24 μm, a width of 5 μm, a thickness of 1 μm and a doping concentration of 1X 10 16 cm -3 。
Under the condition that the device works in forward conduction and the anode voltage is lower, electrons in the drift region cannot be directly pumped away by the anode N + region in short circuit with the anode P + region due to the blocking of the anode P-well layer. Along with the gradual increase of the anode voltage, the auxiliary MOS gate at the anode is opened, electrons can flow away through the anode N + region and can also flow away through the anode P + region, and at the moment, the device is in a bipolar working mode, so that the Snapback voltage folding phenomenon is eliminated. When the device is turned off, the anode auxiliary grid can also assist in extracting electrons in the drift region, and the turn-off loss of the device is reduced. Under the condition that the device works in reverse conduction, the trench diode positioned at the cathode can be started before a PN junction formed by the cathode P + and the (N-drift) drift region is conducted, so that the quantity of injected minority carrier holes during reverse conduction is reduced, and the reverse recovery performance of the device is greatly improved. Under the condition that the device works in reverse conduction, the floating gate positioned in the anode reverse conduction region realizes automatic opening by utilizing the voltage applied to a reverse bias PN junction formed by the anode N-buffer and the anode P-well, thereby improving the reverse conduction performance.
The LIGBT device of example 1 as proposed in the structure shown in fig. 1 to 2 was subjected to performance simulation analysis, the mechanism thereof was analyzed, and electrical simulation was performed using sentaturus simulation software. In the simulation process, the device in the embodiment 1 and the conventional LIGBT have the same simulation parameters, wherein the thickness of the (N-drift) drift region is 4 μm, the service life of the carrier is 10 μ s, and the ambient temperature is 300K.
Fig. 3 is an equivalent circuit diagram of the RC-LIGBT device of embodiment 1, in which the LIGBT region is equivalent to an NMOS controlled PNP transistor. The reverse conducting area is equivalent to two NMOS tubes positioned at the anode, wherein the anode auxiliary grid is equivalent to the NMOS tube with the drain electrode and the grid electrode which are in short circuit together, and the anode floating electrode is equivalent to the NMOS tube with the source electrode and the grid electrode which are in short circuit together when in forward conducting. The channel diode area is equivalent to a PN diode which is positioned at the cathode and is connected with an NMOS tube with a grid electrode and a source electrode which are in short circuit. At the moment of turn-off, the two NMOS tubes positioned at the anode can be started to assist in extracting electrons positioned in the (N-drift) drift region, the turn-off speed of the device is improved, and the turn-off loss of the device is reduced. At the time of reverse recovery, because the threshold voltage of the NMOS positioned at the cathode is lower than the conduction voltage of the PN diode, the NMOS is conducted in advance of the PN diode, minority holes injected into the device during reverse conduction are reduced, and the reverse recovery characteristic of the device is greatly improved.
Fig. 5 is a graph comparing the blocking characteristics of example 1 and the conventional LIGBT at a drift region length (Y-axis direction) of 18 μm. Example 1 concentration in drift region was 2X 10 15 cm -3 The breakdown voltage at time is 276V; the concentration of conventional LIGBT in drift region is 2 × 10 15 cm -3 The breakdown voltage at this time was 273V, and both were in the same withstand voltage class.
FIG. 6 shows the drift region length (Y-axis direction) of 18 μm and the concentration of 2X 10 in example 1 and the conventional LIGBT 15 cm -3 The avalanche breakdown characteristic curves are compared.
FIG. 7 shows the drift region length (Y-axis direction) of 18 μm and the concentration of 2X 10 in example 1 and the conventional LIGBT 15 cm -3 Comparing the lower latch-up characteristic curve with the figure, since the area of the ordinary MOS grid of the embodiment 1 is smaller than that of the ordinary MOS grid of the traditional LIGBT, the saturation current of the embodiment 1 is far smaller than that of the traditional LIGBT, and the latch-up resistance performance of the embodiment 1 is far better than that of the traditional LIGBT.
Fig. 8(a) in fig. 8 is a graph comparing the forward conduction characteristic curves of the example 1 and the conventional LIGBT. When conducting in the forward direction, the cathode is grounded, and a positive voltage of 10V is applied to the gate. In the forward conduction stage, the conduction voltage drop of the traditional LIGBT is smaller and is 0.97V; the conduction voltage drop of example 1 was 1.35V. In the forward conduction stage, the efficiency of hole emission is reduced due to the smaller area of the cathode control gate in the drift region of example 1 compared with the conventional LIGBT and the smaller area of the anode P + region, so the conduction voltage drop of the device of example 1 is slightly higher than that of the conventional LIGBT. Fig. 8(b) is an electron concentration distribution diagram near a normal MOS gate, which controls the injection of cathode electrons at the time of forward conduction, and it can be seen that an inversion layer appears in the MOS channel, and a large amount of electrons are injected from the cathode into the drift region. Fig. 8(c) is an electron concentration distribution diagram in the vicinity of the trench MOS gate, which is in an off state at the time of forward conduction and in which no inversion layer is present in the channel. Fig. 8(d) is an electron concentration distribution diagram near the anode floating MOS gate, where the anode floating MOS gate is in an on state at the time of forward conduction, and an inversion layer appears in a channel to provide an extra channel for electrons in the drift region, and a large amount of electrons flow into the anode through the channel. Fig. 8(e) is an electron concentration distribution diagram near the anode-assisted MOS gate, which is in an off state at the time of forward conduction, and a channel appears with a significant inversion layer due to a small conduction voltage, but a large amount of electrons are attracted to gather at the lower side.
Fig. 9(a) is a reverse conduction characteristic curve of example 1. When conducting in reverse direction, the anode is grounded and the cathode applies a gradually increasing positive voltage. The device can be turned on in the reverse direction thanks to the introduction of the channel diode region and the reverse conduction region. The reverse conduction voltage drop of the example 1 device was 1.29V. Fig. 9(b) is an electron concentration distribution diagram in the vicinity of the normal MOS gate, which is turned off at the time of reverse conduction, and no inversion layer appears in the channel. Fig. 9(c) is a diagram showing an electron concentration distribution in the vicinity of the trench MOS gate, in which the trench MOS gate is turned on at the time of reverse conduction, an inversion layer is formed in the channel, and a large amount of electrons are injected from the cathode into the drift region. Fig. 9(d) is an electron concentration distribution diagram near the anode floating MOS gate, where the anode floating MOS gate is in an on state at the time of forward conduction, an inversion layer appears in a channel to provide a channel for electrons in a drift region, and a large amount of electrons flow into the anode through the channel, so that the device obtains a reverse conduction capability. Fig. 9(e) is an electron concentration distribution diagram near the anode auxiliary MOS gate, where the anode auxiliary MOS gate is in an off state at the time of reverse conduction, no inversion layer is present in the channel, and the electron current under the channel is very small.
Fig. 10(a) and fig. 10(b) in fig. 10 are the turn-off characteristic curves of the topology of the test circuit, in which the load is an inductive load, and the conventional LIGBT under the same turn-on voltage drop as in example 1. The off time refers to the time it takes for the collector current to drop from 90% to 10%. Compared with the traditional LIGBT device, the device of the embodiment 1 has two more NMOS electron extraction channels. At the turn-off moment, electrons can directly flow out through the two NMOS positioned at the anode, so that the number of emitted holes due to the flow-out of the electrons through the anode P + is reduced, and the turn-off loss of embodiment 1 is greatly reduced. Fig. 10(c) is an electron concentration distribution diagram near the normal MOS gate, which is turned off at the device turn-off time. Fig. 10(d) is an electron concentration distribution diagram in the vicinity of the trench MOS gate, which is in an off state at the time of device turn-off. Fig. 10(e) is an electron concentration distribution diagram near the anode floating MOS gate, where the anode floating MOS gate is in an on state at the time of device turn-off, an inversion layer appears in the channel to provide an extra extraction channel for electrons in the drift region, and a small amount of electrons are accumulated below the channel at the end of turn-off. Fig. 10(f) is an electron concentration distribution diagram in the vicinity of the anode auxiliary MOS gate, in which the anode auxiliary MOS gate is in an on state at the time of device turn-off, and since the anode voltage is sufficiently large at the end of turn-off, the voltage applied to the anode auxiliary MOS gate is also sufficiently large, the channel is completely inverted, and electrons in the vicinity of the channel are completely extracted.
Fig. 11(a) and 11(b) in fig. 11 are respectively a topology structure diagram of a test circuit and reverse recovery characteristic curves of embodiment 1 and a conventional PIN diode under the same conduction current. Compared with the traditional LIGBT device, the channel diode positioned at the cathode of the device in the embodiment 1 is started to inject electrons earlier than the PN junction diode, so that the quantity of minority holes injected into a drift region is reduced. At the time of reverse recovery, the number of holes required to be extracted from the device is greatly reduced, thereby greatly improving the reverse recovery characteristics of the device of example 1. Fig. 11(c) is an electron concentration distribution diagram in the vicinity of the normal MOS gate, which is in an off state at the time of reverse recovery. Fig. 11(d) is an electron concentration distribution diagram in the vicinity of the tunnel MOS gate, which is in an off state at the time of reverse recovery. Fig. 11(e) is a graph showing the electron concentration distribution near the anode floating MOS gate, where the anode floating MOS gate is turned on at the time of reverse recovery, an inversion layer appears in the channel to provide an extra extraction channel for electrons in the drift region, and a small amount of electrons still accumulate below the channel at the end of reverse recovery. Fig. 11(f) is a graph showing the electron concentration distribution near the anode-assisted MOS gate, which is turned off most of the time at the time of the reverse recovery, and is turned on briefly to extract a part of the electrons in a short time under the action of the external inductor.
The LIGBT device integrating four MOSFETs according to the present invention is illustrated in fig. 1, and the main process flow thereof is shown in fig. 12. The main process comprises the following steps: the ordinary LIGBT region, the reverse conducting region and the trench diode region are formed by the processes of ion implantation, diffusion, etching, oxidation, deposition, polycrystalline filling, annealing and the like. And finally, depositing metal electrodes to form a source electrode, a grid electrode and a drain electrode.
Finally, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (7)

1. An RC-LIGBT device integrating four MOSFETs comprises a cathode P + region (1), a cathode N + region (2), a cathode P-well region (3), a drift region (4), an oxygen burying layer (5), a substrate (6), an anode P + region (7), an anode P-well region (8), an anode N-buffer region (9), a common MOS metal grid (12) and a common MOS grid oxide layer (16), and is characterized by further comprising an anode N + region (10), an anode floating N + region (11), a channel MOS metal grid (13), an anode auxiliary MOS metal grid (14), an anode floating MOS metal grid (15), a channel MOS grid oxide layer (17), an anode auxiliary MOS grid oxide layer (18) and an anode floating MOS grid oxide layer (19);
the reverse conducting region consists of an anode N-buffer region (9), an anode P-well region (8), an anode N + region (10), an anode auxiliary MOS metal grid (14), an anode auxiliary MOS grid oxide layer (18), an anode floating N + region (11), an anode floating MOS metal grid (15) and an anode floating MOS grid oxide layer (19); the anode N + region (10) is positioned right behind the anode P + region (7), and the anode N + region (10) and the anode P + region (7) are jointly wrapped on the upper right side by the anode P-well region (8); the anode P-well area (8) is completely wrapped on the upper right side by the anode N-buffer area (9); the anode floating N + region (11) is positioned at the rear upper part of the anode N-buffer region (9) and is positioned in the same horizontal direction with the anode P + region (7) and the anode N + region (10); the anode auxiliary MOS metal grid (14) and the anode auxiliary MOS grid oxide layer (18) are positioned right above the anode P-well region (8) in the interlayer of the anode N-buffer region (9) -the anode P-well region (8) -the anode N + region (10); the lower side of the anode auxiliary MOS grid oxide layer (18) is in direct contact with the upper side of the anode P-well region (8), and the upper side of the anode auxiliary MOS grid oxide layer (18) is in direct contact with the lower side of the anode auxiliary MOS metal grid (14); the anode floating MOS metal grid (15) is positioned right above the anode P-well region (8), the anode N-buffer region (9) and the anode floating N + region (11) in an interlayer of the anode N + region (10), the anode P-well region (8), the anode N-buffer region (9) and the anode floating N + region (11); the lower side of the anode floating MOS metal gate oxide layer (19) is directly contacted with the upper sides of the anode P-well region (8) and the anode N-buffer region (9), and the upper side of the anode floating MOS metal gate oxide layer (19) is directly contacted with the left lower side part of the anode floating MOS metal gate (15); the anode floating MOS metal grid (15) is directly contacted with an anode floating MOS grid oxide layer (19) and an anode floating N + region (11);
the channel diode region consists of a cathode N + region (2), a cathode P-well region (3), a drift region (4), a channel MOS metal grid (13) and a channel MOS grid oxide layer (17); the cathode N + region (2) is positioned on the right side of the cathode P + region (1) and is completely wrapped by the cathode P-well region (3); the drift region (4) is positioned at the lower side and the right side of the cathode P-well region (3); the channel MOS metal gate (13) is positioned right above the cathode P-well region (3) in the interlayer of the cathode N + region (2), the cathode P-well region (3) and the drift region (4); the lower side of the channel MOS gate oxide layer (17) is in direct contact with the upper side of the cathode P-well region (3) and the left part of the upper side of the drift region (4), and the upper side of the channel MOS gate oxide layer (17) is in direct contact with the lower side of the channel MOS metal gate (13);
the bottom of the device consists of a buried oxide layer (5) and a substrate (6); the buried oxide layer (5) is positioned at the lower side of the drift region (4) and at the same time positioned at the upper side of the substrate (6).
2. The RC-LIGBT device integrating four MOSFETs according to claim 1, characterized in that the anode P + region (7) and the anode N + region (10) are in common direct contact with the anode electrode; the electrode of the anode auxiliary MOS metal grid (14) is connected with the anode electrode; and the electrode of the channel MOS metal grid (13) is connected with the cathode electrode.
3. An RC-LIGBT device integrating four MOSFETs according to claim 1 or 2, characterised in that the source of a normal MOSFET is a cathode N + region (2), the drain is a drift region (4), the gate is a normal MOS metal gate (12), the gate oxide is a normal MOS gate oxide (16);
the source electrode of the channel MOSFET is a drift region (4), the drain electrode is a cathode N + region (2), the grid electrode is a channel MOS metal grid electrode (13), and the grid oxide layer is a channel MOS grid oxide layer (17);
the source electrode of the anode auxiliary MOSFET is an anode N-buffer area (9), the drain electrode is an anode N + (10), the grid electrode is an anode auxiliary MOS metal grid electrode (14), and the grid oxide layer is an anode auxiliary MOS grid oxide layer (18);
the source electrode of the anode floating MOSFET is an anode N + region (10), the drain electrode of the anode floating MOSFET is an anode floating N + region (11), the grid electrode of the anode floating MOS metal grid electrode (15) is, and the grid oxide layer of the anode floating MOS grid electrode is an anode floating MOS grid oxide layer (19).
4. The RC-LIGBT device integrating four MOSFETs according to claim 3, wherein said normal MOSFET is configured to control injection of cathode electrons; the channel MOSFET is used for being started before an internal parasitic diode when being conducted reversely; the anode auxiliary MOSFET is used for ensuring that the device provides an additional channel for electrons on the premise of a bipolar mode.
5. The RC-LIGBT device integrating four MOSFETs according to claim 3, wherein the normal MOSFET is used for controlling the turning on and off of the device; the channel MOSFET is used for adjusting the proportion of multi-electron and minority electron holes injected into the device at the reverse conduction moment of the device; the anode auxiliary MOSFET is used for eliminating the Snapback voltage folding phenomenon in the traditional RC-LIGBT.
6. The RC-LIGBT device integrating four MOSFETs according to claim 1, characterized in that the thickness of the trench MOS gate oxide (17), the anode-assisted MOS gate oxide (18) or the anode floating MOS gate oxide (19) is adjusted as required.
7. The RC-LIGBT device integrating four MOSFETs according to claim 1, characterized in that the material of the anode floating MOS metal gate (15) comprises doped polysilicon or aluminum.
CN202210506312.4A 2022-05-10 2022-05-10 RC-LIGBT device integrating four MOSFETs Pending CN115036307A (en)

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