CN115020396B - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
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- CN115020396B CN115020396B CN202210587480.0A CN202210587480A CN115020396B CN 115020396 B CN115020396 B CN 115020396B CN 202210587480 A CN202210587480 A CN 202210587480A CN 115020396 B CN115020396 B CN 115020396B
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- chip
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- solder paste
- packaging substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
Abstract
The invention discloses a chip packaging structure and a packaging method, wherein the surface of a packaging substrate of the chip packaging structure is provided with a raised supporting part, the supporting part is arranged corresponding to a chip bump pad, solder paste is printed at the position corresponding to the supporting part to generate a solder paste part, a chip is welded on the packaging substrate through the solder paste part, and an isolating film covers the surfaces of the packaging substrate and the chip, so that the chip and the packaging substrate form a cavity; the invention discloses a packaging method, which comprises the following steps: pressing a supporting plate on the packaging substrate, manufacturing a supporting part protruding the packaging substrate at a corresponding position of the supporting plate, printing solder paste at the supporting part, and welding a chip on the packaging substrate through the solder paste part, wherein the chip is a flip chip, and pressing the chip and the packaging substrate by adopting an isolating film, so that a cavity is formed between the chip and the packaging substrate; the chip packaging structure and the packaging method provided by the invention have the advantages that the process operation is simple, the packaging cost is greatly reduced, the chip manufacturing process is simplified, and the reliability is improved.
Description
Technical Field
The invention relates to the technical field of radio frequency system module packaging, in particular to a chip packaging structure and a packaging method.
Background
With the development of 5G and market demand, the rf front-end chip is also highly integrated. Because of the special structural function of the filter, the piezoelectric property of the piezoelectric material is utilized, and the surface of the interdigital transducer must be ensured not to contact other substances in the packaging process, namely the surface of the chip must be ensured to be a cavity. At present, the implementation method of the filter cavity has two forms, namely, the cavity is formed by adopting a mode of adding a coating film on a long copper column or a tin-plated ball on the surface of a wafer in the manufacturing process of the discrete device, and the scheme is mainly used for packaging the discrete device, and has mature process, lower cost and better reliability. However, the selection of a filter using such a package structure in a module packaging process has significant process challenges and package reliability problems in the packaging process. The other mode is that cavities are formed by coating films in the wafer manufacturing process, namely WLP (Wafer Level Package) packaging mode, the WLP filter packaging structure has higher cost, but has better performance and good reliability, and can be directly applied to the module packaging with the filter system.
The implementation scheme of the existing filter discrete device or module specifically comprises the following steps:
1) And (3) a long copper column is arranged on the surface of the filter wafer, the copper column is dipped with tin, then the copper column is reversely buckled on the packaging substrate in an ultrasonic flip-chip bonding mode, and a cavity is formed in a film coating mode, so that the filter packaging process is completed. Is suitable for packaging forms of discrete devices.
2) The method for forming tin balls or tin ball implantation on the surface of the filter wafer adopts a flip-chip bonding and film coating process to form a cavity to complete the filter packaging, usually CSP (Chip Scale Package) packaging process, has higher cost for tin printing and ball implantation process, has poor ball flatness after tin printing or tin ball loading, affects later welding, and is not suitable for modularized packaging with a filter.
3) WLP (Wafer Level Package) the cavity structure is formed in the filter wafer in a film coating mode, and can be directly used for the radio frequency modularized packaging product with the filter.
Therefore, the existing system module packaging structure with the filter can only select the filter with the cavity structure of the WLP (Wafer Level Package) wafer when the filter packaging structure is selected, and other related devices, such as a switch chip, a low-noise chip, a power amplifier chip and the like, are integrated in one module system to form a modularized packaging structure, so that the performance is improved and the size is reduced.
However, WLP filters are costly in construction and are not conducive to modular packaging of the system. For the filter which does not have a cavity structure on the wafer, the bump is required to be manufactured on the surface of the wafer, and then the bump is connected with the substrate, so that the filter which needs to be covered with a film to form the cavity is not suitable for systematic module packaging and has the problem of poor reliability, wherein the method for manufacturing the bump comprises, but is not limited to, a long copper column, the copper column is not dipped with tin to form the bump, the long copper column is dipped with tin to form the bump, or the bump is formed after tin ball planting.
In addition, for the module package formed by multiple devices, the filter to be coated cannot avoid other related devices on the module in the film coating process, as shown in fig. 1, the package substrate can also be coated with devices except for the filter in the film coating process, for example, the package structure is a flip chip or other chips with wire bonding structures, and the Bump welding spots at the bottom of the chip after the flip chip is subjected to peritoneum can not realize bottom filling, so that the product has higher reliability risk.
For the filter with the wafer without the cavity structure, the filter chip and other flip chip film-coated chip bottom Bump welding spots are not under filling protection, so that the product has higher reliability risk.
1) Because the filter chip and other flip chip are covered with the film and then the bottom bump of the chip cannot be protected by the filler, the filter chip and other flip chip can be damaged by poor mechanical stress and thermal stress, and the product has higher reliability risk.
2) The filter chip has higher manufacturing cost of the lamp process, and is not beneficial to control of the product cost.
3) Or the bottom bump position of other flip chip needs to be subjected to dispensing treatment before being coated.
Disclosure of Invention
In order to overcome the defects of the technology, the invention provides a chip packaging structure and a packaging method, wherein a supporting layer is pressed on a packaging substrate so as to be provided with a supporting part protruding out of the packaging substrate, solder paste is filled in the supporting part and is higher than the supporting part, a filter chip and other flip chips are welded on the packaging substrate, the process operation is simple, and the packaging cost is greatly reduced.
The technical scheme adopted for overcoming the technical problems is as follows: the application provides a chip packaging structure, which comprises a packaging substrate, wherein a raised supporting part is arranged on the surface of the packaging substrate, the supporting part is arranged corresponding to a chip bump pad, solder paste is printed at a position corresponding to the supporting part to generate a solder paste part, and the height of the solder paste part is higher than that of the supporting part; the chip is welded on the packaging substrate through the solder paste part, wherein the chip is a flip chip and at least comprises a filter chip; and the packaging material at least comprises an isolating film, and the isolating film covers the surfaces of the packaging substrate and the chip, so that the chip and the packaging substrate form a cavity.
The manufacturing of the salient points and the implementation of the salient point tin dipping process on the filter chip are not needed, and in the actual packaging process, namely, the manufacturing of the copper column on the filter chip and the implementation of the copper column tin dipping process are not needed, so that the manufacturing cost of the filter chip is greatly reduced.
Further, the inner wall, the upper surface and the connection part with the substrate of the supporting part are all provided with metal plating layers.
Further, the supporting portion is a blind hole for connecting the chip and the surface of the packaging substrate.
And through the metal coating, the chip bump pad and the packaging substrate are electrically connected.
Further, the outer diameter of the supporting part is equal to the diameter of the chip bump pad.
The outer diameter of the supporting part is equal to the diameter of the bump pad of the chip, the bump is replaced by the supporting part, and specifically, the filter chip is supported by the supporting part instead of the copper column.
Further, the solder paste of the solder paste portion completely fills the support portion and is higher than the support portion.
The application provides a packaging method based on the chip packaging structure, which comprises the following implementation steps: s1, providing a packaging substrate, and pressing a supporting plate on the packaging substrate; s2, manufacturing a supporting part of the convex packaging substrate at a corresponding position of the supporting plate based on the position of the bump pad of the chip and the bump height; s3, printing solder paste on the supporting position in an SMT mode, and welding a solder paste part generated by printing the solder paste on the chip on the packaging substrate, wherein the chip is a flip chip and at least comprises a filter chip; s4, laminating the chip and the packaging substrate by using the isolating film, so that a cavity is formed between the chip and the packaging substrate.
Further, the step S2 specifically includes: s21, drilling holes in corresponding positions of the supporting plate based on positions of bump pads of the chip and bump heights so as to obtain supporting holes; s22, plating metal on the inner wall of the supporting hole; s23, cutting the support plate outside the support hole based on the thickness of the support plate, and stripping the support plate distributed outside the support hole after cutting, thereby obtaining a support part.
Further, the plastic packaging method further comprises the step of plastic packaging the outer side face of the isolation film.
The beneficial effects of the invention are as follows:
1. laminating a supporting layer on the substrate, wherein the process is simple and is equivalent to a process for directly manufacturing a multi-layer substrate;
2. the solder paste is filled in the supporting part from the position of the supporting layer corresponding to the bump pad to the supporting part, so that the chip can be conveniently welded
3. The manufacturing of the convex points and the dipping of the convex points in the tin process on the filter chip are reduced, namely, the manufacturing of the copper columns and the dipping of the copper columns in the filter chip are reduced, so that the manufacturing cost of the filter chip is greatly reduced.
4. The filter chip without the cavity is mounted and coated, and then is supported by the supporting part and the solder paste to form a cavity with a certain height;
5. the filter chip without the salient points is the same as a common flip chip, different chip distinguishing welding modes are not needed, the filter chip without the salient points is directly welded on the substrate through a flip technology, and the reliability of the product is improved.
6. For a common flip chip, the process of underfill glue is not needed, the reliability of the product can be met through the supporting part and the solder paste, and the filter cavity is prevented from being polluted by the underfill glue to influence the filter function.
7. The filter chip and other flip chips can be packaged by adopting the same process, so that the packaging efficiency is improved, the product reliability is improved, and the packaging cost is reduced.
Drawings
FIG. 1 is a prior art multi-device RF systemized modular package structure with filters;
FIG. 2 is a schematic diagram of a chip package structure according to an embodiment of the invention;
fig. 3 is a schematic diagram illustrating lamination of a supporting board in a chip packaging method according to an embodiment of the invention;
FIG. 4 is a schematic diagram illustrating a method of packaging a chip according to an embodiment of the invention;
FIG. 5 is a schematic diagram of plating holes in a chip packaging method according to an embodiment of the invention;
FIG. 6 is a schematic diagram illustrating a method of packaging chips according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a chip packaging method according to an embodiment of the invention;
FIG. 8 is a schematic diagram of tin printing of a chip packaging method according to an embodiment of the invention;
FIG. 9 is a schematic diagram illustrating a chip packaging method according to an embodiment of the invention;
FIG. 10 is a schematic diagram of a filter cavity formed by laminating an isolation film according to an embodiment of the present invention;
in the figure, a 1-package substrate; a 2-filter chip; 21-a filter cavity; 3-flip chip; 4-a support; 41-metal plating; 5-solder paste part; 6-isolating film; 7-plastic sealing layer; 8-supporting plates; 9-support holes.
Detailed Description
The invention will now be described in further detail with reference to the drawings and the specific examples, which are given by way of illustration only and are not intended to limit the scope of the invention, in order to facilitate a better understanding of the invention to those skilled in the art.
The radio frequency system module packaging structure with the filter comprises a packaging substrate 1, wherein a convex supporting part 4 is arranged on the surface of the packaging substrate 1, the supporting part 4 is arranged corresponding to a chip bump pad, solder paste is printed at a position corresponding to the supporting part 4 to generate a solder paste part 5, and the height of the solder paste part 5 is higher than the depth of the supporting part 2; the chip is soldered to the package substrate through the solder paste portion 5, wherein the chip is a flip chip, and at least includes the filter chip 2, the package material includes at least the isolation film 6, and the isolation film 6 covers the package substrate 1 and the surface of the chip, so that the chip and the package substrate 1 form a cavity.
In one embodiment of the invention, a chip package structure with a filter chip and other flip-chips, the other flip-chips 3 being adapted correspondingly to the function of the filter chip 2, the other flip-chips comprising a switching flip-chip, a low noise amplifier chip and/or a power amplifier chip, etc. As shown in fig. 2, the filter chip 2 and the other package chips 3 are packaged in one radio frequency system module. The filter chip 2 does not need to be manufactured with convex points and convex point tin dipping technology, and the manufacturing cost of the filter chip is greatly reduced.
In one embodiment of the present invention, the upper surface of the inner wall of the supporting portion 4 and the connection portion with the substrate are provided with metal plating layers 41, the supporting portion 4 is filled with solder paste for soldering chips, and the filled solder paste forms a solder paste portion 5 with a height greater than the depth of the supporting portion. The solder paste filled support replaces the bumps on the filter chip and the electrical connection of the chip and the package substrate 1 is achieved by the metallization 41. The salient points can be obtained without manufacturing copper columns and tin dipping process of the copper columns.
In one embodiment of the present invention, the other flip chip 3 and the filter chip 2 are soldered on the same side of the package substrate, and are soldered on the solder paste portion corresponding to the supporting portion 4. Since the selective coating is not required, the filter chip 2 and the other flip chip 3 are directly pressed by the isolation film 6, so that the filter chip 2 and the package substrate 1 form a filter cavity 21, and the other flip chip 3 and the package substrate 1 also form a cavity.
The problem that welding spots are easy to crack, tin connection and reliability failure caused by the fact that the welding positions of the chips cannot be filled with epoxy resin is structurally solved, and the packaging cost is greatly reduced.
In the embodiment of the present invention, the separator 6 is an epoxy resin film. Because the thickness of the isolation film 31 is thin, in one embodiment of the present invention, the C-gold plastic layer 7 is formed on the outside of the isolation film 31 by using a compression molding process, so that electrical protection is provided for the filter chip 2 and the other flip chip 3.
The original way of installing flip chip 3 all needs to adopt the underfill, just can solve the reliability problem of connection, but adopt in this application to fill up solder paste and chip in the supporting part and carry out the welded mode, need not the technology of underfill, just can satisfy the reliability problem of product.
The height of the supporting part is equal to the height of the chip bump, and the outer diameter of the supporting part is equal to the diameter of the chip bump.
Example 2
The embodiment also provides a chip packaging method, and the packaging method of the packaging structure with the filter chip is further described below by an application example, so that a person skilled in the art can better understand the process method of the radio frequency system module package of the invention.
S1, providing a substrate, and pressing a supporting plate on the packaging substrate;
as shown in fig. 3, a layer of support plate 8 is pressed before the package substrate 1 is used as a solder mask, and the support plate 8 is generally pressed on the surface of the package substrate 1 where chips and components are to be mounted. In one embodiment of the present invention, the support plate 8 is PP material, and the thickness of the material is equal to the height of the bump on the wafer, so that the bump will be used to support the filter chip 2. Since the package substrate 1 is also generally made of the same material as the support plate 8, the manufacturing process is equivalent to one more layer in manufacturing the package substrate 1, and the difficulty and complexity of the manufacturing process are not additionally increased.
S2, manufacturing a supporting part of the convex packaging substrate at a corresponding position of the supporting plate based on the position and the height of the chip bump pad;
the step S2 specifically comprises the following steps:
s21, drilling holes in corresponding positions of the supporting plates based on positions and heights of the chip bumps so as to obtain supporting holes 9;
in one embodiment of the present invention, as shown in fig. 4, holes are drilled on the supporting plate 8 at positions corresponding to the Bump pads to obtain supporting holes 9, where the hole diameters of the supporting holes 9 are equal to the diameters of the bumps formed on the wafer, and the manufacturing process of the supporting holes 9 is the same as the manufacturing process of the inner layer holes of the package substrate.
S22, plating metal on the inner wall of the supporting hole 9 to form a metal plating layer;
in one embodiment of the invention, copper is plated on the mounting hole walls as shown in FIG. 5. The thickness of the formed metal coating 41 has no special requirement, and the thickness is the same as that of the inner layer hole wall of the packaging substrate 1. The metal plating layer 41 is formed such that the metal plating layer 41 is formed on the inner wall, upper surface and connection portion with the package substrate 1 of the supporting hole 9.
S23, cutting outside the support hole 9 based on the support plate thickness, and peeling off the support plate 8 distributed outside the support hole 9 after the cutting, thereby obtaining the support portion 4 composed of a part of the support plate 8 and the metal plating layer 41.
In one embodiment of the present invention, as shown in fig. 6, a cut is made at the periphery of the supporting hole 9, and the outer diameter of the annular ring is identical to the diameter of the BUMP PAD, i.e., the BUMP PAD, and the cutting depth is the thickness of the supporting plate 8.
The excess plate is peeled off as shown in fig. 7, thereby obtaining a supporting portion 4 protruding from the package substrate 1, and surface treatment is performed on the grommet of the supporting portion 4 for soldering, as in the surface treatment process of the bonding pad.
Generally, the surface treatment of the annular ring is performed by processes such as ENEPIG, thin Ni ENEPIG, OSP or None Ni ENEPIG.
S3, printing solder paste on the supporting position in an SMT mode, and welding a solder paste part generated by printing the solder paste on the chip on the packaging substrate, wherein the chip is a flip chip and at least comprises a filter chip 2;
in some embodiments, in addition to the filter chip 2, further flip chips 3 are included, which further flip chips 3 are adapted to the function of the filter chip 2, which further flip chips generally comprise switching flip chips, low noise amplifier chips and/or power amplifier chips.
Solder paste is printed on the package substrate 1 at the position of the supporting portion 4 by SMT method, so that the solder paste completely fills the inside of the supporting portion 4, and a solder paste portion 5 is formed. In one embodiment of the present invention, as shown in fig. 8, the supporting portion 4 is a blind hole including a metal plating layer 41, connecting the package substrate 1 and the chip. Therefore, the solder paste is completely filled into the holes and is higher than the supporting portion 4, thereby forming a solder paste portion 5.
The bump-free filter chip 2 is directly soldered on the package substrate 1 through a flip-chip process as in the case of the conventional flip-chip 3 chip, as shown in fig. 9, improving the product reliability. In one embodiment of the invention, the filter chip 2 and other flip chips 3 are soldered to the package substrate 1 by SMT or DA equipment.
The filter chip 2 does not need to be manufactured with bumps and the bump tin dipping process, namely, the manufacturing of copper columns and the copper column tin dipping process are not needed, and the manufacturing cost of the filter chip 2 is greatly reduced.
S4, laminating the chip and the packaging substrate by using the isolating film, so that a cavity is formed between the chip and the packaging substrate.
As shown in fig. 10, the package substrate 1 to which the filter chip 2 and the other flip chip 3 are attached is subjected to lamination of the isolation film 6 so that the filter chip 2 and the package substrate 1 form a cavity. Since the other flip chip 3 is subjected to SMT soldering through the supporting portion 4, the reliability of the flip chip 3 is ensured, and the solder balls do not need to be protected and reinforced, so that the bottom of the flip chip 3 does not need to be subjected to glue filling treatment, and the filter cavity 21 is prevented from being polluted by glue filling to affect the filter function. For the filter chip 2, the height of the filter chip 2 is ensured due to the heights of the support portion 4 and the solder paste portion 5, and a filter cavity 21 having a certain height and being stable is formed with the surface of the package substrate 1.
S5, molding the device surface covered with the isolation film,
because the thickness of the isolation film is thinner, the device surface covered with the isolation film 6 needs to be subjected to plastic package molding through Compression Mold (Compression Mold process), so that a plastic package layer 7 is formed, and the filter chip 2 and other flip chips 3 are electrically protected, so that a package structure schematic diagram shown in fig. 2 is finally formed.
In some embodiments, the method further comprises the steps of completing the manufacture of the electromagnetic shielding layer by adopting sputtering, spraying, 3D printing, shielding film lamination and electroplating. And adopting spraying, sputtering 3D printing or conducting film lamination technology to manufacture the conducting metal layer.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. The above-described structure and method embodiments are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The foregoing has described only the basic principles and preferred embodiments of the present invention, and many variations and modifications will be apparent to those skilled in the art in light of the above description, which variations and modifications are intended to be included within the scope of the present invention.
Claims (5)
1. A chip package structure, comprising:
the packaging substrate is provided with a raised supporting part on the surface, the supporting part is obtained by drilling holes at the position corresponding to the bump pads of the chip on the supporting plate, and solder paste is printed at the position corresponding to the supporting part to generate a solder paste part, wherein the supporting plate is pressed on the packaging substrate and is the same as the packaging substrate in material, and the height of the solder paste part is higher than that of the supporting part; the inner wall, the upper surface and the joint of the support part and the substrate are provided with metal plating layers;
the chip is welded on the packaging substrate through the solder paste part, wherein the chip is a flip chip and at least comprises a filter chip, the supporting part replaces bumps of the chip, and the outer diameter of the supporting part is equal to the diameter of a bump pad of the chip;
and the packaging material at least comprises an isolating film, and the isolating film covers the surfaces of the packaging substrate and the chip, so that the chip and the packaging substrate form a cavity.
2. The chip package structure of claim 1, wherein the supporting portion is a blind via connecting the chip and the surface of the package substrate.
3. The chip package according to claim 2, wherein the solder paste of the solder paste portion completely fills the supporting portion and is higher than the supporting portion.
4. A packaging method based on the chip packaging structure according to any one of claims 1 to 3, characterized in that the implementation step comprises:
s1, providing a packaging substrate, wherein a supporting plate is pressed on the packaging substrate, and the supporting plate and the packaging substrate are the same in material;
s2, manufacturing a supporting part of the convex packaging substrate at a corresponding position of the supporting plate based on the position of the bump pad of the chip and the bump height;
s21, drilling holes in corresponding positions of the supporting plate based on positions of bump pads of the chip and bump heights so as to obtain supporting holes;
s22, plating metal on the inner wall of the supporting hole;
s23, cutting the outer side of the supporting hole based on the thickness of the supporting plate, and stripping the supporting plate which is distributed on the outer side of the supporting hole after cutting, so as to obtain a supporting part;
s3, printing solder paste on the supporting position in an SMT mode, and welding a solder paste part generated by printing the solder paste on the chip on the packaging substrate, wherein the chip is a flip chip and at least comprises a filter chip;
s4, laminating the chip and the packaging substrate by using the isolating film, so that a cavity is formed between the chip and the packaging substrate.
5. The method of claim 4, further comprising molding the outer side of the isolation film.
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| CN202210587480.0A CN115020396B (en) | 2022-05-25 | 2022-05-25 | Chip packaging structure and packaging method |
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| CN101114622A (en) * | 2006-07-27 | 2008-01-30 | 矽品精密工业股份有限公司 | Flip-chip type semiconductor packaging structure and chip bearing member |
| JP2009212195A (en) * | 2008-03-03 | 2009-09-17 | Panasonic Corp | Flexible printed board, method of mounting on flexible printed board, and optical pickup device equipped with flexible printed board thereof |
| US10950568B2 (en) * | 2017-05-23 | 2021-03-16 | Micron Technology, Inc. | Semiconductor device assembly with surface-mount die support structures |
| CN216120295U (en) * | 2021-10-09 | 2022-03-22 | 江苏卓胜微电子股份有限公司 | Acoustic surface filter radio frequency module packaging structure and electronic equipment |
| CN114284234A (en) * | 2021-12-16 | 2022-04-05 | 深圳新声半导体有限公司 | Packaging structure and manufacturing method for packaging structure |
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